JPH11330362A - Resistance voltage divider circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a resistance voltage divider circuit wherein the settling time difference during the sampling of each divided voltage is reduced without increasing the circuit area. SOLUTION: This resistance voltage divider circuit 1 has a unit resistor column 3, connected between a high side terminal 2A of a reference voltage and a low side terminal 2B of the reference voltage, and a first and a second resistor column 4A, 4B connected in parallel with the unit resistor column 3. The first resistor column 4A is formed by connecting a plurality of resistors R9 -R12 , which change the alternating current impedance at respective connection points C2 , C4 , C6 , in series and by connecting each resistor R9 -R12 with two unit resistors in parallel, and the second resistor column 4B is formed by connecting a plurality of resistors R13 , R14 , which change the alternating current impedance at the connection point C4 , in series and by connecting each resistor R13 , R14 with four unit resistors in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resistive voltage dividing circuit, and more particularly, to an analog-to-digital (A) circuit on a semiconductor integrated circuit.
/ D) The present invention relates to a resistance voltage dividing circuit suitable for generating a comparison reference voltage of a converter.

[0002]

2. Description of the Related Art A resistor voltage dividing circuit used for generating a comparison reference voltage of an A / D converter on a semiconductor integrated circuit generally includes a plurality of unit resistors having a certain resistance value connected in series. And outputs a divided voltage from each connection point between the unit resistors.

However, in recent years, in addition to the increase in the speed of the A / D converter, the reduction of the voltage dividing range and the improvement of the accuracy due to the reduction of the power supply voltage have been promoted. I have.

A conventional resistive voltage dividing circuit for meeting such a demand is disclosed in, for example, Japanese Patent Application Laid-Open No. 58-162859.
Publication and Reference `` IEEE JOURNAL OF SOLID-STATE CIRC
UITS, VOL. SC-20, NO. 6, DECEMBER 1985 P1138-1143 ".

[0005] The resistance voltage dividing circuit disclosed in Japanese Patent Application Laid-Open No. 58-162859 forms a plurality of resistor strings by connecting a plurality of resistors having a resistance value higher than a required resistance value in series. By directly connecting the connection points between the resistors in the resistor string and considering the combined resistance value that appears between the connection points as a necessary resistance value, the resistance value appears to be small, thereby increasing the accuracy of the absolute value of the resistor. It is to become.

FIG. 3 shows a resistor voltage dividing circuit disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 58-162859. The resistor voltage dividing circuit 1 includes a first, second, and third resistor strings 4A, 4A, between a higher terminal 2A of the reference voltage and a lower terminal 2B of the reference voltage.
4B and 4C are connected in parallel, and the connection point of each resistor is connected between the resistor columns, as shown by the broken line in the figure, and a unit resistor composed of a combined resistor having a reduced resistance value according to the number of resistor columns. 5 is constituted. The first, second and third resistor rows 4A, 4B, 4C have a higher resistance value (CΩ) than the required resistance value, and a plurality of resistors R ₁ connected in series.
To R _8, comprising a _{R 9 ~R 16, R 17 ~R} 24. With such a configuration, the resistance value of the unit resistor 5 decreases, and the precision of the absolute value of the resistor can be improved.

FIG. 4 shows a resistor voltage dividing circuit disclosed in the above document. The resistor voltage dividing circuit 1 is configured by connecting a resistor string 3 and a resistor string 4 in parallel between a higher terminal 2A of a reference voltage and a lower terminal 2B of a reference voltage, and directly connecting an intermediate potential point therebetween. It is. The resistor string 3 is composed of a plurality of resistors R ₁₃ and R _{14 having} a low series combined resistance value of the resistor string 4.
Is comprised of a plurality of resistors R ₁ to R ₈ to provide a higher resistance R _13, R ₁₄ series combined resistance value. The resistance R ₁ of the resistance row 4
The divided voltage from the connection points C ₁ "~C _7" between R ₈ is output.

[0008]

However, Japanese Patent Application Laid-Open No.
According to the conventional resistor voltage dividing circuit 1 disclosed in Japanese Patent No. 162859, in order to lower the resistance value of the unit resistor 5 composed of the parallel combined resistors, it is necessary to increase the number of parallel resistors.
When integrated, there is a disadvantage that the area on the semiconductor integrated circuit increases.

That is, assuming that the AC impedance is Z, the range of the AC impedance Z is when the unit resistor 5 is composed of 2 ⁿ (n = 1, 2, 3,...) Resistors having a resistance value of RΩ. , {(2 ⁿ -1) / 2 ⁿ ｝ R ≦ Z ≦ {2 ^(n-1) / 2} R. This indicates that the difference in the AC impedance at each voltage dividing point increases as the number of unit resistors dividing the voltage increases. It is clear that the connection point where the AC impedance becomes highest is the middle point of the partial pressure, and the AC impedance Z seen from this middle point is as follows: Z = {2 ^(n-1) / 2} R . For this reason, the connection point at which the settling is slowest among the sampled voltages at the connection points is the middle point of the divided voltage, and the settling time depends on the AC impedance at the middle point of the divided voltage. As a result, when the number of voltage divisions is determined as in the case of the comparison reference voltage of the A / D converter, in order to shorten the settling time at the middle point of the divided voltage, the AC impedance at the middle point must be reduced. Therefore, it is necessary to reduce the resistance value R, and when forming a resistor string on a semiconductor integrated circuit by regarding the combined resistance value seen from each connection point as a unit resistance value when a plurality of resistors are arranged in parallel. As the required unit resistance value decreases, the number of parallel circuits increases. As a result, the area increases according to the number of parallel circuits.

[0010] Conventional resistance voltage dividing circuit 1 shown in the above-mentioned document
According to the method described above, there is a disadvantage that the relative variation in the settling time becomes very large because the difference in AC impedance is large.

That is, as shown in FIG.
Is the unit resistance R₁₃, R₁₄Is D (Ω)
And the unit resistance R₁₃, R₁₄Each of the resistor strings 4 connected in parallel to
Resistance R ₁~ R₈Is 2 × D (Ω),
Resistance R₁~ R₈Connection point C₁"~ C_FourExchange
Impedance Z₁"~ Z_FourIs as follows: Z₁"= 55D / 36Z_Two"= 19D / 9Z_Three"= 7D / 4Z_Four"= 4D / 9. Therefore, the AC impedance Z₁"~ Z_FourAnd the maximum value of
The ratio of the minimum values is about 1: 4.75. Note that connection point C
_Five"~ C₇The calculation of the AC impedance of
₁"~ C_FourThe description is omitted because it is the same as "".
As a result, like the conversion method of the A / D converter described in the above paper,
Unit resistance R₁₃, R₁₄Connection point C between_FourDivided voltage of sun
A resistor constituting the resistor string 4 inserted in parallel with the pulling time.
Anti-R₁~ R₈Connection point Z between₁"~ C₇Of the divided voltage
If the sampling time is not different,
The disadvantage is that the relative variation between them is very large.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a resistance voltage dividing circuit which reduces a settling time difference when sampling each divided voltage without increasing a circuit area.

[0013]

According to the present invention, in order to achieve the above object, a plurality of unit resistors are connected in series to divide a reference voltage, and the divided voltage is connected to each connection between the plurality of unit resistors. In a resistive voltage dividing circuit that outputs from a point, a plurality of unit resistor groups including at least two different number of unit resistors obtained by equally dividing the plurality of unit resistors by at least two different divisors, There is provided a resistor voltage dividing circuit including a plurality of resistors connected in parallel.

[0014]

FIG. 1 shows an example of an A / D converter to which a resistance voltage dividing circuit according to a first embodiment of the present invention is applied. The A / D converter 10 is a 3-bit flash type, and has a resistance voltage dividing circuit 1 for dividing a reference voltage.
And a comparator array 11 that compares each divided voltage input from the resistance voltage dividing circuit 1 with an analog voltage input from the input terminal 11a by using seven comparators and outputs the comparison result;
A logic circuit 12 for outputting the output of the comparator array 11 as a digital output code from an output terminal 12a.

The resistor voltage dividing circuit 1 includes a unit resistor string 3 connected between the higher terminal 2A of the reference voltage and the lower terminal 2B of the reference voltage, and a first resistor string connected in parallel to the unit resistor string 3. And second resistor strings 4A and 4B.

The unit resistor string 3 is composed of a plurality of unit resistors R _{1 to} R ₈ connected in series.

The first resistor string 4A is connected to each connection point C ₂ ,
A plurality of resistors R _{9 to} R ₁₂ for changing the AC impedance of C ₄ and C ₆ are connected in series, and each resistor R _{9 to} R ₁₂ is connected in parallel to a predetermined number (for example, two) of unit resistors. Things.

The second resistor row 4B connects a plurality of resistors R ₁₃ and R ₁₄ that change the AC impedance of the connection point C ₄ in series, and connects each resistor R ₁₃ and R ₁₄ to a predetermined number (for example, 4
) Are connected in parallel with the unit resistance of (1).

Next, the operation of the first embodiment having the above configuration will be described. When the divided voltage is sampled at a certain cycle, a path for supplying a current at the time of sampling to the connection points C ₂ , C ₄ and C ₆ is added by the resistors R _{9 to} R ₁₂ of the first resistor row 4A. , The resistance R of the second resistance row 4B
_13, a path for supplying the current at the time of sampling to the connection point C ₄ by R ₁₄ is further added.

Here, a case is considered in which the divided voltages at the connection points C _{1 to} C ₄ in the upper half of the unit resistance string 3 are sampled. First, the higher side VT of the reference voltage and the lower side V of the reference voltage
If the output impedance of the voltage source supplying B can be considered to be sufficiently low for a high frequency band, it can be said that the higher side VT of the reference voltage and the lower side VB of the reference voltage are AC grounded.

At this time, the resistance R when the higher side VT of the reference voltage is viewed from the connection points C ₄ , C ₂ , C ₁ respectively.
[C ₄ ], R [C ₂ ] and R [C ₁ ] are as follows. _{R [C 4] = R 13} // (R 9 + R 10) // (R 1 + R 2
+ R ₃ + R ₄ ) R [C ₂ ] = R ₉ / (R ₁ + R ₂ ) R [C ₁ ] = R ₁ where A // B = (AB) / (A + B) Here, FIG. Thus, the unit resistance R of the unit resistance row 3
The unit resistance value of _{1 to} R ₈ is A [Ω], the resistance value of the resistors R _{9 to} R ₁₂ of the first resistor row 4A is 2 × A [Ω], and the resistances R ₁₃ and R of the second resistor row 4B are R ₁₃ and R. _{Assuming that} the resistance value of ₁₄ is 4 × A [Ω], the resistance value when the higher voltage VT of the reference voltage is viewed from the above connection points C ₄ , C ₂ , C ₁ is as follows. Become. R [C ₄ ] = 4A / 3 R [C ₂ ] = A R [C ₁ ] = A

In FIG. 1, when the divided voltages generated at the connection points C _{1 to} C ₄ are sampled at a certain cycle, the AC impedances Z _{1 to} Z ₄ seen from the connection points C _{1 to} C ₄ are sampled.
Is represented by the following equation. Z ₁ = ((((Zc // R ₁₃ ) + (R ₁₀ // (R ₃ + R ₄ ))) // R ₉ ) + R ₂ ) // R ₁ Z ₂ = ((Zc // R ₁₃ ) + (R ₁₀ // (R ₃ + R ₄ ))) // (R ₉ // (R ₁ + R ₂ )) Z ₃ = ((Zc // R ₁₃ ) + R ₄ ) // ( R ₉ // (R ₁ + R ₂ ) + R ₃ ) Z ₄ = Zc // (R ₁₃ // (R ₉ + R ₁₀ ) // (R ₁ + R ₂ + R ₃ + R ₄ )) , Zc = R ₁₄ // (R ₁₁ + R ₁₂ ) // (R ₅ + R ₆ + R ₇ + R ₈ ), A / B = (AB) / (A + B) Here, as shown in FIG. And the unit resistance R of the unit resistance row 3
The unit resistance value of _{1 to} R ₈ is A [Ω], the resistance value of the resistors R _{9 to} R ₁₂ of the first resistor row 4A is 2 × A [Ω], and the resistances R ₁₃ and R of the second resistor row 4B are R ₁₃ and R. When configured the resistance value of ₁₄ 4 × a [Ω], the AC impedance Z ₁ to Z ₄ which is visible from the connection points C ₁ -C ₄ are the values below. Z ₁ = 2A / 3 Z ₂ = 2A / 3 Z ₃ = A Z ₄ = 2A / 3 Note that the higher side VT of the reference voltage and the lower side V of the reference voltage
B can be said to be grounded in an alternating manner, so that Z ₅ =
Z ₃ , Z ₆ = Z ₂ , and Z ₇ = Z ₁ .

Here, the AC impedances Z _{1 to} Z ₄ of the _first and second resistor rows 4A and 4B when there are no resistors R _{9 to} R ₁₄ are as follows: Z ₁ = 7A / 8 Z ₂ = 3A / It is clear that 2 Z ₃ = 15 A / 8 Z ₄ = 2 A, and it is also clear that the connection point where the AC impedance is the maximum is the middle point C ₄ . This indicates that the resistance values of the unit resistors R _{1 to} R ₈ need to be halved when the maximum value of the AC impedance is made equal when the resistors R _{9 to} R ₁₄ are not present.

In addition, when sampling the divided voltage from the initial charge 0 to the capacitance having the capacitance value C, the sampling voltage when sampling at the sampling time T can be generally expressed as follows. VX = VS × {1−e ^{(−T / CR)} } (1) where, VX: voltage value sampled by the capacitor C at time T VS: divided voltage value to be sampled R: resistance value e: natural logarithm (≒ 2.7183 ...) From this equation (1), it can be seen that VX approaches VS as e ^{(−T / CR)} approaches 0. To make VX close to VS, T / CR >> 0, that is, T >> CR may be set.

Now, when the divided voltage VS is sampled, VX becomes αVS << VX <= ｛1+ (1
−α)｝ VS (however, a time (settling time) t that converges in the range of 0 <α <1) is represented by the following equation. t = ln {1 / (1−α)} × CR (2) Here, since the capacitance value C includes the parasitic capacitance of the unit resistances R _{1 to} R ₈ itself, the capacitance value C is smaller than that of the present embodiment. Is R ₉ ~
Parasitic capacitance at the node C ₁ -C ₇ between the unit resistors R ₁ to R ₈ than when there is no resistance R ₁₄ is increased. However, normally, the capacitance used for sampling the divided voltage generated by the resistance voltage dividing circuit 1 (hereinafter referred to as “sampling capacitance”) is ignored because the capacitance value is sufficiently larger than the parasitic capacitance. be able to. Therefore, assuming that the capacitance value C is constant at the capacitance value of the sampling capacitor, the settling time is proportional to the value of R, and the variation of the settling time depends on the relative variation of R. Therefore, in the present embodiment, the ratio between the maximum value and the minimum value of the AC impedance is 1: 1.5, whereas when there is no resistance of R _{9 to} R ₁₄ , the ratio is approximately 1: 2.3. As can be seen, the variation in the settling time is relatively large. Note that the lower half of the unit resistance row 3 is the same as the upper half, and a description thereof is omitted.

According to the first embodiment, the following effects can be obtained. (A) The first and second resistor strings 4A and 4B are added to the unit resistor string 3.
Are connected in parallel, and a path for supplying a current at the time of sampling can be connected to a plurality of connection points C ₂ , C ₄ , and C ₆ between the unit resistors. Dispersion can be achieved, and a monotonous increase in AC impedance at each of the connection points C _{1 to} C ₇ can be suppressed. As a result, it is possible to reduce a settling time difference when sampling each divided voltage. (B) Since the number of connection points between the resistors R _{9 to} R ₁₄ inserted in parallel and the unit resistor row 3 can be reduced as compared with the one-to-one parallel resistor voltage dividing circuit 1, the wiring area is reduced. As a result, it is possible to prevent the area on the semiconductor integrated circuit from increasing according to the number of paralleled resistors.

The present invention is not limited to the above-described embodiment, but can be variously modified. For example, in the above embodiment, the resistance value of the resistor inserted in parallel for every two unit resistors is 2 × A [Ω], but this value is not limited. Further, there is no limitation as to whether a resistor is inserted in parallel for every two or more unit resistors, or whether the number of resistors inserted in parallel with the unit resistor is three or more. However, the value of the resistor inserted in parallel is preferably a value obtained by multiplying the unit resistance value of the resistor voltage dividing circuit 1 to be inserted by the number of unit resistors included in the insertion interval. The number of parallelizations is a value of a multiplier when expressed as a power of 2 of the number of unit resistors minus one.
It is preferable that the number of parallel lines is increased, for example, the interval in the case of parallel insertion is such that the first parallel-inserted resistor row is every two and the second parallel-inserted resistor row is every four. It is preferable to increase the interval at the time of connection with the unit resistance by a power of 2 in accordance with the following equation. By making such a combination,
The possible range of the AC impedance at the connection point of each unit resistor can be minimized. In the above-described embodiment, since eight unit resistors, which are the minimum configuration of the present invention, are used, it is suitable to insert two resistor columns rather than raising to the power of two. The resistance string is
For every two unit resistors, the resistance value of the connected resistor is 2
× A [Ω] is suitable for every 4th unit resistance in the second resistance row, and 4 × A [Ω] is suitable for the resistance value of the connected resistor.

FIG. 2 shows an example of an A / D converter to which a resistance voltage dividing circuit according to a second embodiment of the present invention is applied. The resistance voltage dividing circuit 1 of the A / D converter 10 is different from the first embodiment in the value of the resistance used. That is, in the case where the resistance voltage dividing circuit 1 is constituted only by the unit resistance strings 3, the AC impedance at the middle point where the resistance value is the highest is obtained, this value is set to Z (max), and twice this value is set in parallel. The values of the resistors R _{9 to} R ₁₄ to be inserted are used, and Z (max) is used as the unit resistors R _{1 to} R ₈ . For example, as shown in FIG.
x) = B [Ω], the unit resistance of the unit resistors R _{1 to} R ₈ is B [Ω], and the resistance of the resistors R _{9 to} R ₁₄ inserted in parallel with the unit resistors R _{1 to} R ₈ is 2 × B [Ω].

Here, as in the first embodiment, the AC impedances Z ₁ ′ to Z ₄ ′ at the connection points C ₁ ′ to C ₄ ′ are set.
Is obtained as follows. Z ₁ ′ = 21 B / 32 Z ₂ ′ = 5 B / 8 Z ₃ ′ = 10 B / 11 Z ₄ ′ = B / 2 Accordingly, the ratio between the maximum value and the minimum value of the AC impedance is about 1: 1.8. Further, it can be seen from the present embodiment that the resistance voltage dividing circuit 1 has two types of resistance values.
Note that the calculation of the AC impedance at the connection points C ₅ ′ to C ₇ ′ is the same as that of the connection points C ₁ ′ to C ₄ ′, and will not be repeated.

According to the second embodiment described above, there are two types of resistance values of the resistors used in the present invention. Even if the number of divisions is large, the value of the unit resistance can be set to a sufficient value, so that the resistance voltage dividing circuit 1 can be more easily realized when implemented on a semiconductor integrated circuit. In addition, there is an effect that the value of the unit resistance can be set relatively large.

[0031]

As described above, according to the resistance voltage dividing circuit of the present invention, the difference of the AC impedance seen from the connection point of each unit resistance can be reduced, so that the settling time difference when sampling each divided voltage is obtained. Can be reduced. In addition, the number of connection points between the resistor inserted in parallel and the unit resistance row can be reduced as compared with the one-to-one parallel resistor voltage dividing circuit, so that the wiring area can be reduced. Can be prevented from increasing according to the number of parallelizations.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing an example of an A / D converter to which a resistance voltage dividing circuit according to a first embodiment of the present invention is applied.

FIG. 2 is a circuit diagram illustrating an example of an A / D converter to which a resistance voltage dividing circuit according to a second embodiment of the present invention is applied.

FIG. 3 is a circuit diagram of a conventional resistance voltage dividing circuit.

FIG. 4 is a circuit diagram of a conventional resistance voltage dividing circuit.

[Explanation of symbols]

1 resistive divider 2A high side terminal 2B low side terminal 3 units resistor array 4A first resistor array 4B second resistor string 11a input terminal 11 comparator array 12a output terminal 12 the logic circuit C ₁ -C _7, C ₁ '-C _7' high side of the low-side VT reference voltage at the connection point R ₁ to R ₈ unit resistor R ₉ to R ₁₄ resistors VB reference voltage

Claims (7)

[Claims] 1. A resistor voltage dividing circuit for connecting a plurality of unit resistors in series to divide a reference voltage and outputting the divided voltage from each connection point between the plurality of unit resistors, , A plurality of unit resistors including at least two different numbers of unit resistors obtained by equally dividing the unit resistors by at least two different divisors are provided with a plurality of resistors connected in parallel, respectively. Characteristic resistive divider circuit. 2. A resistor voltage dividing circuit according to claim 1, wherein said plurality of resistors form at least two resistor strings between two points for generating said reference voltage. 3. The resistor component according to claim 1, wherein said plurality of resistors have a resistance value according to a unit resistance value of said plurality of unit resistors and a corresponding divisor of said at least two different divisors. Pressure circuit. 4. The resistive voltage ^dividing device according to claim 1, wherein said at least two resistor strings are composed of (n-1) resistor strings when the number of said plurality of unit resistors is m (= 2 ⁿ ). circuit. 5. The (n-1) -th row of resistors is configured by resistors connected in parallel to the unit resistor group including 2 ^k unit resistors in an arbitrary k-th column. Resistor voltage divider circuit as described. 6. The resistance column of the (n-1) th column is formed by a resistor having a resistance value of 2 ^k × AΩ in a k-th column, where a unit resistance value of the plurality of unit resistors is AΩ. The resistance voltage dividing circuit according to claim 5, wherein 7. A plurality of unit resistors, wherein Z is an AC impedance of a connection point having a maximum AC impedance among a plurality of connection points between the plurality of unit resistor groups.
= BΩ as a unit resistance, and the (n−1) -th resistor row has a resistance value of 2 in an arbitrary k-th row.
6. The resistance voltage dividing circuit according to claim 5, which is constituted by a resistor having a resistance value of × BΩ.