JPH1133018A - Medical video picture processing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable processing at a high video rate to be executed without use of a high-speed CPU. SOLUTION: This medical video picture processing device presets control data in a sequence memory 31 from a CPU 27, designates and reads the head address of one unit of the control data by means of an address counter 32 during blanking period, feeds it to a video picture processing circuit 22, and imparts sequencer controlling data (CONTROL) to the address counter 32 for incrementing; these operations are repeated to execute a series of processes conforming to the control data that are input by the video picture processing circuit 22 after the blanking period.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for processing medical video images such as X-ray video images.

[0002]

2. Description of the Related Art An image used for medical examination / diagnosis is obtained using an X-ray TV fluoroscopic system or the like, and this image is digitized and subjected to various image processing.
In this case, the image processing circuit is usually directly controlled by the CPU, and the CPU is also directly controlled when shooting an image at the video rate or reproducing and displaying the image at the video rate.

[0003]

However, when the image processing circuit is directly controlled by the CPU as in the prior art, there have been problems in terms of speed and cost. That is, C
When the image processing circuit is directly controlled by the PU,
It is necessary to complete various settings required for the next processing to the image processing circuit during the blanking period between each frame of the video, and the CPU must perform a large amount of processing in a short time. No. Therefore, a heavy load is imposed on the CPU, and a high-speed CPU must be used.
In particular, higher-speed image data collection (shooting)
The higher the playback, the higher the processing speed is required.
Due to such restrictions, it is difficult to realize high-speed data collection and reproduction, and if it is necessary to cope with this, a large and expensive device must be used.

[0004] In view of the above, it is an object of the present invention to provide a medical video image processing apparatus capable of reducing the load on a CPU, performing image processing at a high rate with an inexpensive configuration.

[0005]

In order to achieve the above object, in a medical video image processing apparatus according to the present invention, a timing generating means for generating video timing, and image processing is performed at a video rate based on the timing. A series of data read out from the storage means in synchronization with a vertical synchronization signal of video timing, and set in the image processing means during a blanking period; And a central control means for storing data relating to the processing procedure of the video image in the storage means.

If data relating to the processing procedure of the video image is stored in the storage means of the video control means, a series of data is read from the storage means in synchronization with the vertical synchronizing signal, and during the blanking period, It is set in the image processing means, and after the blanking period, the image processing means performs image processing based on the set data. The central control means only needs to store the data relating to the processing procedure of the video image in the storage means of the video control means, and its timing is not restricted at all, and since the image processing means is not involved during the processing. However, even if the video rate increases, a high-speed central control means is not required. In this way, the burden on the central control means can be reduced, and an inexpensive central control means can be used even for image processing at a high video rate.

[0007]

Next, embodiments of the present invention will be described in detail with reference to the drawings. In FIG. 1, X-rays are emitted from an X-ray tube 11 toward a subject (human body) 10, and the X-rays passing through the subject 10 are made incident on an image intensifier 12 to output an optical image.
This optical image is guided to the TV camera 14 via the optical system 13. A horizontal synchronization signal HS and a vertical synchronization signal VS are sent from the video timing generator 26 to the TV camera 14, and an image signal is output from the TV camera 14 at a video rate.

This image signal is digitized by an A / D converter 21 and sent to a video image processing circuit 22. The video image processing circuit 22 performs various processes on the digitized image data, and stores the data in the frame memory 25 and outputs the same. The output processed image data is converted back to an analog video signal by the D / A converter 23, sent to the TV monitor device 24, and displayed.

[0009] The image data collection (shooting) and processing at a series of video rates are performed by various video timing signals (HS, V) generated by the video timing generator 26.
S etc.), the basic timing is synchronized. The video sequencer 30 controls a series of processes performed by the video image processing circuit 22 according to the vertical synchronization signal VS. The control data such as the sequence of this series of processing has been sent from the CPU 27 to the video sequencer 30 via the CPU bus 28 in advance.

That is, the video sequencer 30 comprises a sequence memory 31, an address counter 32, and a start address register 33. The control data sent from the CPU 27 is written to the sequence memory 31. For example, as shown in FIG. 2, this control data is Reg. Indicating the address of a control register in the video image processing circuit 22. ADR and data WR. data and sequence control data CO
It consists of three kinds of information of NTROL. A set of data set during one blanking period is a unit of SEQ, and the start address of each SEQ is SEQ. A
DR. In FIG. 2, each of the three SEQs has a start address SEQ. ADR1, SEQ. ADR
2, SEQ. It is stored from ADR3.

When the video sequencer 30 is started, first, the start address register 33 is synchronized with VS.
Is read into the address counter 32. Note that the start address register 33
The start address is written in advance by the CPU 27. Thus, the start address SEQ. ADR1 is designated by the address counter 32, so that the control data Reg.
ADR1, WR. Data1 is read, and writing to the corresponding address of the register of the video image processing circuit 22 is performed.

At this time, the address SEQ. The sequence control data CONTROL1 stored in the ADR1 is also read out, but is sent to the address counter 32. This CONTROL 1 indicates an instruction for incrementing an address, and SEQ. ADR is advanced by one step, the next address is specified, and Reg. ADR2, WR. dat
a2 is read and sent to the video image processing circuit 22. CONTROL2 read at this time also indicates an instruction for incrementing the address, and the next address is designated, and Reg. ADR3, WR. d
data3 is read and sent to the video image processing circuit 22. In this manner, the write operation is sequentially performed and the write operation to the video image processing circuit 22 is performed.
When the number reaches SEQ. ADRn is read,
The corresponding WR. data is null, and CONTROLn read at the same time is the end of this SEQ and the start address SEQ. ADR2 is shown, and when this is input to the address counter 32, the address counter 32
EQ start address SEQ. It is set to ADR2 and waits for the next VS.

When the next VS is input, the start address SEQ. A signal indicating ADR2 is output from the address counter 32, and the control data Reg. ADR, WR. da
ta and CONTROL are sequentially read and sent to the video image processing circuit 22 one after another.

On the side of the video image processing circuit 22, a series of control data is sent and set during the blanking period, and when the blanking period ends, the WR. The processing is sequentially executed according to the data.

In this manner, the setting of a set of data SEQ in the video image processing circuit 22 during the blanking period and the processing operation according to the SEQ after the blanking period are sequentially performed in synchronization with the VS. The last SEQ
Is completed and the processing operation is performed, CONTROL indicates the end of a series of sequences, and an interrupt is generated in the CPU 27 to notify the end of the series of sequences.

Therefore, after the CPU 27 first sets the control data for a series of SEQs in the sequence memory 31, the CPU 27 performs other independent processing without involving the operation of the video image processing circuit 22. Then, when a series of SEQ is completed, another series of S
The control data for the EQ is set.
Therefore, the time for setting a series of processing procedures in the sequence memory 31 of the video sequencer 30 can be performed separately from the video timing, and is not restricted by the video timing. During the execution of a series of video image processing sequences, the CPU 27 basically does not need to intervene. Therefore, even if the shooting video rate is increased, the high-speed processing capability of the CPU 27 is not questioned.
Real-time processing can be performed with an inexpensive configuration. Further, during execution of a series of video image processing sequences by the video image processing circuit 22,
The PU 27 can perform other processing.

The above description relates to one example, and it goes without saying that the present invention is not limited to this description. For example, in the above description, the case of performing video shooting and real-time image processing in synchronization with video shooting is described. However, a video signal once recorded on an image recording device or the like is reproduced at a high speed, and image processing is performed at a speed corresponding to the video signal. It is also applicable when performing. Further, the specific configuration and the like can be variously changed.

[0018]

As described above, according to the medical video image processing apparatus of the present invention, the involvement of the CPU during execution of a series of video image processing sequences is eliminated, thereby greatly reducing the load on the CPU. Even when processing is performed at a high video rate, it can be configured using an inexpensive CPU.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is a schematic diagram showing data stored in a sequence memory.

[Description of Signs] 10 Subject 11 X-ray tube 12 Image intensifier 13 Optical system 14 TV camera 21 A / D converter 22 Video image processing circuit 23 D / A converter 24 TV monitor device 25 Frame memory 26 Video timing generator 27 CPU 28 CPU bus 30 Video sequencer 31 Sequence memory 32 Address counter 33 Start address register

Claims (1)

[Claims] 1. A timing generating means for generating video timing, an image processing means for performing image processing at a video rate based on the timing, a storage means for storing data relating to a processing procedure of a video image in advance, and a video timing A video control means including means for reading out a series of data from the storage means in synchronization with a vertical synchronization signal and setting the data in the image processing means during a blanking period; and storing data relating to a processing procedure of a video image in the storage means. A medical video image processing apparatus, comprising: a central control unit.