JPH11328109A - Communication device, phase shift detecting method, and storage medium - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a communication device, a phase shift detecting method and a storage medium which enable a very simple serial communication means where data length is composed of only transfer information to decide an informa tion array phase shift of transfer information by monitoring a serial transfer clock state without adding any bit for detecting a phase shift in serial informa tion from periodic noise. SOLUTION: This device has a 1st counter means 112 which uses a serial transfer clock as a count source, a slave station communication processing control means 113 which sends a feedback signal to a master station if a count value reaches a set value, a 2nd counter means 114 which uses the serial transfer clock as a count source, a sending-back means 115 which sends a feedback signal back to the master station each time the count value reaches the set value, and a transfer clock cycle monitor means 111 which detects a phase shift of the serial transfer clock that it generates.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a communication apparatus, a phase shift detecting method, and a storage medium, and more particularly, to the exchange of input / output information between a central processing unit of an apparatus and electric units scattered in the apparatus. The present invention relates to a communication device to be executed, a phase shift detection method, and a storage medium.

[0002]

2. Description of the Related Art Conventionally, a serial communication device in a device is referred to as a main device of serial communication called a master station of a central processing unit of the device and a slave station of a plurality of electric units scattered in the device. It exchanges information with a serial communication sub-device, and has been used in many devices for the purpose of suppressing the cost of the device and the ease of assembling the device. Initially, commercially available communication ICs were used, and logic ICs were used to configure the master and slave circuits. Eventually, with the progress of the gate array, both the master station and the slave stations have been changed to the configuration using the gate array IC. When the scale of the CPU that controls the entire apparatus is expanded,
The CPU of the central processing unit has the master station configuration, and only the slave station configuration has been made into a gate array IC.

However, basically, the information exchange configuration in the serial communication device is based on the fact that the master station and each slave station are one-to-one from the data length of the serial transfer data executed by the master station and each slave station. The corresponding data was found and processed. In other words, when performing information exchange between the master station and each slave station, the slave station address individually set to distinguish the type of slave station is combined with the information exchange data to constitute the data length of the serial transfer data. Met. Therefore, after allocating the addressing of the slave station according to the number of slave stations (the distinction of each slave station by the absolute address), the data length in the serial communication device is configured, and the number of bits for executing the data processing of the slave station circuit is determined. Was something.

On the other hand, the number of slave stations for each apparatus varies depending on the scale of the apparatus, such as a large number of required stations and a small number of stations. By unifying the number of bits of the slave station address of the serial communication device,
When a common serial communication device is used, the load may be heavy depending on the device and the communication performance depending on the device. Therefore, since it is more advantageous to design a slave station configuration according to the scale of the device as a whole device, the serial communication device has been designed as a customized device according to each device to be used.

[0005] As the price competition for the apparatus intensifies, the cost of the apparatus must be further reduced and the development period of the apparatus must be shortened. By using serial communication devices that can be used and shared by various devices, mass production of slave array gate array ICs will be achieved to further reduce costs and shorten the period of device development by diverting serial communication devices. , Came to aim for stability of reliability. Therefore, the basic control means for serial communication by the master station CPU is unified, and a control configuration capable of coping with the control of the number of slave stations required for each device by a simple software change. Also, a serial communication device has emerged in which the slave station gate array IC has a circuit configuration that can be used in any device without any design change.

That is, a gate array IC constituting a slave station
In order to make a serial communication device that can be used by any device, a slave station address for executing information processing between a conventional master station and each slave station is configured by an absolute address, and is basically set by a relative address. With this configuration, a serial communication device capable of executing a slave station address (hereinafter simply referred to as an identifier) and information exchange data in a fixed bit number configuration is provided. As a result, even when the number of slave stations used for each device is different, serial communication can be performed without changing the data processing bit number of the slave circuit. In this configuration using relative addresses, the absolute address is not simply replaced with the relative address, but based on the arrangement order of the slave stations connected to the serial communication transmission line, the permutation combination is combined with the relative address. It is distinguished by judging. That is,
This is a means by which the number of slave stations that vary in various devices can be determined by an identifier composed of a fixed number of bits.

Hereinafter, this type of serial communication device will be briefly described. Although a serial communication device according to a conventional example and an embodiment of the present invention to be described later will be described as being used in an electrophotographic device, it is not particularly limited to an electrophotographic device.

In an electrophotographic apparatus, for example, an apparatus intended for black-and-white printing has an electric unit (hereinafter, collectively referred to as a main unit) which is at least necessary to execute black-and-white printing. In addition, based on this apparatus, an extended electric unit for full-color printing, an additional electric unit such as a paper feeder and a paper ejector of the apparatus, or an additional electric unit for double-sided printing, etc. Although there is no problem, an electric unit (hereinafter, referred to as an optional unit) that can be added to expand the device or improve the usability of the device. Collectively includes both cases). In other words, each slave station connected in the transmission path of the serial communication device is always allocated to either the main unit or the optional unit, and the slave station in the transmission path allocated to the main unit is used to operate the device. Is an absolutely necessary electrical unit, and is always connected in the transmission path of the serial communication device.

If the electrophotographic apparatus is composed of only the main unit, each slave station of the main unit connected to the transmission line of serial communication is distinguished mainly by the arrangement order in which the slave units are connected to the transmission line. The data is stored in the memory map table expanded in the memory of the station CPU, and it is possible to determine even if there is no identifier by corresponding to the order of serial transfer, so that one-to-one data processing can be performed between the master station and each slave station. In other words, the master station can set in advance in the memory map table the order of what main unit exists for each slave station of the main unit. Next, in the case where optional units are mixed, if it can be determined from the arrangement order of the main unit that the number of the main unit is the number of the optional unit after the number of the main unit, all the units existing in the electrophotographic apparatus are determined. It is possible to understand the arrangement order of the electric units.

That is, in the case of the main unit, the identifier assigned to the slave station is set with a specific value, and the remaining values are assigned to the option units. Thus, it is determined whether or not the unit is the main unit based on the sucked identifier. In the case of the main unit, the number of the main unit can be recognized by a preset memory map table. At the time of an optional unit, the optional unit corresponding to the value indicated by the identifier may be recognized based on the immediately preceding main unit number. For example, if the identifier sucked after the time when the main unit indicates the third indicates not the main unit but the fifth, it can be determined that the fifth optional unit after the third main unit exists.

Then, as long as the next sucked identifier is not a specific value indicating the main unit, the existence of all the optional units following the third main unit can be determined. The presence / absence of all option units that may exist after one main unit ends when the next identifier to be extracted indicates the main unit. Further, if the sucked identifier is the main unit and the next sucked identifier is the main unit, it is determined that there is no optional unit therebetween. Thus, even if the identifiers indicating the option unit numbers are the same, all slave stations can be distinguished if the arrangement order numbers of the main units do not overlap.

In other words, an identifier composed of a fixed number of bits is also determined in combination with the arrangement order according to the number of main units existing in the transmission path, and theoretically, a semi-infinite number Can be determined. For example, if the number of identifier bits is fixed at 4 bits, the number of slave stations that can be connected in the transmission path is 16 if allocated with absolute addresses.
In the allocation based on the arrangement order and the relative addresses, up to 15 optional units can be connected to one main unit by subtracting the specific value indicating the main unit. Then, the number of optional units multiplied by the number of main units (if there are ten main units, a total of 10 + 150 slave stations can be determined) can theoretically be connected in the transmission path.

Based on the above, a specific example of control for distinguishing all slave stations in the master station will be described. When the configuration of the electrophotographic apparatus is determined, the order in which all slave stations can be connected to the transmission line of the serial communication apparatus is also determined. . As a result, in the memory of the master station CPU, there is a slave station connected in the transmission path without distinction between the main unit and the optional unit, and the memory map according to the order of all slave stations arranged in full specifications that can be connected. Set up the table. If the arrangement order of the slave stations according to the full specification is changed during the development, the arrangement order of the slave stations in the memory map table may be updated accordingly.

Then, serial communication is executed during an initialization operation of the electrophotographic apparatus when the apparatus actually operates, and
According to the arrangement order of all slave stations connected to the current transmission line, according to the arrangement order of all slave stations, only the identifier of each slave station is sucked, and it is set in advance while determining whether or not there is an optional unit in the arrangement order of all slave stations in full specifications that can be connected. Initialization serial communication is executed in order to reset the memory map table to the arrangement order of all slave stations in the current full specification. The subsequent serial communication basically corresponds to the rearranged arrangement order of the memory map table, and may execute the normal serial communication, which is information exchange of only serial transfer data with each slave station.

Thus, the serial communication device can determine all slave stations connected in the transmission path without limitation even if the number of bits of the identifier is fixed. Since the number of bits of the identifier can be fixed, a serial communication device common to all devices can be realized with the following configuration.

First, in order to configure the slave station with the minimum number of fixed bits, an identifier and information data are serially communicated in another dimension. As a result, the length of data to be serially transferred is shortened, the communication time per operation is shortened, and the number of bits to be processed in one serial communication is reduced. realizable. In other words, by making the number of processing bits of the identifier and the information data the same fixed number of bits, the basic configuration of the slave station circuit is basically a serial / parallel conversion circuit including a shift register circuit with a fixed number of bits and an input / output latch circuit. It will be. Although the fixed number of bits is not particularly limited, the 4-bit configuration makes it possible to simplify the gate array IC with a more efficient circuit configuration, and to mass produce cheaper ones. become.

Next, the transmission path form of the serial communication device is as follows.
Since the serial / parallel conversion circuit is used as a base, the serial transfer data is sequentially transferred in synchronization with the serial transfer clock starting from the master station CPU, and is sequentially shifted and transferred to a plurality of slave stations connected in series in the transmission path. Let it. Then, it is constituted by a ring-shaped loop transmission path which is shifted to the main station again. On the other hand, if each slave station sets serial return data to the master station in its own shift register before the shift operation, the slave station is configured by a loop transmission path that is shifted to the master station again. Is transmitted to each slave station, and at the same time, serial return data from each slave station is shifted and transferred to the master station.

Finally, the master station has control software for executing the control for increasing or decreasing the number of slave stations with the contents described above and a memory area, and also performs serial communication of an identifier and information data in another dimension. For this purpose, a timing instruction for serial communication processing by serial / parallel conversion at each slave station is basically controlled by an instruction signal controlled by the master station. Specifically, the operation of the latch circuit of each slave station and the operation control such as data loading and data shift of the shift register circuit are controlled by an instruction signal issued from the master station, and the master station operates as a slave station. Is configured to be controlled by remote control. As a result, the serial communication control by the master station is divided into an initialization serial communication means for sucking up the identifier of the connected slave station and a normal serial communication means for exchanging information data with the connected slave station.
The configuration is such that serial communication is executed independently in time series.

In the serial communication device having the above configuration, the basic control means for serial communication by the master CPU can be unified, and the control of the number of slave stations required for each device can be dealt with by a simple software change. In addition, the slave gate array IC has a circuit configuration that can be used in any device without changing the design. As a result, the gate array IC can be used in various devices and can be used in common.
In addition to mass production of, a further reduction in cost has been achieved, and it has become possible to reduce the time required for device development and to stabilize reliability by diverting serial communication devices.

[0020]

However, the above-mentioned prior art has the following drawbacks.
That is, as a fundamental problem in serial communication, there is information corruption of transmission information content which can occur when device noise jumps into a serial transmission path. In other words, since serial information is read and written in synchronization with the serial communication transfer clock, if device noise enters the serial transfer clock line, signal processing is performed for the slave station as if a single clock was added. To become
That is, the actual serial information content is processed with a one-shot deviation.

On the other hand, device noise can be roughly divided into a case where it occurs randomly and a case where it has periodicity.
The latter device noise having periodicity is a noise component that can be generated by a switching operation of a certain constituent circuit, and emits a noise component when a pre-designed circuit performs a circuit operation at a predetermined timing. It has periodicity because it occurs when jumping into another circuit. This periodic device noise is usually corrected and improved at the stage of device design and will not occur.However, in rare cases, it may occur intermittently. Needs to be addressed in advance.

In the case of a normal serial communication device, as a measure against information corruption caused by device noise generated at random, the serial information content is read twice and compared to determine whether it is true or false, or a parity bit is provided in the serial information content. (If the slave station is composed of a hardware circuit, the former method of confirming the authenticity of the information content by double reading comparison is usually adopted.)
As a result, random device noise jumps into the serial transfer clock, and even if the information phase of the serial information content is shifted, the authenticity of the information content can be easily detected and determined.

On the other hand, a device noise having a periodicity (hereinafter referred to as a device noise)
In most cases, the means for preventing information corruption that can be caused by periodic noise can be determined by the above-described means for reading information twice. A problem arises when they occur synchronously in phase. In other words, when the serial information contents are read twice, when the information is garbled in synchronization with the same phase of the first serial information contents and the second serial information contents, the comparison results match, and the serial information contents become identical. Is determined to be true. This periodic noise is usually dealt with by providing a phase shift detecting means in the data length configuration of the serial information.

That is, a start bit and an end bit are provided in the data length configuration received by one slave station, and several bits are provided.
Be able to check the beginning and end of the data length. As a result, even if the transfer information is shifted due to device noise and the like, and the reading unit is not caught twice, if the start bit and the end bit satisfying the condition do not exist at a predetermined position, the serial It is possible to determine that noise has jumped into the transfer clock and a phase shift has occurred in the information content. As described above, in the general serial communication device, the garbled information of the serial information due to the device noise jumping into the serial transmission line can be determined in each slave station by analyzing the read information.
The transmission of erroneous information can be prevented beforehand.

However, in the case of the serial communication device as described in the conventional example, the basic configuration is configured as a shift register, and only the serial information is shifted in synchronization with the serial transfer clock generated from the master station. This is an extremely simple serial communication means in which each slave station unconditionally latches and reads information as information addressed to itself at a predetermined timing. For this reason, as means for preventing information corruption due to randomly generated device noise, double reading and comparing means of serial information content can be used, but since there is no means for the start bit and end bit for periodic noise, However, there is a disadvantage in that there is no means for determining the phase detection as to whether or not the read serial information content is corrupted.

If a bit for detecting a phase shift is added to the serial information, the number of signal processing bits increases, so that the scale of the serial transfer circuit, which occupies most of the slave station circuit configuration, increases, and the cost increases. In devices where a large number of slave stations hang in the serial transmission path due to an increase in the number of transfer bits or
This is disadvantageous in that a single communication time becomes longer or the performance of the serial communication device in another sense is deteriorated.

The present invention has been made in view of the above points, and monitors the serial transfer clock state without adding a bit for detecting a phase shift in the serial information with respect to periodic noise. A communication device that can determine the information array phase shift of transfer information due to periodic noise even with extremely simple serial communication means whose data length is configured with
It is an object to provide a phase shift detection method and a storage medium.

[0028]

According to one aspect of the present invention, there is provided a communication apparatus in which a master station and a plurality of slave stations are connected via a loop-type transmission line. First counter means using a serial transfer clock synchronized with transfer of serial information to be generated as a count source, second counter means using the serial transfer clock as a count source, and counting of the first and second counter means Transfer clock cycle monitoring means for detecting a phase shift of a serial transfer clock generated by itself based on the operation.

According to a second aspect of the present invention, the first counter means is provided in each of the slave stations, and the counting operation is controlled by an instruction signal from the master station. Has at least one and counts the total number of the serial transfer clocks. The phase shift of the serial transfer clock is detected.

In order to achieve the above object, a third aspect of the present invention is to provide a feedback signal for notifying a phase timing to a master station when a count value of the first counter means reaches a set value, and to provide a feedback signal to a slave station. Slave communication processing control means for executing a series of serial communication operation processing, and return means for returning a feedback signal to the master station every time the count value of the second counter means reaches a set value. I do.

According to a fourth aspect of the present invention, the second counter means is provided in each of the slave stations, and the transmission line is generated by the transfer clock cycle monitoring means at predetermined intervals. And a plurality of feedback signals generated from each slave station are transmitted as a single signal to the master station. The phase shift of the serial transfer clock of each slave station is detected based on the state of a signal transmitted by one signal via the slave station.

According to a fifth aspect of the present invention, the second counter means includes a slave station connected to the farthest point of the transmission line, wherein the transmission line monitors the transfer clock cycle. Means for transmitting a phase timing generated every predetermined period to the means, wherein the transfer clock cycle monitoring means determines a phase of a serial transfer clock in the transmission path based on a signal state transmitted through the transmission path. It is characterized by detecting a shift.

In order to achieve the above object, the invention according to claim 6 is characterized in that the second counter means has a slave station connected to an arbitrary point on the transmission line, and the transmission line has the transmission clock cycle. A transmission line for transmitting a phase timing generated every predetermined period to a monitoring unit, wherein the transfer clock cycle monitoring unit is configured to transmit a serial transfer clock in the transmission line based on a signal state transmitted through the transmission line. The phase shift is detected.

According to a seventh aspect of the present invention, the second counter means is provided in the master station, and the slave station communication processing control means is provided with a slave station located last in the transmission path. Either the serial transfer clock passed through or the serial transfer clock to the farthest slave station in the transmission path is fed back to the master station, and the transfer clock cycle monitoring means counts the returned serial transfer clock to a count source. The phase operation of the serial transfer clock in the transmission path is detected by calculating the phase timing for each predetermined period by the counting operation described above.

In order to achieve the above object, the invention according to claim 8 is characterized in that the master station is a serial communication main device included in a central processing unit of a device equipped with a communication device main body, and the slave station communicates with the slave station. It is a serial communication sub-device provided in the electric units scattered in the device equipped with the device main body.

In order to achieve the above object, a ninth aspect of the present invention is a method for detecting a phase shift in a communication apparatus in which a master station and a plurality of slave stations are connected via a loop transmission path.
A first counter step using a serial transfer clock synchronized with the transfer of serial information issued from the master station as a count source, a second counter step using the serial transfer clock as a count source, and the first and second counters And a transfer clock cycle monitoring step of detecting a phase shift of a serial transfer clock generated by itself based on a step counting operation.

According to a tenth aspect of the present invention, the first counter step is provided in each of the slave stations, and the counting operation is controlled by an instruction signal from the master station. Has at least one and counts the total number of the serial transfer clocks. The phase shift of the serial transfer clock is detected.

To achieve the above object, the invention of claim 11 is to provide a feedback signal for notifying a phase timing to the master station when the count value of the first counter step has reached a set value, and to provide a feedback signal to the slave station. Slave communication processing control step of executing a series of serial communication operation processing,
A returning step of returning a feedback signal to the master station every time the count value of the second counter step reaches a set value.

According to a twelfth aspect of the present invention, the second counter step is provided in each of the slave stations, and the transmission line is generated every predetermined period by the transfer clock cycle monitoring step. And a plurality of feedback signals generated from each slave station are transmitted to the master station as one signal, and in the transfer clock cycle monitoring step, the transmission path is transmitted through the transmission path. The phase shift of the serial transfer clock of each slave station is detected based on the signal state transmitted by one signal via the slave station.

According to a thirteenth aspect of the present invention, the second counter step includes a slave station connected to the farthest point of the transmission line, wherein the transmission line monitors the transfer clock cycle. A transmission path for transmitting a phase timing generated every predetermined period to the step, wherein the transfer clock cycle monitoring step includes the step of: determining a phase of a serial transfer clock in the transmission path based on a state of a signal transmitted through the transmission path. It is characterized by detecting a shift.

In order to achieve the above object, the invention according to claim 14 is characterized in that the second counter step is provided by a slave station connected to an arbitrary point on the transmission line, and the transmission line is connected to the transmission clock cycle. A transmission path for transmitting a phase timing generated every predetermined period to a monitoring step, wherein in the transfer clock cycle monitoring step, a serial transfer clock in the transmission path is transmitted based on a signal state transmitted through the transmission path. The phase shift is detected.

In order to achieve the above object, the invention according to claim 15 is characterized in that the second counter step is provided in a master station, and in the slave station communication processing control step, a slave station located last in the transmission path is identified. Either the serial transfer clock passed through or the serial transfer clock to the farthest slave station in the transmission path is fed back to the master station. In the transfer clock cycle monitoring step, the returned serial transfer clock is counted by a count source. The phase operation of the serial transfer clock in the transmission path is detected by calculating the phase timing for each predetermined period by the counting operation described above.

To achieve the above object, the invention of claim 16 is the invention wherein the master station is a serial communication main device included in a central processing unit of a device equipped with a communication device,
The slave station is a serial communication sub-device of an electric unit scattered in a device equipped with a communication device.

In order to achieve the above object, an invention according to claim 17 is a program for executing a phase shift detecting method applied to a communication apparatus in which a master station and a plurality of slave stations are connected via a loop transmission path. A storage medium readable by a stored computer, wherein the phase shift detection method includes:
A first counter step using a serial transfer clock synchronized with the transfer of serial information issued from the master station as a count source, a second counter step using the serial transfer clock as a count source, and the first and second counters And a transfer clock cycle monitoring step of detecting a phase shift of a serial transfer clock generated by itself based on a step counting operation.

[0045]

Embodiments of the present invention will be described below with reference to the drawings.

[1] First Embodiment FIG. 1 is a functional block diagram showing a configuration of a main part of a serial communication device according to a first embodiment of the present invention and corresponding to the claims. . The serial communication device according to the first embodiment of the present invention includes a master station 1 and a plurality of slave stations 2-.
.., 2-n.
The master station 1 includes a transfer clock cycle monitoring unit 111, and the slave stations 2-1 and 2-2,..., 2-n include a first counter unit 112, a slave station communication processing control unit 113, 114 and return means 115.

The first counter means 112 uses a serial transfer clock generated in synchronization with the transfer of serial information generated from the main station as a count source, and performs a count operation in response to an instruction signal generated from the main station. Is controlled. When the first counter means 112 reaches a preset count value, the slave station communication processing control means 113 issues a feedback signal notifying the master station of the phase timing, and also performs a response to the serial information of a series of serial communication in the slave station. The operation processing of the serial communication is executed as timing for executing the predetermined signal processing. The second counter 114 counts the total number of input serial transfer clocks using the serial transfer clock as a count source. The return means 115 is the second counter means 11
A feedback signal is returned to the master station every time the count value of 4 reaches a preset value. The transfer clock cycle monitoring means 111 detects a phase shift of the serial transfer clock generated by the transfer clock cycle monitoring means 111 based on a feedback signal returned from the return means 115 at a phase timing every predetermined cycle.

It should be noted that the second counter means 114 may be constituted by a plurality of slave stations individually, may be constituted by a slave station connected to the farthest point of the serial communication transmission line, or may be constituted by a serial communication transmission line. The slave station connected to an arbitrary point on the road may have the configuration or the master station may have the configuration. Second embodiment of the present invention described below
In the embodiment, the second counter means 114 is provided in a serial communication transmission line. In a third embodiment of the present invention described later, the second counter means 114 is provided in the main station.

FIG. 2 is a block diagram showing a circuit configuration of a slave station of the serial communication device according to the first embodiment of the present invention. The slave station of the serial communication device according to the first embodiment of the present invention includes an input selector circuit 201, an input latch circuit 2
02, a shift register circuit 203, a double read latch circuit 204, an output latch circuit 205, a clock number counter circuit 206, a phase control counter circuit 207, a count value decode circuit 208, a multi-input AND circuit 209, and a gate logic group 210. It has become. The configuration illustrated in FIG. 2 is an example, and the configuration is not limited to the illustrated configuration.

The input selector circuit 201 has a parallel input A,
Select one of the parallel inputs B. Input latch circuit 202
Holds the input from the input selector circuit 201. The shift register circuit 203 performs transfer of serial information. The twice-read latch circuit 204 holds the first data of the serial information read by the shift register circuit 203 in the serial communication operation, and
Is compared with the second serial data read.
The output latch circuit 205 is written when the data contents match as a result of the comparison, and outputs the data as a parallel output. In this case, the comparison circuit for the first data and the second data is constituted by an exclusive OR circuit (hereinafter, abbreviated as an EXOR circuit), but is included in the double read latch circuit 204 in FIG. The configuration is not shown particularly.

The clock number counter circuit 206 corresponds to the second counter means in the present invention, and uses a serial transfer clock generated in synchronization with the transfer of serial information generated from the main station as a count source. The phase control counter circuit 207 corresponds to the first counter means in the present invention, calculates the processing timing of the serial communication control signal in the slave station, and outputs a predetermined timing pulse by the count value decoding circuit 208. Instructs execution of serial communication signal processing. The count value decoding circuit 208
Outputs a predetermined timing pulse. The multi-input AND circuit 209 combines the serial communication processing execution phases in the slave station into one timing output signal and returns the same as a feedback signal to the master station. The gate logic group 210 includes:
A predetermined circuit processing condition is added based on the timing selected by the count value decoding circuit 208.

In the first embodiment of the present invention, for ease of explanation, the configuration of the slave station is shown as a 4-bit configuration, but may be 8 bits, and the number of bits is not particularly limited.

FIG. 3 is a block diagram showing a system configuration of the serial communication device according to the first embodiment of the present invention. The serial communication device according to the first embodiment of the present invention includes a master station 320 and a plurality of slave stations 321, 322, 32.
3, 324. Note that the configuration illustrated in FIG. 3 is an example, and the configuration is not limited to the illustrated configuration.

A transmission line is formed between the master station 320 and the plurality of slave stations 321, 322, 323, and 324 having the configuration shown in FIG. 2 in the form shown in the figure.
Feedback control signals output from the slave stations 321 to 324 to the master station 320 are connected in a wired OR configuration as shown in the figure.

Before explaining the operation of the serial communication device according to the first embodiment of the present invention, the slave station of the serial communication device according to the first embodiment of the present invention shown in FIG. The circuit configuration will be briefly described along the flow of data.

The input selector circuit 201 determines the information designated from the parallel input information (indicated by the parallel inputs A and B in the figure) of a plurality of slave stations (the parallel inputs A, B depending on whether or not the information load instruction is resetting the communication). B is selected) to the input latch circuit 202 configured in the next stage. The input latch circuit 202 latches and holds at the rising edge of the serial transfer clock input when the count value output from the phase control counter circuit 207 is 00H.
03 load data. Although not particularly shown, the input latch circuit 202 is connected to an EXOR circuit in a configuration in which an input and an output correspond to each other on a bit-by-bit basis, and an EXOR output of each bit is a multi-input OR circuit. It is gated and returns an output indicated by REQ in the figure to the master station as a communication request signal.

The above-mentioned communication request signal is generated when the input information of the slave station transferred to the master station is updated. The transfer request data latched at the output of the input latch circuit 202 and the transfer completion data of the input latch circuit 202 are output. By comparing the current parallel input data transmitted to the input one by one for each of the same bits, it is possible to detect whether or not the result transferred to the master station and the current input signal state have been updated. Therefore, EX is updated when any one of the input / output signal states is updated.
The OR circuit is in a mismatched state, and the communication request signal R
It is configured to set an EQ signal. It is configured as a control signal that is fed back to the master station as a communication request signal.

When the count value output from the phase control counter circuit 207 is 00H or 06H, the shift register circuit 203 loads the data latched and held by the input latch circuit 202 at the falling edge of the serial transfer clock. After that, execute the first shift operation,
The serial transfer data is read twice and latched and held in the latch circuit 204. Next, the second shift operation is performed after 06H, so that the double read latch circuit 2 located at the next stage is performed.
It is possible to compare the serial transfer data of the first shift operation latched and held in 04 with the serial transfer data of the second shift operation for each bit.

Although not shown, this detection circuit is connected to the double read latch circuit 204 by an EXOR circuit in a one-to-one bit correspondence configuration, and an EXO circuit for each bit is provided.
R output is gated by a multi-input AND circuit, and OUT
It is expressed as the output indicated by. As a result, if they match, it can be determined that communication has succeeded, and the data is latched and held in the output latch circuit 205. If they do not match, it is determined that communication has failed, and a timing output signal is output at the timing when the count value of the phase control counter circuit 207 is 0DH, and a serial communication error is transmitted to the master station. In other words, when all bits of the serial transfer data from the master obtained in the second time match the contents obtained in the first time, it is determined that the serial communication result is true, and the output latch circuit located at the final stage 205
Are output in parallel as output at the slave station.

Next, control signals between the master station and the slave stations of the serial communication apparatus according to the first embodiment of the present invention shown in FIG. 3 will be briefly described.

As shown in FIG. 3, the present serial communication device
Starting from the master station 320, a plurality of slave stations 321, 322,
323,... Are respectively connected to signals. The data shift signal, which is a serial transfer data signal, starts from the shift-out of the master station, is connected to the shift-in of the next slave station, and passes from the shift-out of the slave station to the shift-in of the next slave station. , And finally forms a loop-type transmission line that is looped back to the main station shift-in. Accordingly, if the slave station information is set in advance for each slave station in the serial transfer data signal, the slave station can simultaneously absorb the slave station information by shift transfer from the master station to each slave station. It is needless to say that if there is a dummy shift operation in control, data obtained by the shift may be ignored.
Further, even if the slave station information is not set in advance, the slave station information absorption shift transfer may be executed after the shift transfer from the master station to each slave station, and the shift timing of the serial transfer data is not particularly limited.

On the other hand, the instruction control signal from the master station to each slave station for instructing the operation is a system reset signal, a communication reset signal, an instruction signal for instructing the counter circuit to perform a counting operation at the slave station, and serial transfer data for shift transfer. The four types of transfer clock signals are all connected in parallel from the main station. The system reset signal is used to unconditionally reset the slave station circuit operation to zero and stop it. The communication reset signal is used to initialize some of the slave station circuit operations during the execution of the communication operation. Used for operations and the like. The instruction signal is connected to an enable terminal for controlling the count operation of the phase control counter circuit 207 for controlling communication timing detection of each slave station. The transfer clock signal is a shift clock used when performing a transfer shift of serial transfer data, but is also connected to the clock number counter circuit 206 and used as transfer clock monitoring means as in the present embodiment.

The control signal fed back from the slave station to the master station includes a timing output signal for transmitting a communication processing control phase in the slave station, a communication request signal for transmitting a communication request generated in the slave station to the master station, Counts the total number of transfer clocks received by the controller, and outputs three types of clock number output signals for notifying the phase to the master station in a predetermined cycle. As a system, four types of slave station control signals and three types of feedback control signals are serially transferred. It is positioned other than the data signal. The three types of feedback control signals are independently connected to the main station in one wired OR configuration for each signal type.

As described with reference to FIG. 2, the communication request signal is a buffer which forms a wired OR when any one bit of the data content before and after the transfer detected by the input latch circuit 202 changes. Turn on.
The communication request signal of each of the plurality of slave stations is connected to the master station as one transmission signal in a wired OR configuration, and any one of the communication request signals of the plurality of slave stations is turned on. The main station is notified that there is a communication request.

On the other hand, the timing output signal is outputted at a preset phase at the timing counted by the phase control counter circuit 207 described above. In this embodiment, the slave station data transmitted to the master station is
03, the first data transferred from the master station is read twice and stored in the latch circuit 204 at 00H.
At the time of H, at the time of 0CH at which the second data shift transferred from the main station is completed, each is turned on. Also, as a result of comparing the first and second data contents transferred from the master station,
Each timing is set at 0DH to be turned on when they do not match.

Thus, the main station changes the ON phase with respect to 00H, 06H, and 0CH, which are always turned on when a predetermined timing comes, based on the count value of the first main station counter means of the main station. To check. Normally, when there is no error, all the slave stations are turned on at the same time, so they are not turned on at another timing. Conversely, if there is a timing error in any of the slave stations, some slave stations are turned on at another timing, so that it can be seen that a transfer shift error due to noise or the like has occurred. When the signal is turned off without an error, such as 0DH, the signal is turned on even if there is only one error in the slave station, so that it can be seen that a transfer shift error has occurred. Therefore, the timing output signal is 00
If the master station confirms ON only at the timings of H, 06H, and 0CH and detects and confirms that it does not turn on at other timings, it is possible to determine whether or not communication processing control in all slave stations is normal.

Next, the operation of the serial communication device according to the first embodiment of the present invention in a slave station circuit configuration will be described with reference to FIG. FIG. 4 is a timing chart showing an operation of the serial communication device according to the first embodiment of the present invention in a slave station circuit configuration. In the present embodiment, the transfer shift operation is basically performed twice by serial communication performed once.

When starting the serial communication, the master station first issues a communication reset to take the phase of the communication operation processing in the slave station, and resets the count value of the phase control counter circuit 207 as the slave station communication processing control means. Clear to zero.
As a result, it becomes possible to load new transfer data into the shift register circuit 203 that transfers slave station information. The communication request signal is transmitted to the shift register circuit 203.
It is needless to say that, when new transfer data is loaded, the latch is updated by the input latch circuit 202, and is automatically released at that timing. In other words, the master station checks the communication request signal after completing the serial communication and prepares for the next serial communication. Needless to say, if the necessity of serial communication arises due to master station control, serial communication is executed regardless of the communication request signal. Even at that time, the communication request signal is latched and updated by the input latch circuit 202, so that it is automatically released at that timing.

When the count value of the phase control counter circuit 207 becomes 00H, the parallel input information of the slave station is latched and held at the rising edge of the serial transfer clock input thereafter, and at the falling edge of the clock. The latch data is loaded into the shift register circuit 203. Then, the master station turns on the instruction signal to execute the count operation, and issues the next serial transfer clock. Even if the next serial transfer clock is issued while the instruction signal is off, the operation related to the transfer shift of the slave station is not performed. When the instruction signal is on and the next serial transfer clock is received, the phase control counter circuit 2
The count value of 07 is counted up to 01H, and the operation setting of the shift register circuit 203 changes from the load operation to the shift operation. Then, at the fall, the shift operation by the shift register circuit 203 is started.

The shift operation by the shift register circuit 203 is executed for each serial transfer clock, and the count value of the phase control counter circuit 207 is incremented when a count instruction is given by an instruction signal. Eventually, when the shift register circuit 203 completes a shift operation for a predetermined number of shifts determined by the number of slave stations connected in the transmission path, the count value of the phase control counter circuit 207 is adjusted to 06H by the instruction signal. Then, the transfer data from the main station of the shift register circuit 203 is read twice and latched in the latch circuit 204. Also, the shift register circuit 2
At 03, the returned data to the same main station, which has just been returned, is reloaded from the latched input latch circuit 202, and the second shift operation by the shift register circuit 203 is continued. .

Similarly, a shift operation is performed for each serial transfer clock, and the count value of the phase control counter circuit 207 also counts up as specified by the instruction signal. Then, when the second shift operation is completed, the count value of the phase control counter circuit 207 is also adjusted by the instruction signal to become 0CH, and the shift register circuit 203
The comparison is performed on a bit-by-bit basis with the data transferred from the master station of the first and second readings and the first data content latched and held by the latch circuit 204. In the case of the present embodiment, the instruction signal is set to be continuously maintained on so that the comparison execution and the operation of the comparison result are processed continuously by the serial transfer clock. Absent.

The comparison of the transfer data when the count value of the phase control counter circuit 207 is 0CH is constituted by the double read latch circuit 204, and is not shown in the figure.
The input / output of each latch circuit is EXORed for each bit.
It is connected to the input of the D circuit and configured as an OUT output. Therefore, when they match, a high level is output, and when they do not match, a low level is output. Then, at the next serial transfer clock at which the count value of the phase control counter circuit 207 becomes 0DH, the latch pulse of the output latch circuit 205 to be generated and the OUT output of the double read latch circuit 204 are ANDed, so that the comparison result is obtained. Only when they match, the latch holding data of the twice-read latch circuit 204 is latched by the output latch circuit 205 and output as a parallel output which is a slave output.

On the other hand, a timing output signal for feeding back the slave station communication control state to the master station is obtained by inverting the OUT output signal from the double read latch circuit 204, which is the comparison result, by an inverting circuit, and generating an output latch circuit at 0DH. 2
By performing AND operation with the latch pulse of No. 05, the timing output signal from the slave station is turned on only when there is no match. As a result, if the timing output signal remains off at 0DH, the master station can determine that the execution of the serial communication operation has been successful. Because of the OR configuration, the timing output signal transmitted to the master station is turned on, it is determined that the execution of the serial communication operation has failed, and the serial communication for retry is executed. The master station determines that the serial communication has failed according to the state of the retry serial communication.

The above is a description of the simple configuration and control of the serial communication operation according to the first embodiment of the present invention. The slave control operation according to the count value of the phase control counter circuit 207 in the present embodiment is the slave communication processing control means. Further, the master station has first master station counter means for controlling in synchronization with the count operation of the phase control counter circuit 207 of the slave station which is remotely controlled, and executes the phase comparison with the timing output signal fed back from the slave station. By executing the transfer information phase error detection, the signal processing execution operation of serial communication in all slave stations is monitored.

Hereinafter, the transfer clock cycle monitoring means for detecting the phase shift of the serial transfer clock in the serial communication device according to the first embodiment of the present invention will be described with reference to FIG. 2, FIG. 3, FIG. 4, and FIG. It will be described with reference to FIG.
In the serial communication according to the present embodiment, the control operation is divided into normal serial communication mainly exchanging the constantly changing information content of each slave station and initialization serial communication exchanging information set in advance to the slave station. The purpose of the present invention is to monitor the transfer clock during serial communication, and the same applies to any communication form. Therefore, for the sake of simplicity, a means for monitoring and controlling a transfer clock during execution of serial communication in normal serial communication will be described.

In FIG. 2, a clock number counter circuit 206, which is a transfer clock monitoring and controlling means during serial communication execution, uses a transfer clock generated from the master station as a count source and executes a count operation until the operation is stopped by executing a communication reset. It is configured in a form that continues to do so. Specifically, at the start of serial communication, the count value is cleared to zero by communication reset at the start of serial communication, and all input transfer clocks are counted up. And when the count value goes around once,
The count data value is loaded again by the pulse output from the ripple carry-out terminal, and continues to count the number of input transfer clocks. As a result, a clock number output signal having a constant cycle (every predetermined count number) with respect to the transfer clock can be transmitted to the master station. The configuration of the clock number counter circuit 206 described in the present embodiment is not limited, and the number of transfer clocks can be counted in a ring counter format. Any circuit configuration can be used.

In the present embodiment, the clock number counter circuit 206 is configured to emit a pulse when it receives 16 transfer clocks at first, and to emit a pulse when it receives 13 transfer clocks thereafter. I have. The clock number output signal is connected to the master station in a wired OR configuration between all slave stations as shown in FIG. As a result, when serial communication is normally executed, as shown in the clock number output signal of the timing chart of FIG. 4, after the master station issues a communication reset, only when 16 transfer clocks are output, (Single output at a predetermined phase) and thereafter, every time 13 transfer clocks are output, a clock number output signal is transmitted to the main station. If the device noise enters the transfer clock of any one of the slave stations, and a phase shift occurs, the pace of the clock number output signal transmitted to the master station will shift.

For example, when the device noise enters the transfer clock of one slave station and one phase shift occurs, the clock number output signal transmitted to the master station has both the thirteenth and fourteenth phase signals. The signal is turned on. Further, when the apparatus noise enters the transfer clocks of all the slave stations and one phase shift occurs, the clock number output signal transmitted to the master station is turned on only at the fourteenth phase. is there. Therefore, if the master station counts the number of transfer clocks generated by the master station output transfer clock number counter means shown in the flowcharts of FIGS. 5 and 6, the phase of the returned clock number output signal can be determined in advance. By simply recognizing the set period and comparing and judging the count with the main station output transfer clock number counter means, it is possible to always monitor and control the transfer clock when executing the serial communication.

Finally, specific transfer clock monitoring and control means in the master station of the serial communication device according to the first embodiment of the present invention will be described with reference to the flowcharts of FIGS. In FIGS. 5 and 6, the master station output transfer clock number counter means is abbreviated as a master station clock number counter. 5 and 6, for ease of explanation, the operation control unit of the transfer clock number counter is mainly shown, and other serial communication control units are omitted.

In FIGS. 5 and 6, when the serial communication is executed, the start point indicated by S in the figure is entered, and the serial communication program is started. A communication reset is executed in step S530, and serial communication is started (in the case of the present embodiment, the communication reset turned on in step S530 is automatically turned off after a predetermined time). Then, the process shifts to step S531, where the master station clock number counter is initialized. In the case of the present embodiment, the clock number counter circuit 206 of the slave station is set to 0FH since the clear start is initially performed (the count number after the communication reset is turned on at 0CH). Step S53
Then, the subroutine for executing serial communication is executed to complete the preparation for accessing data and the like, and the operation shifts to execution of communication. When the execution starts, the process moves to step S533, and the master station clock number counter is checked for zero. If not zero, step S534, step S5
35. In step S536, data shift of serial communication is performed, and in step S537, the value of the master station clock number counter is decremented.

Then, in step S539, it is checked whether the serial communication has been completed, and the flow advances to step S540.
In step S540, a clock number output signal fed back from the serial transmission path is checked. Steps S534, S535, and S536 above
When the clock number output signal is on, since the master station clock number counter is not the predetermined value,
It is determined that device noise or the like has jumped in and the transfer clock has become abnormal, and is processed as a serial communication error in step S543. Normally, the process returns to step S533 because the clock number output signal is off. Eventually,
When the master station clock number counter reaches a predetermined value, the process moves from step S533 to step S541 to check the clock number output signal fed back from the serial transmission line.

When the clock number output signal of the master station clock counter reaches a predetermined value and the clock number output signal is off, it is determined that device noise or the like has jumped in and the transfer clock has become abnormal. It is processed as. Usually, since the clock number output signal is turned on at this timing, step S542 is performed.
The main station clock number counter indicates the following predetermined value 0C.
Set H. Incidentally, it is needless to say that the value is set in accordance with the data load value of the clock number counter circuit 206 formed in the slave station, and is not particularly limited. Then, the process returns to step S533 again, and the same operation is repeated. When the serial communication ends in step S539, the execution of one serial communication ends.

The above is the first embodiment of the present invention. The total number of serial transfer clocks is counted by the second counter means (clock number counter circuit 206) of each slave station, and the count value is set in advance. A clock number output signal is fed back to the master station every time it reaches the specified value. On the other hand, the master station detects the phase timing of the output signal of the number of clocks for each predetermined cycle, and determines whether or not the timing is normal. It has. As a result, it is possible to detect an abnormality due to device noise that may occur during serial communication entering the transmission path.

As described above, according to the serial communication device according to the first embodiment of the present invention, the serial transfer provided in each of the slave stations and issued in synchronization with the transfer of the serial information sent from the master station. A first counter 112 whose count operation is controlled by an instruction signal generated from the main station using a clock as a count source;
When 2 reaches a preset count value, the master station issues a feedback signal notifying the phase timing to the master station, and performs serial communication operation processing as timing for executing predetermined signal processing on serial information of serial communication in the slave station. Slave communication processing control means 11 for executing
3, second counter means 114 provided at each slave station for counting the total number of input serial transfer clocks using the serial transfer clock as a count source, and the count value of the second counter means 114 is preset. Return means 1 for returning a feedback signal to the master station every time the value becomes a value
15 and a transfer clock cycle monitoring means 111 provided in the main station and detecting a phase shift of a serial transfer clock generated by itself based on a feedback signal returned from the return means 115 at a phase timing every predetermined cycle. It has the following functions and effects.

In the above configuration, the first counter means 112 (phase control counter circuit 207) of each slave station
Is operated by a control signal generated by the main station to control the count operation as timing counter means for executing data processing of serial transfer information with the main station. Specifically, the count value is cleared to zero by a communication reset signal, and the execution or stop of the count operation is controlled by the instruction signal. At the time of the count operation, the count value is incremented at the rising edge of the serial transfer clock, and the count value makes one round in response to the end of one shift of the serial transfer data.

When the count value indicated by the first counter means 112 (phase control counter circuit 207) reaches a preset count value, a specific signal processing circuit configured as a slave station executes an operation and further counts. One round of the value ends the slave signal processing for one serial communication. Specifically, for example, at 00H, the information to be returned to the master station is loaded into the shift register circuit 203, and at 06H,
The information transferred from the master station is read twice from the shift register circuit 203, stored in the latch circuit 204, and
As in the case of H, the shift register circuit 203 is reloaded with the same information as the previous information to be returned to the main station again. And OC
At the time of H, the same information re-transferred from the main station is compared with the contents of the shift register circuit 203 and the data latched earlier,
When the readout process is executed twice and the comparison result matches at 0 DH, the operation is performed so as to store the data in the output latch circuit 205 which performs the parallel output and terminate the operation.

The control by the first counter means 112 (phase control counter circuit 207) is the slave station communication processing control means, which performs predetermined serial communication operation processing when a fixed count value is reached. Therefore, the master station determines the number of data bits to be serially transferred at one time in accordance with the number of slave stations connected in the transmission path. The instruction signal is operated so as to control the count operation at a timing along the shift operation. That is, in order to execute, for example, ten slave stations with 4-bit information data, the first counter 11
The count value of 2 (phase control counter circuit 207) is set to 06
The count operation may be executed by thinning out the serial transfer clock so as to set H. In the data loading operation of the shift register circuit 203 at the time of 00H, loading is performed once per serial transfer clock. In other words, the load operation is executed in response to the number of serial transfer clocks input, and the shift to the shift operation is performed with the last loaded data.

On the other hand, the second counter means 114 (clock number counter circuit 206) counts all serial transfer clocks at the time of executing the serial communication operation unconditionally. However, at the time of starting one communication operation and immediately after reaching a predetermined count value, a count operation from a preset count value is performed, and a feedback signal is issued every time the count value reaches a predetermined count value. . as a result,
Second counter means 114 (clock number counter circuit 2
From 06), it is possible to issue a feedback signal to the master station every specific number of serial transfer clocks (every predetermined cycle). As a result, the master station operates so that the phase timing of the serial transfer clock generated by itself can be detected at a specific cycle.

Therefore, the master station compares the clock phase with the serial transfer clock number generated by itself, for each serial transfer clock number feedback signal returned from the second counter means 114 (clock number counter circuit 206). With the above operation, the phase shift of the serial transfer clock serving as the transfer clock cycle monitoring means can be detected. The second counter means 1
14 (clock number counter circuit 206) only needs to be present in the serial transfer clock transmission path of the serial communication device, and the number and positions of the 14 devices are determined according to the device. That is, the second counter means 114 (clock number counter circuit 206) may be provided for each slave station, or may be provided for the slave station located at the farthest point of the serial communication transmission line.
Further, it may be provided at a slave station located at an arbitrary point on the serial communication transmission line, or may be provided at a slave station located at the end of the serial communication transmission line. On the other hand, an independent terminal may be provided for the slave station and a second counter means may be provided.

Further, the main station is provided with the first counter means 112.
The first main station counter operates in synchronization with the count value of the (phase control counter circuit 207) and the second main station operates in synchronization with the count value of the second counter 114 (clock number counter circuit 206). The first counter means has a double reading comparison, and the second counter means has a clock phase by operating to compare with the phase timing of the feedback signal from each counter means. The detection can be confirmed, and each is determined to act to determine a serial information transfer error.

That is, the present serial communication device has counter means for counting the number of serial transfer clocks, and has return means for feeding back to the master station at predetermined intervals. Further, the master station counts the number of serial transfer clocks sent out by its own counter means having the phase timing fed back, and has a transfer clock cycle monitoring means for comparing the phases with each other. To detect.

Thus, in the present serial communication device, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means whose data length is constituted only by transfer information, there is an effect that the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost.

[2] Second Embodiment FIG. 7 is a block diagram showing a circuit configuration of a slave station of a serial communication device according to a second embodiment of the present invention. The slave station of the serial communication device according to the second embodiment of the present invention includes an input selector circuit 701, an input latch circuit 702, a shift register circuit 703, a double read latch circuit 704, an output latch circuit 705, and a phase control counter circuit 707. , Count value decoding circuit 708, multi-input AND circuit 709,
The configuration includes a gate logic group 710.
Note that the configuration illustrated in FIG. 7 is an example, and the configuration is not limited to the illustrated configuration.

The second embodiment of the present invention is different from the first embodiment in that the clock number counter circuit 206 which is the second counter means shown in FIG. The configuration is the same as that of the first embodiment except that it does not exist in the communication channel but exists in the serial communication transmission path. The clock number counter circuit 206 shown in FIG. 2 exists in the serial communication transmission line, and belongs to a certain slave station unit, but does not have to each slave station.

In the second embodiment of the present invention, a case will be described in which the data is added to the farthest slave serial transfer clock line located farthest in the serial transmission path. However, the clock number counter circuit 2 shown in FIG.
As a place where 06 is located, for example, it may be added to a slave station belonging to the end of the serial transmission line, and it is effective to add the place to a place where the influence of device noise is large. Therefore, it is needless to say that the adding position is not particularly limited, and a plurality of adding positions may be adopted.

FIG. 8 is a block diagram showing a system configuration of a serial communication device according to the second embodiment of the present invention. The serial communication device according to the second embodiment of the present invention includes a master station 820 and a plurality of slave stations 821, 822, 82.
3, 824 and the clock number counter circuit 206 added to the slave station 823. FIG.
Is an example, and is not limited to the illustrated configuration.

The second embodiment of the present invention is different from the first embodiment in that there is no clock number output signal from each slave station IC, and the slave station 823 has a new second counter means. The configuration is such that a clock number counter circuit 206 is added, and the other configuration is the same as that of the first embodiment.

With the configuration shown in FIG. 8, the clock number output signal from the clock number counter circuit 206 is output from the first
In the same manner as in the embodiment, feedback is provided to the master station via the serial transmission line at a predetermined cycle.
As a result, the master station operates the transfer clock cycle monitoring means shown in FIG. 5 described in the first embodiment to operate the transfer clock cycle monitoring means, thereby causing abnormalities caused by device noise that may be generated during serial communication into the transmission path. Detection becomes possible.

As described above, according to the serial communication apparatus according to the second embodiment of the present invention, the serial transfer provided in each of the slave stations and issued in synchronization with the transfer of the serial information sent from the master station. A first counter 112 whose count operation is controlled by an instruction signal generated from the main station using a clock as a count source;
When 2 reaches a preset count value, the master station issues a feedback signal notifying the phase timing to the master station, and performs serial communication operation processing as timing for executing predetermined signal processing on serial information of serial communication in the slave station. Slave communication processing control means 11 for executing
3, a second counter 114 provided in the serial communication transmission line and counting the total number of input serial transfer clocks using the serial transfer clock as a count source.
Return means 115 for returning a feedback signal to the master station every time the count value of the second counter means 114 reaches a preset value; and return means 115 provided in the master station.
Transfer clock period monitoring means 11 for detecting a phase shift of a serial transfer clock generated by itself based on a feedback signal returned at a phase timing every predetermined period from
The following effects can be obtained because of having 1.

As in the first embodiment, this serial communication device has counter means for counting the number of serial transfer clocks, and has return means for feeding back to the main station at predetermined intervals. Further, the master station counts the number of serial transfer clocks sent out by its own counter means having the phase timing fed back, and has a transfer clock cycle monitoring means for comparing the phases with each other. To detect.

As a result, in this serial communication device, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means whose data length is constituted only by transfer information, there is an effect that the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost.

[3] Third Embodiment FIG. 9 is a block diagram showing a system configuration of a serial communication device according to a third embodiment of the present invention. The serial communication device according to the third embodiment of the present invention comprises a master station 920
And a plurality of slave stations 921, 922, 923, and 924, and a clock counter circuit 206 added to the master station 920. Note that the configuration illustrated in FIG. 9 is an example, and the configuration is not limited to the illustrated configuration.

The third embodiment of the present invention is different from the first embodiment in that there is no clock number output signal from each slave station IC and the serial transfer clock extracted from an arbitrary serial transfer clock line. Is a configuration in which a clock number counter circuit 206 having a clock source as a count source is added to the main station 920, and the other configuration is the same as that of the first embodiment. The clock number counter circuit 206 uses a serial transfer clock via a serial communication transmission line as a clock source, and does not have any slave station.

In the third embodiment of the present invention, a case will be described in which a farthest slave serial transfer clock line located farthest from a serial transmission path is detected. However, the detection position of the serial transfer clock detected by the clock number counter circuit 206 may be, for example, the serial transfer clock belonging to the end of the serial transmission path, and it is effective to add the detection position to a place where the influence of device noise is large. It is a target. Therefore, it is needless to say that the position of the serial transfer clock to be detected is not particularly limited, and a plurality of serial transfer clocks may be added.

With the configuration shown in FIG. 9, the clock number output signal from the clock number counter circuit 206 is output from the first
In the same manner as in the embodiment, feedback is directly provided to the main station at a predetermined cycle. As a result, the master station operates the transfer clock cycle monitoring means shown in FIG. 5 described in the first embodiment, and detects an abnormality caused by device noise that may occur during serial communication entering the transmission path. It becomes possible.

As described above, according to the serial communication apparatus according to the third embodiment of the present invention, the serial transfer provided in each slave station and issued in synchronization with the transfer of the serial information sent from the master station. A first counter 112 whose count operation is controlled by an instruction signal generated from the main station using a clock as a count source;
When 2 reaches a preset count value, the master station issues a feedback signal notifying the phase timing to the master station, and performs serial communication operation processing as timing for executing predetermined signal processing on serial information of serial communication in the slave station. Slave communication processing control means 11 for executing
3, a second counter means 114 provided in the master station for counting the total number of input serial transfer clocks using the serial transfer clock as a count source, and a count value of the second counter means 114 being a preset value. Return means 115 for returning a feedback signal to the master station every time
And a transfer clock cycle monitoring means 111 which is provided in the main station and detects a phase shift of the serial transfer clock generated by itself based on a feedback signal returned from the return means 115 at a phase timing every predetermined cycle. The following effects are obtained.

As in the first embodiment, the present serial communication device has counter means for counting the number of serial transfer clocks, and has return means for feeding back to the master station at predetermined intervals. Further, the master station counts the number of serial transfer clocks sent out by its own counter means having the phase timing fed back, and has a transfer clock cycle monitoring means for comparing the phases with each other. To detect.

Thus, in the present serial communication device, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means whose data length is constituted only by transfer information, there is an effect that the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost.

The present invention may be applied to a system composed of a plurality of devices or an apparatus composed of one device. A storage medium storing software program codes for realizing the functions of the above-described embodiments is supplied to a system or an apparatus, and a computer (or CPU or MPU) of the system or the apparatus executes the program code stored in the storage medium. Needless to say, this can also be achieved by executing the reading.

In this case, the program code itself read from the storage medium realizes the functions of the above-described embodiment, and the storage medium storing the program code constitutes the present invention.

Examples of a storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and CD.
-R, a magnetic tape, a nonvolatile memory card, a ROM, or the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS and the like running on the computer are actually executed based on the instructions of the program code. It goes without saying that a part or all of the above-described processing is performed, and the functions of the above-described embodiments are realized by the processing.

Further, after the program code read from the storage medium is written into a memory provided on a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, It goes without saying that the CPU provided in the function expansion board or the function expansion unit performs part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

[0114]

As described above, according to the communication apparatus of the first aspect of the present invention, a communication apparatus in which a master station and a plurality of slave stations are connected via a loop-type transmission path, First counter means using a serial transfer clock synchronized with transfer of serial information generated from a station as a count source; second counter means using the serial transfer clock as a count source; and the first and second counter means And the transfer clock cycle monitoring means for detecting the phase shift of the serial transfer clock generated by itself based on the counting operation.

The communication device of the present invention has counter means for counting the number of serial transfer clocks. Further, the master station has the transfer clock cycle monitoring means for detecting the phase shift of the serial transfer clock generated by the master station based on the counting operation of the first and second counter means, thereby detecting the abnormality of the serial transfer clock. . Accordingly, in the communication device of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise.
Even in a very simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, it is possible to determine the information arrangement phase shift of the transfer information due to the periodic noise by an easy means and at a low cost. This has the effect.

According to the communication apparatus of the present invention, the first counter means is provided in each of the slave stations, and the counting operation is controlled by an instruction signal from the master station. Has at least one, and counts the total number of the serial transfer clocks. Since the phase shift of the serial transfer clock is detected, the following effects are obtained.

The communication device of the present invention has counter means for counting the number of serial transfer clocks. Further, the master station counts the number of serial transfer clocks sent out by its own counter means having the phase timing fed back, and has a transfer clock cycle monitoring means for comparing the phases with each other. To detect. Accordingly, in the communication apparatus of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means having only a data length consisting of only the data length, there is an effect that the information arrangement phase shift of the transfer information due to the periodic noise can be determined by an easy means and at a low cost.

According to the communication apparatus of the present invention, when the count value of the first counter means reaches a set value, a feedback signal for notifying a phase timing is issued to the master station, and the slave station is provided with a feedback signal. A slave station communication processing control means for executing a series of serial communication operation processing, and a return means for returning a feedback signal to the master station every time the count value of the second counter means reaches a set value,
The following effects are obtained.

The communication apparatus of the present invention has counter means for counting the number of serial transfer clocks, and has return means for feeding back to the master station at predetermined intervals. Furthermore,
The master station counts the number of serial transfer clocks sent out by its own counter means having the phase timing fed back, and detects an abnormality in the serial transfer clock by having transfer clock cycle monitoring means for comparing the phases with each other. . Accordingly, in the communication apparatus of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means having only a data length consisting of only the data length, there is an effect that the information arrangement phase shift of the transfer information due to the periodic noise can be determined by an easy means and at a low cost.

According to the communication apparatus of the present invention, the second counter means is provided in each of the slave stations, and the transmission line is generated by the transfer clock cycle monitoring means every predetermined cycle. And a plurality of feedback signals generated from each slave station are transmitted as a single signal to the master station. Since the phase shift of the serial transfer clock of each slave station is detected based on the state of the signal transmitted by one signal via the control unit, the following effects are obtained.

A plurality of feedback signals generated from each slave station are transmitted to the master station as one signal, and the phase shift of the serial transfer clock of each slave station is detected based on the signal state transmitted by the one signal. Similarly, in the communication apparatus of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means whose data length is constituted only by information, there is an effect that the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost.

According to the communication apparatus of the present invention, the second counter means has a slave station connected to the farthest point of the transmission line, and the transmission line monitors the transfer clock cycle. Means for transmitting a phase timing generated every predetermined period to the means, wherein the transfer clock cycle monitoring means determines a phase of a serial transfer clock in the transmission path based on a signal state transmitted through the transmission path. The following effects are obtained because the displacement is detected.

By detecting the phase shift of the serial transfer clock in the transmission path based on the state of the transmitted signal,
As described above, in the communication device of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means whose data length is constituted only by transfer information, there is an effect that the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost.

According to the communication apparatus of the present invention, the second counter means has a slave station connected to an arbitrary point on the transmission path, and the transmission path has the transmission clock cycle. A transmission line for transmitting a phase timing generated every predetermined period to a monitoring unit, wherein the transfer clock cycle monitoring unit is configured to transmit a serial transfer clock in the transmission line based on a signal state transmitted through the transmission line. Since the phase shift is detected, the following effects are obtained.

By detecting the phase shift of the serial transfer clock in the transmission path based on the state of the transmitted signal,
As described above, in the communication device of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means whose data length is constituted only by transfer information, there is an effect that the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost.

According to the communication apparatus of the present invention, the second counter means is provided in the master station, and the slave station communication processing control means determines the last slave station located in the transmission path. Either the serial transfer clock passed through or the serial transfer clock to the farthest slave station in the transmission path is fed back to the master station, and the transfer clock cycle monitoring means counts the returned serial transfer clock to a count source. Since the phase timing of each predetermined cycle is calculated by the counting operation described above and the phase shift of the serial transfer clock in the transmission line is detected, the following effects are obtained.

By calculating the phase timing of each predetermined cycle by the counting operation using the returned serial transfer clock as a count source and detecting the phase shift of the serial transfer clock in the transmission path, the present invention can be implemented similarly to the above. In the communication device of (1), the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in a very simple serial communication means, there is an effect that the information arrangement phase shift of the transfer information due to the periodic noise can be determined by an easy means and at a low cost.

According to the communication apparatus of the present invention, the master station is a serial communication main apparatus included in a central processing unit of a device equipped with a communication apparatus main body, and the master station is in communication with the slave station. Since this is a serial communication sub-device included in the electric units scattered in the device equipped with the device main body, the following effects are obtained.

As described above, in the communication device of the present invention, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in an extremely simple serial communication means whose data length is constituted only by transfer information as described above, the information arrangement phase shift of transfer information due to periodic noise can be determined by an easy means and at low cost. There is.

According to a ninth aspect of the present invention, there is provided a phase shift detecting method applied to a communication apparatus in which a master station and a plurality of slave stations are connected via a loop transmission path. A first counter step using a serial transfer clock synchronized with the transfer of serial information from the master station as a count source, a second counter step using the serial transfer clock as a count source, and the first and second counter steps.
And a transfer clock cycle monitoring step of detecting a phase shift of the serial transfer clock generated by the self based on the counting operation of the counter step.

The phase shift detecting method of the present invention has a counter step for counting the number of serial transfer clocks. Further, a transfer clock cycle monitoring step of detecting a phase shift of the serial transfer clock generated by the self based on the counting operation of the first and second counter steps detects an abnormality of the serial transfer clock.
Thus, in the communication apparatus to which the phase shift detecting method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information for the periodic noise. In addition, even in a very simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, the information arrangement phase shift of the transfer information due to the periodic noise can be easily performed while maintaining low cost. There is an effect that determination can be made.

According to the phase shift detecting method of the present invention, the first counter step is provided in each of the slave stations, and the counting operation is controlled by an instruction signal from the master station. The counter step includes at least one or more and counts the total number of the serial transfer clocks, and the transfer clock cycle monitoring step includes:
Since the phase shift of the serial transfer clock generated by itself is detected based on the feedback signal which the master station has and which is returned from the slave station at a phase timing every predetermined period, the following effects are obtained.

The phase shift detecting method of the present invention has a counter step for counting the number of serial transfer clocks. Furthermore, the transfer clock cycle monitoring step of counting the number of serial transfer clocks sent out by the counter means having its own phase timing fed back and comparing the phases with each other detects an abnormality of the serial transfer clock. Thus, in the communication apparatus to which the phase shift detecting method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information for the periodic noise. In addition, even in a very simple serial communication means in which the data length is constituted only by transfer information as in the conventional technology,
There is an effect that the information arrangement phase shift of the transfer information due to the periodic noise can be determined by an easy means and at a low cost.

According to the phase shift detecting method of the present invention, when the count value of the first counter step reaches a set value, a feedback signal for notifying a phase timing is issued to the master station and the slave station is controlled. And a return step of returning a feedback signal to the master station every time the count value of the second counter step reaches a set value. The following effects are obtained.

The phase shift detecting method of the present invention has a counter step for counting the number of serial transfer clocks,
There is a returning step of feeding back to the master station at predetermined intervals. Furthermore, the transfer clock cycle monitoring step of counting the number of serial transfer clocks sent out by the counter means having its own phase timing fed back and comparing the phases with each other detects an abnormality of the serial transfer clock. Thus, in the communication apparatus to which the phase shift detecting method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information for the periodic noise. In addition, even in a very simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, the information arrangement phase shift of the transfer information due to the periodic noise can be easily performed while maintaining low cost. There is an effect that determination can be made.

According to a twelfth aspect of the present invention, the second counter step is provided in each of the slave stations, and the transmission line is transferred to the transfer clock cycle monitoring step every predetermined period. And a transmission path for transmitting the phase timing generated in the transmission clock cycle, and a plurality of feedback signals generated from each slave station are transmitted to the master station as one signal by the wired OR circuit. Since the phase shift of the serial transfer clock of each slave station is detected based on the signal state transmitted by one signal via the path, the following effects are obtained.

By transmitting a plurality of feedback signals from each slave station to the master station as one signal and detecting the phase shift of the serial transfer clock of each slave station based on the signal state transmitted by the one signal, Similarly to the above, in the communication apparatus to which the phase shift detecting method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting the phase shift in the serial information for the periodic noise. In addition, even in a very simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, the information arrangement phase shift of the transfer information due to the periodic noise can be easily performed while maintaining low cost. There is an effect that determination can be made.

According to the phase shift detecting method of the present invention, the second counter step includes a slave station connected to the farthest point of the transmission path, and the transmission path includes:
A transmission path for transmitting a phase timing generated every predetermined period to the transfer clock cycle monitoring step, wherein the transfer clock cycle monitoring step includes a step of transmitting the phase timing in the transmission path based on a signal state transmitted through the transmission path. Since the phase shift of the serial transfer clock is detected, the following effects are obtained.

By detecting the phase shift of the serial transfer clock in the transmission path based on the state of the transmitted signal,
As described above, in the communication device to which the phase shift detection method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting phase shift in the serial information for the periodic noise. Therefore, even in an extremely simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, the information arrangement phase shift of the transfer information due to the periodic noise can be maintained easily and at low cost. There is an effect that it is possible to make a judgment while making a decision.

According to a fourteenth aspect of the present invention, the second counter step is provided by a slave station connected to an arbitrary point on the transmission path, and the transmission path includes the transmission line. A transmission path for transmitting a phase timing generated every predetermined period to a clock cycle monitoring step, wherein the transfer clock cycle monitoring step includes the step of serially transmitting data in the transmission path based on a signal state transmitted through the transmission path. The following effects are obtained because the phase shift of the clock is detected.

By detecting the phase shift of the serial transfer clock in the transmission path based on the state of the transmitted signal,
As described above, in the communication device to which the phase shift detection method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting phase shift in the serial information for the periodic noise. Therefore, even in an extremely simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, the information arrangement phase shift of the transfer information due to the periodic noise can be maintained easily and at low cost. There is an effect that it is possible to make a judgment while making a decision.

According to a fifteenth aspect of the present invention, the second counter step is provided in the master station, and the slave station communication processing control step is located last in the transmission path. Either the serial transfer clock via the slave station or the serial transfer clock to the furthest slave station in the transmission path is fed back to the master station, and in the transfer clock cycle monitoring step, the returned serial transfer clock is Since the phase timing of each predetermined period is calculated by the count operation using the count source and the phase shift of the serial transfer clock in the transmission path is detected, the following effects are obtained.

By calculating the phase timing for each predetermined period by the counting operation using the returned serial transfer clock as a count source and detecting the phase shift of the serial transfer clock in the transmission path, the present invention can be implemented similarly to the above. In the communication device to which the phase shift detection method of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting the phase shift in the serial information for the periodic noise. Even in an extremely simple serial communication means whose data length is constituted only by simple transfer information, there is an effect that the information arrangement phase shift of the transfer information due to periodic noise can be determined by an easy means and at a low cost. .

According to the phase shift detecting method of the present invention, the master station is a main unit of serial communication included in a central processing unit of a device equipped with a communication device main body, and the slave station is Since the sub-devices of the serial units included in the electric units scattered in the device equipped with the communication device main body, the following effects are obtained.

Similarly to the above, in the communication apparatus to which the phase shift detecting method of the present invention is applied, the state of the serial transfer clock is monitored without adding a bit for detecting phase shift in the serial information for periodic noise. Therefore, even in an extremely simple serial communication means in which the data length is constituted only by the transfer information as in the prior art, the information arrangement phase shift of the transfer information due to the periodic noise can be easily performed at a low cost. There is an effect that the judgment can be made while maintaining.

According to the storage medium of the present invention, there is provided a program for executing a phase shift detecting method applied to a communication apparatus in which a master station and a plurality of slave stations are connected via a loop transmission path. A storage medium readable by a computer, wherein the phase shift detecting method comprises: a first counter step using a serial transfer clock synchronized with a transfer of serial information issued from a main station as a count source; The second with the count source
And the transfer clock cycle monitoring step of detecting a phase shift of the serial transfer clock generated by the self based on the counting operation of the first and second counter steps, has the following effects.

A computer-readable storage medium storing a program for executing the phase shift detecting method of the present invention has a counter step for counting the number of serial transfer clocks. Further, a transfer clock cycle monitoring step of detecting a phase shift of the serial transfer clock generated by the self based on the counting operation of the first and second counter steps detects an abnormality of the serial transfer clock. Accordingly, in the present communication device to which the storage medium of the present invention is applied, the state of the serial transfer clock can be monitored without adding a bit for detecting a phase shift in the serial information with respect to the periodic noise. Even in an extremely simple serial communication unit having a data length consisting only of transfer information as in the prior art, it is possible to determine an information arrangement phase shift of transfer information due to periodic noise while maintaining low cost by an easy means. This has the effect.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a configuration of a main part of a serial communication device according to a first embodiment of the present invention and corresponding to the claims;

FIG. 2 is a circuit diagram showing a circuit configuration of a slave station of the serial communication device according to the first embodiment of the present invention.

FIG. 3 is a block diagram showing a system configuration of the serial communication device according to the first embodiment of the present invention.

FIG. 4 is a timing chart of serial communication in the serial communication device according to the first embodiment of the present invention.

FIG. 5 is a flowchart showing a master station control operation in the serial communication device according to the first embodiment of the present invention.

FIG. 6 is a flowchart showing a master station control operation in the serial communication device according to the first embodiment of the present invention.

FIG. 7 is a circuit diagram showing a circuit configuration of a slave station of a serial communication device according to a second embodiment of the present invention.

FIG. 8 is a block diagram showing a system configuration of a serial communication device according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a system configuration of a serial communication device according to a third embodiment of the present invention.

[Explanation of symbols]

1, 320, 820, 920 Main stations 2-1 to 2-n, 321 to 324, 821 to 824, 9
21 to 924 Slave station 111 Transfer clock cycle monitoring means 112 First counter means 113 Slave communication processing control means 114 Second counter means 115 Return means 201 Input selector circuit 202 Input latch circuit 203 Shift register circuit 204 Double read latch circuit 205 Output latch circuit 206 Clock number counter circuit 207 Phase control counter circuit 208 Count value decoding circuit 209 Multi-input AND circuit 210 Gate logic group 320, 820, 920 Master station 321-324, 821-824, 921-924 Slave station

Claims (17)

[Claims] 1. A communication device in which a master station and a plurality of slave stations are connected via a loop-type transmission path, wherein a first clock having a serial transfer clock synchronized with transfer of serial information generated from the master station is used as a count source. And a second means using the serial transfer clock as a count source.
And a transfer clock period monitoring means for detecting a phase shift of a serial transfer clock generated by itself based on the counting operation of the first and second counter means. 2. The first counter means is provided in each of the slave stations, and the counting operation is controlled by an instruction signal from the master station. The second counter means has at least one or more and the serial transfer clock. Wherein the transfer clock cycle monitoring means detects a phase shift of a serial transfer clock generated by the master station based on a feedback signal which the master station has and which is returned from the slave station at a phase timing every predetermined cycle. The communication device according to claim 1, wherein 3. A slave station communication which issues a feedback signal for phase timing notification to the master station when the count value of the first counter means reaches a set value, and executes a series of serial communication operation processing at the slave station. Processing control means;
3. The communication device according to claim 1, further comprising a return unit that returns a feedback signal to the master station every time the count value of the second counter unit reaches a set value. 4. The second counter means is included in each slave station, and the transmission path is a transmission path for transmitting a phase timing generated every predetermined period to the transfer clock cycle monitoring means, and An OR circuit and a plurality of feedback signals generated from each slave station are transmitted to the master station as one signal, and the transfer clock cycle monitoring means changes the signal state transmitted by one signal through the transmission path. 4. The communication apparatus according to claim 1, wherein a phase shift of a serial transfer clock of each slave station is detected based on the detected phase shift. 5. The second counter means includes a slave station connected to the farthest point of the transmission path, and the transmission path transmits a phase timing generated at predetermined intervals to the transfer clock cycle monitoring means. 2. A transmission line for transmission, wherein the transfer clock cycle monitoring means detects a phase shift of a serial transfer clock in the transmission line based on a state of a signal transmitted through the transmission line. The communication device according to any one of claims 1 to 3. 6. The second counter means includes a slave station connected to an arbitrary point on the transmission path, wherein the transmission path comprises:
A transmission path for transmitting a phase timing generated every predetermined period to the transfer clock cycle monitoring means, wherein the transfer clock cycle monitoring means is configured to transmit the phase timing generated in the transmission path based on a signal state transmitted through the transmission path. 4. The method according to claim 1, wherein a phase shift of the serial transfer clock is detected.
The communication device according to any one of the above. 7. The second counter means is provided in a master station, and the slave station communication processing control means is adapted to control a serial transfer clock via a slave station located last in the transmission path or a serial transfer clock in the transmission path. Any one of the serial transfer clocks to the distant slave station is fed back to the master station, and the transfer clock cycle monitoring means uses the returned serial transfer clock as a count source to count the phase timing of each predetermined cycle by a count operation. 2. The method according to claim 1, wherein the phase shift of the serial transfer clock in the transmission path is calculated and detected.
The communication device according to any one of claims 1 to 3. 8. The main station is a main unit of serial communication included in a central processing unit of a device equipped with a communication device main body, and the slave station is an electric unit scattered in a device equipped with a communication device main body. The communication device according to claim 1, wherein the communication device is a serial communication sub-device included in the communication device. 9. A phase shift detecting method applied to a communication apparatus in which a master station and a plurality of slave stations are connected via a loop transmission path, wherein the serial transfer is synchronized with the transfer of serial information issued from the master station. A first counter step using a clock as a count source, a second counter step using the serial transfer clock as a count source, and a serial transfer clock generated by itself based on the count operation of the first and second counter steps. A transfer clock cycle monitoring step of detecting a phase shift. 10. The first counter step is provided in each of the slave stations, and the counting operation is controlled by an instruction signal from the master station. The second counter step has at least one or more and the serial transfer clock. And the transfer clock cycle monitoring step detects a phase shift of a serial transfer clock generated by the master station based on a feedback signal which the master station has and which is returned from the slave station at a phase timing every predetermined cycle. The phase shift detecting method according to claim 9, wherein 11. A slave station communication that issues a feedback signal for phase timing notification to the master station when the count value of the first counter step reaches a set value, and executes a series of serial communication operation processing at the slave station. 11. The phase shift detecting method according to claim 9, further comprising: a process control step; and a returning step of returning a feedback signal to the master station every time the count value of the second counter step reaches a set value. . 12. The second counter step is provided in each of the slave stations, and the transmission path is a transmission path for transmitting a phase timing generated every predetermined period to the transfer clock cycle monitoring step, and the transmission path is wired. A plurality of feedback signals generated from the respective slave stations are transmitted to the master station as one signal, and in the transfer clock cycle monitoring step, the signal state transmitted by the single signal via the transmission path is changed to the signal state. 12. A phase shift detecting method according to claim 9, wherein a phase shift of a serial transfer clock of each slave station is detected based on the detected phase shift. 13. The second counter step includes a slave station connected to the farthest point of the transmission line, wherein the transmission line transmits a phase timing generated at predetermined intervals to the transfer clock cycle monitoring step. 10. The transmission line for transmission, wherein in the transfer clock cycle monitoring step, a phase shift of a serial transfer clock in the transmission line is detected based on a state of a signal transmitted through the transmission line. 13. The phase shift detecting method according to any one of claims 1 to 11. 14. The second counter step includes a slave station connected to an arbitrary point on the transmission line, wherein the transmission line transmits a phase timing generated at predetermined intervals to the transfer clock cycle monitoring step. Is a transmission path for transmitting
12. The transfer clock cycle monitoring step according to claim 9, wherein a phase shift of a serial transfer clock in the transmission path is detected based on a signal state transmitted through the transmission path. Phase shift detection method. 15. The second counter step is provided in a master station, and in the slave station communication processing control step, a serial transfer clock via the slave station located last in the transmission path or a serial transmission clock in the transmission path is provided. Feed back any one of the serial transfer clocks to the distant slave station to the master station,
In the transfer clock cycle monitoring step, a phase operation for each predetermined cycle is calculated by a count operation using the returned serial transfer clock as a count source, and a phase shift of the serial transfer clock in the transmission path is detected. The phase shift detecting method according to any one of claims 9 to 11. 16. The master station is a main unit of serial communication included in a central processing unit of a device equipped with a communication device, and the slave station is an electric unit scattered in a device equipped with a communication device. 16. The phase shift detecting method according to claim 9, wherein the phase shift detecting method is a serial communication sub device. 17. A computer-readable storage medium storing a program for executing a phase shift detection method applied to a communication device in which a master station and a plurality of slave stations are connected via a loop transmission path. A phase counter detecting method comprising: a first counter step using a serial transfer clock synchronized with a transfer of serial information issued from a main station as a count source; a second counter step using the serial transfer clock as a count source; A transfer clock cycle monitoring step of detecting a phase shift of the serial transfer clock generated by the self based on the counting operation of the first and second counter steps.