JPH11328101A - Digital signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To carry out fast DMA(direct memory access) transfer between circuit boards by shortening a delay time when a system bus is extended through a bridge. SOLUTION: When the system bus of the bus board 31 on the side of an information processor is extended, the system bus from the bus board 31 is connected to a bridge circuit 63 through bus connection parts 6 (6a, 6b and 6c) and this bridge circuit 63 is connected to four bridge circuits 64a to 64d, which are connected to system buses 12a to 12d respectively. Then DMA transfer is carried out between a CODEC circuit board 21 and a video recording interface circuit board 22 mounted in two slots 43 connected to the one system bus 12a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processor for processing digital video signals and digital audio signals, and more particularly, to a digital signal processor having an extension processing section for extending a system bus to which arithmetic means is connected. It concerns the device.

[0002]

2. Description of the Related Art Computers (arithmetic processing units) are used as digital signal processing units for processing digital video signals and digital audio signals. That is, a general-purpose arithmetic device having an arithmetic means (CPU), an input / output means, a storage means, a system bus, and the like, tends to be used as a digital signal processing apparatus.

However, a general-purpose computer is not always optimal for handling video signals that often require real-time processing.
This is because a general-purpose computer is not provided with an input / output unit dedicated to a video signal or a real-time processing unit.

In order to solve this problem, it is common practice to provide a so-called expansion slot in a system bus of a computer, and to attach a circuit board (expansion board) capable of adding functions to the expansion slot.

[0005]

When complicated processing is required, such as video editing, a plurality of circuit boards requiring a plurality of expansion slots may be required. In some cases, a problem may arise in terms of how to supply a means for exchanging video signals in the system.

In this case, in order to expand the system bus, it is necessary to connect via a bridge due to the limitation of the number of expansion slots to be connected. In an expansion bus structure connected via this bridge, a bridge is required. The delay time due to the transmission of the data becomes a problem.
Since emory access) transfer requires high-speed transfer, it is desired that transfer be performed without using a bridge.

The present invention has been made in view of such circumstances, and has as its object to provide a digital signal processing apparatus capable of reducing a delay in data transfer when a system bus is expanded via a bridge. And

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a system bus, an operation means connected to the system bus, and a connection to the system bus for expanding the system bus. One bridge means, a plurality of other bridge means respectively connected to the one bridge means, and an expansion system bus for bus expansion connected to each of the plurality of other bridge means. It is characterized by:

Here, a DMA (Direct Memory Access) is provided in the same extended system bus among the extended system buses for extending a bus connected to the other bridge means.
Performing transfer. Another example is to mount a digital signal encoding and / or decoding circuit board and a digital signal recording interface circuit board in slots in the same extended system bus.
Further, it is preferable that the arithmetic means determines the slot identification information for identifying the slot and the board identification information of the extension circuit board mounted in the slot.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a digital signal processing device according to an embodiment of the present invention.

The digital signal processing apparatus shown in FIG. 1 includes an information processing apparatus 1 such as a general personal computer or a workstation, and an expansion processing apparatus 10 for expanding a system bus. Are connected via a bus connection board 6. That is, the information processing apparatus 1 is configured such that a CPU 3 such as a microprocessor as an arithmetic unit is connected to an internal system bus 2 to constitute, for example, a normal personal computer. Is connected to an extended system bus 12 of the extension processing device 10 via a bus connection unit 6 that extends

As the system bus 2 inside the information processing apparatus 1, a system bus provided as a standard in a computer system is used. In the present embodiment, a so-called PCI (peripheral component interface) is used.
ect) A bus is used, but is not limited to this.

The extended system bus 12 in the extension processing device 10 extends the internal system bus 2 of the information processing device 1, and in this embodiment, an extended PCI bus is used. In the extension processing device 10, a data bus dedicated to digital video / audio (video / audio) signals is provided in parallel with the extended system bus 12.
AV (Digital Audio Video) bus 13 and local C
A PU bus 14 is provided. The local CPU bus 14 is a control signal dedicated bus for transferring control signals from the local CPU 15 in the extended processing device 10.

DAV bus 1 which is a bus exclusively for video and audio signals
3 has, for example, a configuration as shown in FIG. In FIG. 2, a DAV bus 13 includes a video bus 131, a key bus 132, a video reference (Video Re
f.) Bus 133, audio (Audio) bus 134, audio reference (Audio Ref.) bus 135, and power (Power)
It has a bus 136. Video bus 131
Is a bus dedicated to digital video signals, and is composed of, for example, 120 signal lines. When 10 bits of a digital signal of YUV 4: 2: 2 are Y-color-division multiplexed, 12 channels can be obtained. The key bus 132 is a bus dedicated to a so-called key signal at the time of video synthesis, and is composed of, for example, 30 signal lines. If a 10-bit key signal is multiplexed into 5 bits, 6 channels can be obtained. The video reference bus 133 transmits a video clock signal and a synchronization signal. The audio bus 134 is a bus dedicated to digital audio signals, and is composed of, for example, ten signal lines, one for each.
By multiplexing channels, 80 channels can be obtained. The audio reference bus 135 sends an audio clock signal and a synchronization signal. Power bus 136
Supplies the necessary power to the circuit board connection slots provided on the bus.

The local CPU bus 14 is a control bus used by a local CPU, which is a control arithmetic unit mounted in a predetermined slot among the slots provided in the bus, and includes a circuit mounted in each slot. It is provided to enable difficult control of the circuit in the board via the system bus.

That is, video signals and audio signals often require so-called real-time processing to maintain signal continuity, but when the PCI bus is used as a system bus, digital Only about one channel of the video signal can be secured. Further, in order to edit video signals of two or more channels, such as so-called AB roll editing, it is necessary to temporarily store digital video signal data in a large-capacity memory and read it out at a necessary time. And the configuration becomes complicated, and real-time processing cannot be completely performed.

For this reason, a DAV bus capable of handling digital video signals and audio signals of a plurality of channels in parallel is provided, and various video signal processing circuit boards are provided via the DAV bus for realizing a plurality of channels of real time processing. A local CPU and a local CPU bus are provided to control real-time processing in the video and audio signal processing circuits. As a result, digital signal data can be transmitted from an expansion board such as a CODEC circuit board or a recording medium interface circuit board for encoding / decoding processing by designating an arbitrary channel among a plurality of channels. However, digital signal data of an arbitrary channel can be received, the configuration of data transmission can be freely changed, and digital signal processing of a plurality of channels can be performed in real time.

Here, the circuit board is electrically connected and mechanically supported to the extended system bus 12, DAV bus 13, and local CPU bus 14 in the extension processing apparatus 10 shown in FIGS. Slot 19 is provided. Generally, a slot often refers to a connector for mounting an expansion board to a system bus and electrically connecting the expansion board. In the present embodiment, the slot 19 of the expansion processing device 10 In general, each bus 1
This corresponds to a set of connectors described later provided for each of 2, 13, and 14, respectively. That is, by mounting one expansion board (circuit board) in one slot 19, each of the buses 12, 1
Electrical connection is made via the connectors 3 and 14. However, depending on the expansion board, buses 12, 13, 1
Some do not require an electrical connection with all four.

In this embodiment, for example, fourteen slots are provided in the expansion processing apparatus 10, and a maximum of fourteen expansion boards can be mounted. For example, in the example of FIG. 1, the local CPU circuit board 1 is used as such an expansion board.
5, digital I / O circuit board 17, codec (CODEC) circuit board 21 for encoding / decoding video (video) signals, interface circuit board 23 for video recording, digital special effects, video signal processing for switchers, etc. , A special effect circuit board 24, a circuit board 26 for audio signal processing (encoding / decoding, etc.), an interface circuit board 27 for audio recording, and another circuit board 29. The local CPU circuit board 15 is connected to a control panel 16, the digital I / O circuit board 17 is connected to a connector panel 18, and the video recording interface circuit board 24 is a so-called RAID (redundant array of inexpensive dis
ks) etc., or other information storage media. In addition, information signals (such as digital AV signals) are input and output to and from external devices via the connector panel 18, and, for example, the monitor device 8 is connected.

Each of the slots 19 in FIG. 2 is assigned with a slot number of Slot # 1 to Slot # 14. The 13th (Slot # 13) slot 19 _LC has a local CPU circuit of FIG. The board 15 is mounted, and is set to be a supply source of a clock signal as described later.

FIG. 3 and FIG. 4 are diagrams showing a mechanical schematic structure of a digital signal processing device including the information processing device 1, the bus connection unit 6, and the extension processing device 10. In FIGS. 3 and 4, the system bus 2 is provided on a bus board 31 of the information processing apparatus 1, and usually includes an arithmetic processing circuit (CPU) such as a microprocessor. The bus board 31 is also called a motherboard or a backplane board. In the present embodiment, a so-called PCI motherboard is used. Various buses connected to the system bus are provided on the bus board 31.
Several connectors 33 are provided as expansion slots for mounting expansion boards (circuit boards) such as boards.

The bus board 31 is provided with a connector 36a for extending the system bus, and a bus extension board 6a serving as the bus connection section 6 for extending the system bus is mounted on the connector 36a. Is done. The information processing device 1 and the extension processing device 10 are vertically stacked and arranged, and the bus extension board 6a is
The information processing apparatus 1 is disposed perpendicularly to the bus board 31 so as to pass through the inside of the extension processing apparatus 10. On the extension processing device 10 side, the flat cable 6c is connected via the cable connection portion 6b of the bus extension board 6a, and the flat cable 6c is connected to the bus board 41 in the extension processing device 10 by the connector 36b. so,
It is electrically connected to the extended system bus 12 on the bus board 41. As a result, electrical connection between the system bus 2 of the information processing device 1 and the extended system bus 12 of the extended processing device 10 is established.

Two bus boards (so-called motherboards or backplane boards) 41 and 42 are provided in the extension processing apparatus 10, and the extended system bus 12 is provided on the bus board 41. Substrate 4
2 has the DAV bus 13 and the local CPU bus 14
Is provided. On the bus board 41, several connectors 43 for connecting an expansion board (circuit board) to the expanded system bus 12 are provided, and on the bus board 42, corresponding to these connectors 43. Are provided with a connector 44 for connection to the DAV bus 13 and a connector 45 for connection to the local CPU bus 14, respectively. These connectors 43, 44,
45 corresponds to the slot 19 in FIG.
Connectors 43, 44, 45
Are arranged so as to be aligned on a straight line. For example, in this embodiment, 14 sets of connectors are provided corresponding to 14 slots.

In this embodiment, two bus boards 41,
42 has a step in the vertical direction (vertical direction), and is arranged so as to partially overlap. This is to absorb the difference in the installation level of the connector of the extension board and to increase the effective area of the board. The bus boards 41, 4
Needless to say, 2 may be combined on one substrate.

Here, as shown in FIG. 3 and FIG. 4, the information processing device 1 and the extension
The structure that passes through the inside of the
This is to minimize the extension distance of a system bus such as a bus and minimize unnecessary electromagnetic radiation. Further, in the examples of FIGS. 3 and 4, the structure has a structure in which a flexible flat cable 6c is connected to a bus extension board 6a, and this is generated when the two devices 1 and 10 are connected by the flat cable 6c. The displacement can be absorbed.

In the case where the above-mentioned requirements for the restriction of the unnecessary electromagnetic radiation and the minimization of the extension distance are not so severe, FIG.
As shown in the figure, the connector 36c provided in the information processing apparatus 1
And a connector 36d provided in the extension processing device 10 may be connected via a connection cable 6d.

Since the connector 43 on the bus board 41 of the extension processing apparatus 10 and the connectors 44 and 45 on the bus board 42 are arranged in a straight line, compatibility with a system bus such as a PCI bus is ensured. It is possible to use an extension circuit board (extension board) that can be used for a special purpose, for example, specialized in processing of a digital video / audio signal while keeping the same.

FIG. 6 shows some examples of expansion circuit boards (expansion boards) that can be used by being mounted on the expansion processing apparatus 10. In FIG. 6, the PCI boards 51, 52
Is a circuit board which has a connector 33a for a PCI bus and is also used as an expansion board of a general computer system. The height h ₁ and the width w _{1 of} the half-size PCI board 51 and the full-size PCI board The specific dimensions of the height h ₁ and the width w ₂ are, for example, h ₁
= 98.4 mm, w ₁ = 174.6 mm, w ₂ = 312
mm. In contrast, the expansion processing apparatus 10 dedicated expansion circuit board (expansion board), vertical h _2, and DAV board 53 of the middle size of the X w _2, vertical h _2, full-size transverse w ₃ DAV board 54 are prepared. As a specific example of the dimensions of each part, h ₂ = 221.7 m
m, w ₃ = 470 mm, and w ₂
Is set to 312 mm in the same manner as described above. The middle-sized DAV board 53 has a connector 43a for a PCI bus (the extended main bus 12), and also has a connector 44a for the DAV bus 13, like the normally used PCI boards 51 and 52. , A substrate that is also extended in the height direction. Also, full size DAV
The board 54 further extends the middle-sized DAV board 53 in the horizontal direction, and has a connector 45a for the local CPU bus 14;
This is a board for using this software. It is needless to say that the shape and dimensions of the circuit board can be arbitrarily changed as long as the rules regarding the type and position of each connector are observed.

Next, a method of supplying a video clock signal transmitted through the video reference bus 133 of the DAV bus 13 and an audio clock signal transmitted through the audio reference bus 135 of FIG. 2 will be described with reference to FIG. explain.

FIG. 7 shows a connector 44 for the DAV bus 13 provided on the bus board 42 described above, and a predetermined connector 44 _{LC of} these connectors 44 is shown.
The local CPU circuit board 15 shown in FIG. This connector 44 _LC is the same as that shown in FIG.
This corresponds to the thirteenth (Slot # 13) slot 19 _LC .

The video and audio clock signals from the local CPU circuit board 15 connected to the connector 44 _LC are _supplied via predetermined terminals (eg, pins 10 and 11) to the bus board as a motherboard. It is supplied to a differential input amplifier 46 of the clock driver circuit on 42.
The output from the differential input amplifier 46 is sent to a plurality of differential output amplifiers 47 (for the number to be supplied to other slots), converted into differential signals, and
7 is supplied to predetermined terminals (for example, the 10th and 11th pins) of the connector 44 of the other slot.

This is because in the DAV bus 13,
Each slot is equivalent with respect to the signals in the bus, but only the clock signal comes from a specific slot (Slot # 13) as the clock source, since each slot needs to operate very strictly synchronously. The clock signal from this slot is distributed to other clocks. Further, in a configuration in which the output from one differential input amplifier 46 is supplied to each slot via the differential output amplifiers 47 for the number of other slots, one clock supply line is connected to each slot. As compared with a configuration in which clock signals are sequentially supplied, the differential signal has a higher noise immunity because of a one-to-one supply, so that the influence of noise is small, a sufficient supply current can be secured, and the clock signal received in each slot Not only has the advantage that the phase variation is extremely small, but also because the clock driver circuit is on the bus board and the signal pins are in the same position in each slot, both the side that outputs and receives the clock signal 1
Another advantage is that you do not need to be aware of one-to-one supply.

A local CPU and a local CPU bus 14 of the local CPU circuit board 15 are provided in order to control the above-described real-time processing of the video signal and the audio signal in synchronization with the reference clock. .

When an expansion slot is provided in the system bus, it is necessary to increase the number of slots via a bridge because of the restriction of fan-out. The fan-out number of one bridge is, for example, four, and four bridge ICs are required to provide 14 expansion slots as in the present embodiment.

FIG. 8 shows an extension structure of an expansion slot of a system bus using such a bridge. 8, regarding the system bus 2 of the bus board 31 of the information processing apparatus 1, for example, three expansion slots (corresponding to the connector 33) are provided in the system bus 2a to which a chipset such as the CPU 3 is connected. The system bus 2a is connected to the system bus 2 via a bridge circuit 61.
The system bus 2b is provided with four expansion slots (connectors 33) and a connector 36a for expanding the system bus. In the connector 36a,
The bus extension board 6a is inserted and mounted.
b is connected to the bridge circuit 62 on the bus extension board 6a, and the connector 3 of the bus board 41 on the extension processing apparatus 10 side is connected via the cable connecting portion 6b and the flat cable 6c.
6b, the bridge circuit 62 is connected to the bridge circuit 63 on the bus board 41. The bridge circuit 63 includes four bridge circuits 64a, 64a and 6b.
4b, 64c, and 64d are connected to each other, and extended system buses 12a, 12b, 12c, and 12d are connected to the bridge circuits 64a, 64b, 64c, and 64d, respectively.

In the embodiment shown in FIG. 8, a DMA (Direct Memory Card) is included in a system bus connected to the same bridge circuit.
Ory Access), a circuit board requiring DMA transfer is mounted in an expansion slot of a group belonging to the same bridge circuit. That is, since this DMA transfer is often performed between a digital signal encoding / decoding circuit and an interface circuit of a storage medium for the digital signal, the connector 43 of the system bus 12a connected to the bridge circuit 64a.
Includes a CODEC circuit board 21 for encoding / decoding a video signal and an interface circuit board 2 for video recording.
2 are inserted and mounted, and a DMA is
The connector 43 of the system bus 12c connected to the bridge circuit 64c is connected to a circuit board 26 for signal processing such as encoding / decoding of an audio signal and an interface circuit board 27 for audio recording. And DMA transfer is performed between these substrates 26 and 27.

As described above, by performing the DMA transfer in the system bus connected to the same bridge circuit,
Since the DMA transfer does not need to pass through a bridge circuit, a delay caused by passing through the bridge circuit (for example, 2
70 ns) does not occur, and high-speed and efficient data transfer can be performed.

As in the embodiment of FIG. 8, the bridge circuits 64a to 64d are directly connected to the bridge circuit 63, respectively, so that the bridge circuits 64a to 64d are parallel to each other. 64
Compared to a configuration in which d is connected in series, the delay time due to passing through a bridge circuit can be reduced.

The bus board 31 of the information processing apparatus 1
The delay time from the system bus 2a to which the chip set such as the CPU 3 and the like is connected to the system bus 12a to 12d to which each of the bridge circuits 64a to 64d is connected is equivalent to four bridge circuits, and When the delay time of the bridge circuits is, for example, 270 ns, the delay time (latency) of the four bridge circuits is 1080 ns.

By the way, as described above, in order to confirm whether or not a set of circuit boards on which DMA transfer is performed is inserted and mounted in the group of expansion slots connected to the same bridge circuit, the expansion slots and the circuit boards are checked. Each piece of identification information is obtained.

That is, as shown in FIG. 9, for each slot of the bus boards 41 and 42 on the extension processing apparatus 10 side,
A slot ID circuit 66 is provided to give unique (unique) identification information to the slot that can be distinguished from other slots, and an extension circuit board (expansion board) 54 outputs identification information unique to the board. Board ID circuit 67
Is provided.

In the example of FIG. 9, the slot ID circuit 66
The connector 45 is provided on the bus board 42 and connected to a predetermined pin of the connector 45.
The data is read by an identification circuit (not shown) on the extension board 54 via a. This slot ID
The circuit 66 may be connected to the connector 44, or the slot ID circuit 66 may be provided on the bus board 41 and connected to the connector 43. The slot ID circuit 66, for example, connects a resistor to a terminal pin of a connector, and grounds the other end of the resistor or gives a predetermined potential to represent 0 or 1, so that such a resistor is identified by the slot identification. In this embodiment, for example, four bits corresponding to four bits for identifying 14 slots can be provided, and if the value of the four bits of the slot ID circuit 66 is different for each slot, Good. The slot ID identification circuit (not shown) may be configured by hardware, but may be identified by software using a CPU or the like on the expansion board 54.

The board ID circuit 67 on the extension board 54 is connected to a connector 43a on the extension board, and this connector 43a is connected to the connector 43 on the bus board 41.
And is connected to the extended system bus 10 by being inserted and mounted. The board identification information sent to the system bus 10 is read by the CPU 3 or the like of the information processing apparatus 1 shown in FIG. 1 to identify the installed expansion board. As the board ID circuit 67, for example, a ROM or the like is used. The board ID circuit 67 may be connected to the connector 44a or the connector 45a, and the board may be identified by the circuit on the expansion device 10 side in FIG. 1, for example, by the local CPU 15 or the like.

As described above, the information of the slot ID identified by the identification circuit (not shown) on the extension board 54 is transmitted to the CPU 3 and the local CPU 15 via the system bus 10 and the local CPU bus 14 shown in FIG. And the like, and combining the result with the identification result of the extension board to determine whether or not a set of circuit boards on which DMA transfer is performed is inserted and mounted in the extension slot group connected to the same bridge circuit described above. it can.

Next, a power supply control method will be described.
As shown in FIGS. 1 and 3, the digital signal processing device of the present embodiment includes two units, namely, an information processing device 1 and an extended processing device 10, which are mechanically and electrically coupled. It is supposed to be. If the circuit scale becomes large, it is usual to provide a power supply circuit for each of the devices 1 and 10, but when power is turned on, it is necessary to observe the power-on sequence between these devices 1 and 10. There are many cases. For this reason, in the present embodiment,
A control signal is sent from one power supply to the other power supply.

That is, FIG. 10 shows a configuration in which a power supply device 72 dedicated to the extension processing device is provided on the extension processing device 10 side in addition to the power supply device 71 on the information processing device 1 side. In FIG. 10, the power supply 71 on the information processing apparatus 1 needs to start up faster than the power supply 7 on the extension processing unit 10. Therefore, a power on / off signal from the power switch 73 is transmitted to the power supply 71, and a power control signal output from the power supply device 71 is transmitted from the connector 36 a to the bus connection unit 6 (bus extension board 6 a, cable The power is supplied to the power supply device 72 for the expansion processing device via the connection portion 6b, the flat cable 6c) and the connector 36b via the bus board 41 of the expanded system bus, and controls on / off of the power supply device 72.

As described above, the power supply 72 on the side of the extension processing apparatus 10 is controlled by the power supply 71 of the information processing apparatus 1, so that the power supply 71 is activated after the power supply 71 is started up while maintaining the order of system reset. Control is performed so that 72 rises.

The present invention is not limited to the above-described embodiment. For example, the information processing device and the extended processing device may be integrated and housed in one housing. Further, the specific configuration of the DAV bus, the structure of the bus board, and the like are not limited to the illustrated example.

[0049]

According to the present invention, a system bus, arithmetic means connected to the system bus, one bridge means connected to the system bus for expanding the system bus, and Expansion system bus for bus expansion by having a plurality of other bridge means respectively connected to the bridge means and an expansion system bus for bus expansion respectively connected to these plurality of other bridge means The number of bridge means up to the above can be reduced, and the delay time can be reduced.

Further, DMA (Direct Memory Access) transfer is performed in the same expansion system bus among the expansion system buses for bus expansion connected to the other bridge means, so that the data can be transmitted through the bridge means. DM without
A transfer becomes possible, and high-speed data transfer without delay time by the bridge means can be realized.

Also, by reading the slot identification information and the board identification information and judging the combination thereof, it is determined whether or not a circuit board for performing DMA transfer between slots connected to the same bridge is mounted. Can be automatically determined.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a schematic configuration of a digital signal processing device according to an embodiment of the present invention.

FIG. 2 shows a DAV bus and a local CP in an extended processing device.
It is a figure showing a U bus.

FIG. 3 is a diagram showing a connection structure between an information processing device and an extended processing device of the digital signal processing device according to the embodiment of the present invention.

FIG. 4 is a diagram showing a connection structure between an information processing device and an extended processing device of the digital signal processing device according to the embodiment of the present invention.

FIG. 5 is a diagram illustrating another example of a coupling structure between the information processing device and the extension processing device of the digital signal processing device according to the embodiment of the present invention.

FIG. 6 is a diagram illustrating a specific example of an extension circuit board (extension board).

FIG. 7 is a diagram illustrating a specific example of clock supply.

FIG. 8 is a diagram showing a configuration for connecting a system bus via a bridge.

FIG. 9 is a diagram for explaining a board ID and a slot ID.

FIG. 10 is a diagram for explaining on / off control of a power supply.

[Explanation of symbols]

1 information processing device, 2 system bus, 3 CP
U, 6 bus connection unit, 10 expansion processing unit, 12
Extended system bus, 13 DAV bus, 14
Local CPU bus, 15 local CPU circuit board, 21 CODEC circuit board, 22 video recording interface circuit board, 23 disk device,
24 special effect circuit board, 26 audio signal processing circuit board, 27 audio recording interface circuit board, 31, 41, 42 bus board, 33, 36
a, 36b, 43, 44 connector, 46 differential input amplifier, 47 differential output amplifier, 61, 62, 6
3, 64a-64d bridge circuit, 66 slot ID circuit, 67 board ID circuit, 71, 72 power supply, 73 power switch

Claims (5)

[Claims] 1. A system bus, an arithmetic unit connected to the system bus, one bridge unit connected to the system bus for expanding the system bus, and one unit connected to the one bridge unit, respectively. A digital signal processing device comprising: a plurality of other bridge means; and an expansion system bus connected to the plurality of other bridge means for bus expansion. 2. A direct memory access (DMA) transfer is performed in the same expansion system bus among the expansion system buses for bus expansion connected to the other bridge means. The digital signal processing device according to claim 1. 3. A digital signal encoding and / or decoding circuit board and a digital signal recording interface circuit board are mounted in slots in the same extended system bus. Digital signal processor. 4. The digital signal processing device according to claim 3, wherein said arithmetic means determines the slot identification information for identifying said slot and the board identification information of an extension circuit board mounted in said slot. 5. An information processing unit having a system bus to which an arithmetic unit is connected, and an expansion processing unit for expanding the system bus, wherein a bridge unit is connected to a system bus of the information processing unit. 2. The digital communication system according to claim 1, wherein said one bridge means is connected via said means, and said expansion system unit is provided with said expansion system bus connected respectively via said plurality of other bridge means. Signal processing device.