JPH11328011A - Storage controller and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase the memory access speed in a storage device having plural memory chips. SOLUTION: In flash memories 18 to 20, output data are settled when 100 ns has elapsed after settlement of an address signal and a chip enable signal/CE and 40 ns has elapsed after settlement of an output enable signal/OE. Then, the same chip enable signal/CE1 is simultaneously supplied to plural flash memories 19 and 20 to accelerate the supply timing of the chip enable signal. The address signal is decoded to supply the output-enable signal or the write-enable signal to only one of flash memories 19 and 20, thus reading/writing data from/in one of them is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a storage control device and an information processing device suitable for use in a computer and its peripheral devices.

[0002]

2. Description of the Related Art (1) Regarding memory access timing FIG. 8 shows a general circuit configuration for accessing a flash memory. In the figure, the flash memory 18,
Reference numeral 19 denotes an output enable signal (read permission signal) / OE, a write enable signal (write permission signal) / WE, a chip enable signal (chip operation permission signal) / CE, and an address signal, similarly to a general memory. AD [18:
0] (19 address signals AD0 to AD18).
The flash memories 18 and 19 are also provided with data input / output terminals (not shown) for inputting / outputting data.

[0003] In the present specification, a signal including a “/” (slash) symbol in a name, such as “/ OE”, is a signal of negative logic, and “0” is an active state unless otherwise specified.
“1” becomes inactive. The flash memory 18 can write data when both the chip enable signal / CE and the write enable signal / WE are activated, and when both the chip enable signal / CE and the output enable signal / OE are activated, the data can be written. Reading becomes possible.

The north bridge 5 supplies the output enable signal / OE and the write enable signal / WE to the flash memories 18 and 19, and the corresponding flash memory 1 according to the value of the address signal AD [18: 0].
8 or 19 is supplied with a chip enable signal / CE0 or CE1, respectively. The "north bridge" integrates functions such as memory control and external bus control into one chip.

That is, the flash memories 18 and 19
Are actually accessed by a CPU or the like (not shown).
Will be output. Next, FIG. 9 shows an example of a timing chart when reading the flash memories 18 and 19. In the flash memories 18 and 19, 100 ns or more have passed since the address signal was determined, and 100 ns since the chip enable signal / CE was determined.
40 minutes after the above and the output enable signal / OE is determined
Output data is determined when the three conditions of ns or more are satisfied.

(2) Access Mode In the north bridge 5, two access modes, a single access mode and a burst access mode, can be selected. Here, the single access mode is a mode in which only one address is read in one access, and the burst access mode is a mode in which a plurality of continuous addresses are continuously read.

Here, a timing chart in the single access mode is shown in FIG. FIG. 2A shows a CPU.
This is a bus clock (clock synchronized with a CPU not shown) and has a cycle of 15 ns. tACC is an access time, which indicates a time required until reading. The access time tACC needs to be secured for the flash memories 18 and 19 for 100 ns or more (see FIG. 9). However, in FIG. 10, since all signals are synchronized with the CPU bus clock, an access time tACC is 105 ns, which is a multiple of 15 ns (7 clocks).

After the data reading is completed, an empty cycle tWAIT is secured for various timing adjustments. An empty cycle tWAIT is secured, for example, for 5 clocks (75 ns). Then, in the single access mode, a total of 12 clocks (180 ns) are required for one memory access.

Next, a timing chart in the burst access mode is shown in FIG. In this mode, the address signal is continuously changed as shown in FIG. First, in the first read cycle, the access time tACC is the same as in the single access mode.
The first data DATA0 is read using (7 clocks). In the next three clocks, the address signal is changed to the next address, and the next data DATA1 is read. Thus, the time (3 clocks) spent for the second and subsequent readings is called a burst cycle tBST.

Similarly, the burst cycle tBST is further repeated twice, and the data DATA2 and DATA3 are sequentially read. Thereafter, an empty cycle tWAIT (5 clocks) similar to the single access mode is secured. Therefore, in the burst access mode, a total of 21 (= 7 + 3 × 3 + 5) clocks for four accesses, that is, 315
Since only ns are spent, efficient access is possible.

(3) Regarding Reduction of Power Consumption In a computer or the like, a technique for reducing power consumption in an unused state is known. For example, in a general notebook personal computer, a technique of operating at a clock frequency of 66 MHz and changing the clock frequency to 33 MHz unless a user operation is detected for a predetermined time or more is used.

[0012]

(1) Regarding memory access timing In the circuit shown in FIG.
Since it is assumed that a chip flash memory is used, two chip enable signals / CE0 and CE1 are output. Therefore, in order to use more flash memories, it is necessary to provide an additional decoder. In order to select one memory chip from a plurality of memory chips, generally, an address signal is decoded and one of the chip enable signals is selectively output.

FIG. 12 shows a configuration in which memory chips more than the number of chip enable signals output from the north bridge 5 can be selected by such a general method. In the figure, a decoder comprises OR circuits 21 and 22 and an inverter 2
3 is provided. The OR circuit 21 has a chip enable signal / C
E1 becomes active state “0” and the address signal
When the AD 19 is “0”, the chip enable signal / CEFM 1 which becomes the active state “0” is supplied to the flash memory 19.

The inverter 23 inverts the address signal AD19. The OR circuit 22 enters the active state "0" when the chip enable signal / CE1 is in the active state "0" and the output signal of the inverter 23 is "0" (the address signal AD19 is "1"). The chip enable signal / CEFM2 is supplied to the flash memory 20. Thus, when the chip enable signal / CE1 is in the active state, one of the flash memories 19 and 20 becomes readable or writable according to the value of the address signal AD19.

In the configuration of FIG. 12, address signal AD
19 sequentially passes through the two gate circuits (23, 22) before being converted into the chip enable signal / CEFM2. Here, the delay time of one gate circuit is 6n
s, it takes 12 ns from when the address signal AD19 is determined to when the chip enable signal / CEFM2 is determined.
Will be required. Here, a timing chart in the flash memory 20 is shown in FIG. In the figure, the chip enable signal / CEFM1 is determined 6 ns after the address signal is determined, the chip enable signal / CEFM2 is determined 6 ns later, and the read data is determined 100 ns later.

Here, the number of clocks required for memory access in the configurations shown in FIGS. 8 and 12 is obtained. First, in the configuration of FIG. 8, at least 100 ns is required as the access time tACC. Therefore, a 15 ns C
The number of clocks required for the PU bus clock is as follows: ROMSMPL0 ≧ {100 (nS) ÷ 15 (nS / CLK)} = 6.67∴ROMSMPL0 = 7

Next, the number of clocks required for the flash memory 19 in FIG. 12 is as follows: ROMSMPL1 ≧ [{100 (nS) +6 (nS)} 15 (nS / CLK)] =
7.06∴ROMSMPL1 = 8, and the number of clocks required for the flash memory 20 is ROMSMPL2 ≧ [｛100 (nS) +12 (nS)｝ ÷ 15 (nS / CLK)]
= 7.47 ∴ROMSMPL2 = 8.

That is, in the configuration of FIG. 12, since the data is determined after 106 ns or 112 ns elapses after the address signal is determined, the access time tAC
C requires 8 clocks (120 ns). Further, as described above, an empty cycle tWAIT is secured after the data reading is completed. Assuming that the idle cycle tWAIT is 5 clocks and the CPU bus clock is 66 MHz, the number of instructions that can be accessed per second in each case is as follows.

When ROMSMPL = 7, 66 MHz ÷ (7CLK + 5CLK) ≒ 5,555,56 instructions When ROMSMPL = 8, 66MHz ÷ (8CLK + 5CLK) ≒ 5,128,205 instructions Thus, the number of clocks required for access is 8 clocks. , The performance of the device is at worst 92% ($ 5
130,560,000).

(2) Access Mode As described above, in the north bridge 5, two access modes, a single access mode and a burst access mode, can be selected. It is assumed that they are compatible. That is, in the conventional technique, when the memory itself does not support the burst access mode, the single access mode must be selected in the north bridge 5, and it is difficult to increase the access speed.

(3) Reduction of Power Consumption As described above, in a notebook personal computer or the like, power consumption can be reduced by changing the clock frequency. However, since there is a limit to the adjustment of power consumption based on only the clock frequency, it has been difficult to perform various power consumption adjustments according to processing contents.

The present invention has been made in view of the above-mentioned circumstances, and has as its first object to provide a storage control device and an information processing device which enable high-speed memory access. It is a second object of the present invention to provide a new technique for adjusting power consumption according to the processing content.

[0023]

According to a first aspect of the present invention, there is provided a storage control device for controlling access to a plurality of storage devices. Control means is provided for simultaneously providing a selection signal to be selected, and thereafter providing an access signal indicating read or write to a storage device to be accessed. With the configuration described above, the control means operates to simultaneously provide the plurality of storage devices with a selection signal (for example, / CE) for selecting these storage devices, and each of the storage devices will now perform the first operation. Will be accessible after hours. Further, the control means operates to provide an access signal (for example, / OE or / WE) to a storage device to be subsequently accessed, so that the storage device can be accessed after the second time indicated by the access signal. Generally, the second time (for example, 40 ns) is more than the first time (for example, 100 ns).
Since s) is large and the second time elapses within the first time, the storage device can be accessed faster than before.

According to a second aspect of the present invention, in the storage control device for controlling access to one or more storage devices, a ratio of an operation period and a non-operation period in a selection signal for selecting the one or more storage devices is set. An operation period control means for controlling according to the use condition of the storage device is provided. With the configuration described above, the operation period control means operates to control the ratio of the operation period to the non-operation period in the selection signal according to the use condition of the storage device. For example, since the ratio of the non-operation period is made larger than the operation period in the selection signal by judging the operation time and the standby time, that is, the non-operation period is made longer, the power consumption is appropriately reduced according to the use condition of the storage device. Becomes possible.

According to a third aspect of the present invention, there is provided a storage controller for controlling access to at least one storage device for a single access mode for performing a single access.
In a burst access mode in which a plurality of accesses are continuously performed, a burst control means for controlling the one or more storage devices in the same access time is provided. With the configuration described above, the burst control means performs a plurality of continuous accesses to the storage device for the single access mode, that is, the storage device having no burst access mode at the same access time. No waiting time (for example, tWAIT) is required, and high-speed access is possible.

According to a fourth aspect of the present invention, there is provided a storage control device for controlling access to at least one storage device, comprising: a single access mode for performing a single access;
And a mode switching control means for switching between a burst access mode and a use state of the storage device in accordance with a use condition of the storage device. With the configuration as described above, the mode switching control means includes a single access mode for performing a single access,
The storage device operates so as to switch between a burst access mode and a burst access mode in accordance with the use condition of the storage device. ), It is possible to set appropriate power consumption according to the use situation, and to reduce power consumption.

According to a fifth aspect of the present invention, there is provided an information processing apparatus including the storage control device according to any one of the first to fourth aspects. Therefore, it is possible to provide a high-speed and low-power-consumption information processing device by utilizing the features of these storage control devices. It is preferable to have a prediction means for predicting the use status of the storage device according to claims 2 and 4. For example, the use status of the storage device can be predicted by a job for the information processing device. If the information processing device is a printer, the use state is predicted according to the content of the print job or the presence or absence of the print job, and the control according to claims 2 and 4 is performed based on the predicted use state, so that the storage device Access is possible, and low power consumption and power saving can be realized.

[0028]

BEST MODE FOR CARRYING OUT THE INVENTION Next, a printer control device according to an embodiment of the present invention will be described with reference to FIG. In the figure, a CPU 4 controls other components via an address bus 51, a data bus 52, a PCI bus 53, and an ISA bus 54 based on a control program. The north bridge 5 performs arbitration of the bus of the CPU 4, memory control, conversion from the address bus 51 and the data bus 52 to the PCI bus 53, and the like.
It operates in synchronization with a 6 MHz or 33 MHz bus clock. Further, under the control of the CPU 4, the north bridge 5 can set various timing parameters in a programmable manner.

The flash memory unit 7 includes three slots of flash memories 18 to 20 and a decoder. Each slot can read and write data via an address bus 51 and a data bus 52. The dynamic memory 8 is of a synchronous type. The cache memory 6 temporarily stores data read and written to the flash memory unit 7 or the dynamic memory 8 and improves the operation speed of the CPU 4.

A network interface or the like is connected to the expansion slot 10. Font ROM 11 is
Stores various font data. The image interface 12 exchanges image data with a printer engine or a scanner (not shown). The south bridge 9 performs mutual conversion between the PCI bus 53 and the ISA bus 54, and includes an interrupt controller, a general-purpose timer, a real-time clock, a general-purpose input / output port, and the like.

The battery-backed static RAM 13 stores various user setting information. The serial interface 14 and the parallel interface 15 are used for connection with an external host computer or the like. The dual port RAM 16 has an external fax
Transfers data to and from modules.

Next, the detailed configuration of the flash memory unit 7 is shown in FIG. In the figure, the same reference numerals are given to portions corresponding to the respective portions in FIG. In the figure, the connection relationship between the north bridge 5 and the flash memory 18 is the same as that of FIG. 12, but the flash memories 19 and 20 are different. First, as the chip enable signal / CE of the flash memories 19 and 20, the chip enable signal / CE1 is supplied as it is.

In the figure, the decoder includes OR circuits 28 to 31 and an inverter 32. The OR circuit 28
When the output enable signal / OE output from the north bridge 5 is in the active state "0" and the address signal AD19 is "0", the output enable signal / OE for the flash memory 19 is changed to the active state. Set to "0". Similarly, the OR circuit 29
Write enable signal output from north bridge 5
When / WE is in the active state "0" and the address signal AD19 is "0", the write enable signal / WE for the flash memory 19 is changed to the active state "0".
Set to.

The inverter 32 inverts the address signal AD19. When the output enable signal / OE output from the north bridge 5 is in the active state “0” and the address signal AD19 is “1”, the OR circuit 30 outputs the output enable signal / OE is set to the active state “0”.
Similarly, the OR circuit 31 sets the write enable signal / WE output from the north bridge 5 to the active state “0”.
And the address signal AD19 is "1", the write enable signal / W for the flash memory 20 is
E is set to the active state “0”.

2. Operation of Embodiment 2.1. Access Timing Next, the operation of the present embodiment will be described with reference to FIG. FIG. 3 shows an example in which reading from the flash memory 20 is performed. In the figure, the north bridge 5 outputs an address signal and a chip enable signal / CE at time t1.
1 and output enable signal / OE.
The output enable signal / OE and the address are output as the output enable signal / OEFM2 via the inverter 32 and the OR circuit 30. Here, assuming that the delay time of one gate circuit is 6 ns, an address signal and an output enable signal
Output enable signal / OEFM2 after / OE is determined
It takes 12 ns until is determined. This timing is indicated by time t2 in FIG.

As described above, the flash memories 18 to
One of the conditions for determining the output data at 20 is that 40n after the output enable signal is determined.
s or more must have elapsed. The output enable signal / OEFM2 is determined with a delay of 12 ns as compared with the address signal and the chip enable signal / CE1, but within the time from when the address signal and the chip enable signal / CE1 are determined to 100 ns elapses. Can sufficiently satisfy this condition.

As a result, the timing at which the output data is determined in FIG. 3 is the time t3, which is 100 ns after the time t1, and the output data can be read after 7 clocks (after the time t4, 105 ns). Note that this operation is the same when writing data to the flash memory 20 and when writing or reading the flash memory 19.

As described above, in this embodiment, the output enable signal or the write enable signal having a sufficient time is decoded, and the chip enable signal / CE1 is transmitted to the flash memories 19 and 20 without using the decoding circuit. Since they are supplied at the same time, a decrease in access speed based on the operation time of the decoding circuit can be suppressed.

2.2. Setting in Burst Access Mode As described in FIG.
In the single access mode, the memory access is performed within the access time tACC, and an empty cycle tWAIT is provided thereafter. However, a normal flash memory can operate without necessarily providing the empty cycle tWAIT.

Therefore, if the empty cycle tWAIT can be removed from FIG. 10, the memory access can be speeded up. Therefore, in the present embodiment, the flash memory 1 which does not originally support the burst access mode is used.
Burst access is performed for 8 to 20 to reduce the empty cycle tWAIT.

That is, in this embodiment, when it is necessary to read a plurality of consecutive addresses of the flash memories 18 to 20 at high speed, the CPU 4 sets the north bridge 5 to the burst access mode. At this time, the burst cycle tBST in FIG. 11 is set (to 7 clocks) so as to be equal to the access time tACC. In such an operation, one empty cycle tWAIT (5 clocks) is generated every time the memory is accessed four times.

Accordingly, the number of clocks required for accessing these four addresses is 33 clocks (= 7 clocks × 4 + 5).
Clock), and the number of clocks per address is 8.25 clocks. As described above, in the single access mode, a total of 12 clocks (= 7 clocks + 5 clocks) are required for one address access, so that the access speed can be improved by about 70% at the maximum.

2.3. Power Consumption Reduction Operation 1 The current consumption of the flash memories 18 to 20 used in this embodiment is 35 mA during a read operation and 5 μA during a standby operation (when the chip enable signal / CE is negated). In FIGS. 10 and 11, "during standby operation" is nothing less than the period of the idle cycle tWAIT, and the ratio of the standby operation performed within a fixed time, that is, the duty ratio is 41.67% (= 5).
CLK / (7CLK + 5CLK)) and 15.15% (= 5CLK)
/ (7 CLK × 4 beats + 5 CLK)).

Therefore, the average current consumption in the single access mode is 35000 μA × (1−0.4167) +15 μA ×
0.4167 ≒ 20.422 mA. On the other hand, the average current consumption in the burst access mode is 35000 μA × (1-0.1515) +15 μA ×
0.1515 ≒ 29.699 mA. As described above, when the access mode is set to the single access mode particularly when high-speed access is not required, power consumption can be reduced.

2.4. Power consumption reduction operation 2 If the empty cycle tWAIT can be programmably changed in the north bridge 5, by changing the empty cycle tWAIT in FIGS. 10 and 11 according to the required processing load, particularly high-speed access is required. If not, the period of the empty cycle tWAIT may be lengthened. Thereby, the duty ratio of the standby operation can be increased, and the power consumption can be further reduced.

2.5. Power Consumption Reduction Operation 3 Further, as described above, a technique for reducing the power consumption by changing the CPU bus clock (for example, 66 MHz → 33 MHz) is known, but in the present embodiment,
Further, by changing the number of clocks related to the access time tACC, power consumption can be further reduced. That is, the CPU bus clock is changed from 66 MHz to 3
When reduced to 3 MHz, the access time t of 100 ns
The number of clocks for securing ACC is 7 (15n
s × 7 = 105 ns) to 4 clocks (30 ns × 4 =
120 ns). At this time, if the number of clocks related to the empty cycle tWAIT is kept at "5", the duty ratio can be increased.

2.6. Overall Operation Next, the overall operation of the present embodiment will be described. When the power of the printer control device shown in FIG. 1 is turned on, a mode setting program shown in FIG. 4 is started. Since the CPU 4 operates in a multi-task manner, programs for executing various tasks such as data input / output and image development are started in parallel as necessary in addition to this program.

In FIG. 4, when the process proceeds to step SP1, the operation mode of the printer control device of the embodiment is set to the minimum mode (the mode in which both the processing capacity and the power consumption are the minimum). Specifically, the access mode of the north bridge 5 is set to the single access mode, and the CPU bus clock is set to 33 MHz. The access time tACC is set to 4 clocks (30 ns × 4 = 120 ns), and the empty cycle tWAIT is set to 5 clocks (30 ns).
× 5 = 150 ns).

Next, when the process proceeds to step SP2, it is determined whether print data has been supplied from the serial interface 14 or the parallel interface 15 or the like, and the process waits until print data is detected. As a result, the operation mode is maintained at the minimum mode. Here, when the print data is detected, the process proceeds to step SP3, and the operation mode is set to the intermediate mode (mode in which both the processing power and the power consumption are medium). That is, the CPU bus clock is increased to 66 MHz,
Correspondingly, the clock number of the access time tACC is 7
Changed to clock.

When print data is supplied to some extent,
The image development task is activated, and image data to be output is generated based on the print data. Next step SP
In 4, it is determined whether or not the image development has been started, and the intermediate mode is maintained until the image development is started. Here, when the start of image development is detected, the process proceeds to step SP5, and the operation mode is set to the maximum mode.

In the maximum mode, the CPU bus clock is 66 MHz and the access time tACC is 7 clocks, which are the same as those in the intermediate mode. However, the access mode of the north bridge 5 is set to the burst access mode, and the burst cycle tBST is set to 7 clocks equal to the access time tACC. This allows
Image expansion is performed promptly, and the expanded image is output.

3. Modifications The present invention is not limited to the embodiments described above,
For example, various modifications are possible as follows. (1) In the above embodiment, three types of operation modes, ie, the minimum mode, the intermediate mode, and the maximum mode, are switched. However, the number of operation modes may be two or four or more. In the above embodiment, the idle cycle tWAIT is fixed to 5 clocks in any of the operation modes. However, it goes without saying that the idle cycle tWAIT may be changed according to the operation mode.

FIG. 4 when the empty cycle tWAIT is changed
FIG. 5 shows a modification of the flowchart of FIG. In the figure, when the power is turned on, the process proceeds to step SP11, and the empty cycle tWAIT is set to "5 clocks" (maximum mode). Next, the process proceeds to step SP12, and it is determined whether print data is stored. If "NO" is determined here, the process proceeds to step SP13, and the idle cycle tWAIT is set to "20 clocks" (minimum mode). Then, the process proceeds to step SP14, where it is determined whether print data has been received,
If received, the process proceeds to step SP11, and the operation mode is returned to the maximum mode.

(2) Similarly, in two types of operation modes, the CP
FIG. 6 shows a modification in which the U bus clock and the access time tACC are changed. In the figure, step SP22,
In SP24, the same determination as in steps SP12 and SP14 is performed. If print data has been received, the CPU bus clock is set to 66 in step SP21.
MHz and access time tACC is 7
Set to clock. If the print data is not stored, the access time tACC is 33 MHz.
z, and the access time tACC is changed to three clocks.

(3) Similarly, the flash memories 18 to 2
FIG. 7 shows a modification in which the operation mode is changed by changing only the 0 access mode. In the figure, in steps SP32 and SP34, in steps SP12 and SP1,
The same determination as in No. 4 is performed. If the print data has been received, the access mode is set to the burst access mode in step SP31. If print data is not stored, step SP
At 33, the access mode is set to the single access mode.

(4) In the above embodiment, an example in which the present invention is applied to the flash memory unit 7 of a printer control device has been described. The present invention can be applied to other semiconductor memories, magnetic disks, optical disks, and the like.
Further, the information processing apparatus of the present invention is not limited to the printer control apparatus, but includes various apparatuses that can execute the above-described memory access method, such as various computers, their peripheral apparatuses, and game apparatuses.

[0057]

As described above, according to the first aspect of the present invention, a selection signal for selecting a plurality of storage devices is simultaneously supplied to a plurality of storage devices, and thereafter, a storage device to be accessed is accessed. Since the signal is given, the storage device can be accessed quickly. According to the second aspect of the present invention, the ratio between the operation period and the non-operation period in the selection signal can be controlled according to the use state of the storage device.
Power consumption can be appropriately reduced. According to the third aspect of the present invention, a plurality of accesses are made continuously for a single access mode, that is, a storage device having no burst access mode at the same access time, so that a wait between successive accesses is made. Time (for example, tWAIT) is not required, and high-speed access is possible. Also,
According to the fourth aspect of the present invention, since the single access mode and the burst access mode are switched according to the usage status of the storage device, appropriate power consumption can be set according to the usage status, and power consumption is reduced. be able to.
In addition, the invention according to claim 5 includes the storage control device according to any one of claims 1 to 4, so that the speed of the information processing apparatus can be reduced or the power consumption can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a printer control device according to an embodiment.

FIG. 2 is a block diagram of a main part of the printer control device.

FIG. 3 is a timing chart of each unit in FIG. 2;

FIG. 4 is a flowchart of a program executed by a CPU 4;

FIG. 5 is a flowchart of a modification of the embodiment.

FIG. 6 is a flowchart of another modification of the embodiment.

FIG. 7 is a flowchart of another modification of the embodiment.

FIG. 8 is a circuit diagram of a conventional memory control device.

FIG. 9 is a timing chart in FIG.

FIG. 10 is a timing chart in a single access mode.

FIG. 11 is a timing chart in a burst access mode.

FIG. 12 is a circuit diagram in which a decoding circuit is added to a conventional memory control device.

FIG. 13 is a timing chart of FIG.

[Explanation of symbols]

 4 CPU 5 North Bridge 6 Cache Memory 7 Flash Memory 8 Dynamic Memory 9 South Bridge 10 Expansion Slot 11 Font ROM 12 Image Interface 13 Static RAM 14 Serial Interface 15 Parallel Interface 16 Dual Port RAM 18-20 Flash Memory 21,22 OR Circuit 23 Inverter 28-30 OR circuit 32 Inverter 51 Address bus 52 Data bus 53 PCI bus 54 ISA bus

Claims (5)

[Claims] 1. A storage control device for controlling access to a plurality of storage devices, wherein a selection signal for selecting these storage devices is given to the plurality of storage devices at the same time, and thereafter, a read or read operation is performed to a storage device to be accessed. A storage control device comprising control means for giving an access signal indicating writing. 2. A storage control device for controlling access to one or more storage devices, wherein a ratio of an operation period and a non-operation period in a selection signal for selecting the one or more storage devices is determined according to a use state of the storage device. A storage control device comprising an operation period control means for controlling. 3. A storage control device for controlling access to one or more storage devices for a single access mode for performing a single access, wherein a burst access mode for continuously performing a plurality of accesses and the same access time. A storage control device comprising a burst control means for controlling the one or more storage devices. 4. A storage control device for controlling access to one or more storage devices, wherein a mode switching control means for switching between a single access mode for performing a single access and a burst access mode in accordance with the use condition of the storage device. A storage control device comprising: 5. An information processing apparatus comprising the storage control device according to claim 1.