JPH11328001A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance the processing performance by executing a following instruction before completion of data read without increasing the number of write ports of a register file at the time of reading out plural data from a memory device by one instruction. SOLUTION: When the instruction decoded by a decoder 1 is an instruction to read out plural data, plural read data are stored in latches L0 to L3 of a read data holding circuit 6, and data are read out from the latch corresponding to a designated read register to perform the operation in following instructions. Correspondence between latches L0 to L3 and registers is designated by the write destination register number of the multiple data read instruction. Storage on read data into latches L0 to L3 and update of a register file 2 due to a following instruction are performed in parallel in this manner, thereby the processing performance is enhanced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an information processing apparatus for reading a plurality of data from a memory device and performing an operation.

[0002]

2. Description of the Related Art With the recent development of electronic technology, information processing devices such as microcomputers have become widespread and used in all fields.

Conventionally, information processing apparatuses often perform pipeline processing in order to improve processing performance. The pipeline processing divides the processing of one instruction into a plurality of stages, and shifts these stages to execute a plurality of instructions in parallel.

FIG. 11 is a block diagram showing a configuration of a conventional information processing apparatus. Reference numeral 101 denotes a decoder for decoding an instruction 120 read from a memory device 140, and the decoded results 113 and 114, which are included in the instruction. An immediate 121 is output.

[0005] Reference numeral 102 denotes a register file having a plurality of registers for storing data used for calculation, and 103 denotes data 110 and 11 read from the register file 102.
1 or an arithmetic unit 104 that performs an operation using the immediate value 121 output from the decoder 101. The arithmetic unit 104 reads data from the memory device 140 or sends data to the memory device 140 in accordance with a decoding result 113 obtained by decoding an instruction by the decoder 101. A memory control circuit 105 for performing control for writing or the like is an execution control circuit for controlling the arithmetic unit 103 or the register file 102 according to a decoding result 114 obtained by decoding an instruction in the decoder 101.

A description will be given of a case where, in the conventional information processing apparatus, for example, one instruction is divided into five stages and pipelined.

The five stages are an instruction fetch stage
(Hereinafter referred to as IF stage), instruction decode stage (hereinafter referred to as DEC stage), operation stage (hereinafter referred to as EX stage), memory stage (hereinafter referred to as MEM stage), and write stage (hereinafter referred to as WB stage). . The instruction is read from the memory device 140 in the IF stage, and the read instruction 120 is decoded by the decoder 101 in the DEC stage.

If the decoded instruction is an operation instruction, the operation specified by the instruction is performed using the data 110 and 111 read from the register file 102 or the immediate value 121 output from the decoder 101 in the EX stage. The result of the operation is stored in the register in the register file 102 specified by the instruction in the WB stage.

If the decoded command is a data read command or a data write command, the arithmetic unit 103 uses the data 110 and 111 read from the register file 102 or the immediate value 121 given by the command in the EX stage. , An address 115 indicating a location in the memory device 140 and output to the memory control circuit 104.

If the decoded instruction is a data read instruction, the memory control circuit 104 outputs the address 115 output by the arithmetic unit 103 as the address 116 in the MEM stage, and reads and reads data from the memory device 140. The data 117 given is given to the register file 102 and stored in a designated register in the register file 102 in the WB stage. If the decoded instruction is a data write instruction, the data 118 read from the register file 102 is given to the memory device 140 in the MEM stage, and at the same time, the memory control circuit 104
5 to the memory device 140 as an address 116,
Data 1 to the location specified by address 116 in the stage
18 is stored.

FIG. 12 shows an example of a pipeline operation of the conventional information processing apparatus. FIG. 12 shows a state in which four instructions are being executed, and r0, r1, r2, and r4 are the names of the registers in the register file 102. Also,
(r4) indicates data in the memory device designated by using the value of the register r4 as an address. The first instruction and the third instruction are data read instructions ld, and the second instruction and the fourth instruction are addition instructions add.

The first instruction ld reads data from the memory device 140 using the value of the register r4 as an address and stores the data in the register r0. The second instruction add adds the value of the register r2 to “1” and stores the addition result in the register r2. The third instruction ld adds “4” to the value of the register r4, reads data from the memory device 140 using the result as an address, and stores the data in the register r1. 4th instruction add
Adds the value of the register r2 to “1” and stores the addition result in the register r2.

Each instruction is divided into five stages of IF, DEC, EX, MEM, and WB, and each stage is executed during one clock cycle. The four instructions are executed in parallel, shifted by one stage. Therefore, processing of each instruction requires five clock cycles. By performing such pipeline processing, a result of an instruction can be obtained every cycle, and high processing performance can be realized. it can.

[0014]

When processing image or audio data, a large amount of data must be read from a memory device and processed at high speed. In many cases, image data or audio data is continuously stored in addresses on a memory device. If a plurality of continuous data can be read out at a time, efficient and high-speed processing can be performed.

FIG. 13 shows an operation example in the case where a plurality of data are read by a plurality of data read command and used for the operation. In FIG. 13, the first instruction ldq is a multiple data read instruction, and four consecutive data D0, D1,
Read D2 and D3, four registers r0, r1, r2, r
3 is stored. The data of the four registers r0, r1, r2, and r3 are added by four addition instructions from the third instruction to the sixth instruction, and the total value is stored in the register r5. The write stage of the multiple data read instruction ldq has four stages W
B0, WB1, WB2, WB3, and data D0, D1, read from the memory device 140 at each stage.
D2 and D3 are written to registers r0, r1, r2 and r3, respectively.

The second instruction mov stores the value "0" in the register r5, but cannot store "0" in the register r5 until all the data has been stored in the register by the first instruction ldq. This is the register file 102
Is a single write port and cannot write two data at the same time. As described above, by using the multiple data read instruction, a plurality of data can be read by one instruction. However, the WB stage of the subsequent instruction must be executed until all of the plurality of read data is stored in the register. However, there is a problem that the processing performance cannot be improved much.

Therefore, if a plurality of data are simultaneously read from a memory device by reading a plurality of data and a plurality of data are simultaneously written to a plurality of registers, processing of a subsequent instruction can be performed immediately, and processing performance can be improved. Can be improved. However, in order to write a plurality of data to a plurality of registers at the same time, it is necessary to provide a plurality of register file write ports, which causes a problem of an increase in circuit scale.

When a plurality of data having a smaller number of bits than the number of bits of the register are read, for example, when the number of bits of the register is 32 bits and four data of 8 bits are read, four 8-bit data are read. The concatenated data is read out as 32-bit data, the 32-bit data is stored in one register, and then processed by taking out 8 bits at a time using some instructions. In this case, a plurality of instructions for extracting 8-bit data from a 32-bit register are required, which causes a problem that processing performance is reduced.

Further, when a plurality of data are read and stored in a plurality of registers, the data previously held in the plurality of registers is temporarily saved in a memory device or the like, and the data read by a plurality of data read commands is read. After the above processing is completed, it is necessary to restore the data saved in the memory device to the register, which causes a problem that the processing performance is reduced.

The present invention has been made in view of the above-mentioned conventional problems,
Even if you execute an instruction to read multiple data from memory,
It is an object of the present invention to provide an information processing device that enables execution of a subsequent instruction before reading of all of a plurality of data is completed, and has high processing performance.

[0021]

In order to solve the above problems, an information processing apparatus according to the present invention comprises: a memory device for storing a plurality of data; a register file having a plurality of registers for storing the data; And an instruction decoding means for decoding the instruction, decoding the instruction, and outputting a multiple data read signal when the decoded instruction is a multiple data read instruction. Command execution control means for controlling the operation by the operation means and the reading and writing of data from and to the register file in accordance with the decoding result to be read; Memory control means for reading, and a plurality of data read from the memory device according to the plurality of data read signals. A data holding unit for holding data, a data reading unit for reading data corresponding to a read register indicated by the decoding result from among the data held in the data holding unit, and outputting a data selection signal; Data selecting means for selecting data read from the register file or data read from the data holding means according to a selection signal and outputting the selected data to the arithmetic means.

Also, the information processing apparatus of the present invention has a memory device for storing a plurality of data, a register file having a plurality of registers for storing the data, an arithmetic means for performing an arithmetic operation using given data, And, in the case where the decoded result is a multiple data read instruction, a command decoding means for outputting a multiple data read signal, and the arithmetic means in accordance with the decryption result output by the command decode means. Command execution control means for controlling operation and reading and writing of data to and from the register file; memory control means for reading a plurality of data from the memory device when the plurality of data read signals are provided; Data holding means for holding a plurality of data read from the memory device, A data valid flag indicates that the data in the serial data holding means is stored, among the data held in the data holding means, it reads the data corresponding to the read register indicated by the decoding result,
Data reading means for outputting a data selection signal, and data selection means for selecting data read from the register file or data read from the data holding means and outputting the selected data to the arithmetic means according to the data selection signal. The data reading unit outputs an execution stop signal when reading data from the data holding unit, when the data valid flag indicates that data is not stored in the data holding unit. To stop the processing of the instruction.

Further, the information processing apparatus of the present invention has a memory device for storing a plurality of data, a register file having a plurality of registers for storing the data, an arithmetic means for performing an arithmetic operation using given data, And, in the case where the decoded result is a multiple data read instruction, a command decoding means for outputting a multiple data read signal, and the arithmetic means in accordance with the decryption result output by the command decode means. Command execution control means for controlling operations and reading and writing of data to and from the register file; and memory control means for reading a plurality of data from the memory device and outputting the data to a data bus when the plurality of data read signals are provided. And takes out data from a specific position on the data bus according to the size of the data and outputs the data. Data extracting means, data holding means for holding a plurality of data output by the data extracting means in accordance with the plurality of data read signals, and, among the data held in the data holding means, designated by the decryption result. Reading data corresponding to a read register and outputting a data selection signal; and selecting and reading data read from the register file or data read from the data holding means according to the data selection signal. Data selecting means for outputting to the calculating means.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS.

FIG. 1 is a block diagram showing the configuration of an information processing apparatus according to a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes an instruction for decoding an instruction 20 read from a memory device 40, and decode results 13, 14 and A decoder for outputting an immediate 21 included in the instruction 20; a register file 2 having a plurality of registers for storing data used for the operation;
Is an arithmetic unit that performs an operation using given data 10 and 11 or an immediate 21 output by the decoder 1. The arithmetic unit 4 reads data from the memory device 40 or stores data in the memory 40 in accordance with the decoding result 13 of the decoder 1. A memory control circuit for controlling writing to the device 40;
Is an execution control circuit that controls the arithmetic unit 3, the register file 2, and the like according to the decoding result 14 of the decoder 1,
6 includes four latches L0, L1, L2, L3 and a selection circuit 30.
And a read data holding circuit for temporarily holding data read from the memory device 40 by a multiple data read command, wherein the four data read from the memory device 40 are latches L0, L1, L2, Stored in L3.

Reference numerals 22 and 23 indicate selection signals 3
A selection circuit that selects either the data output from the selection circuit 30 of the read data holding circuit 6 or the data output from the register file 2 and outputs the selected data to the arithmetic unit 3 as the input data 10 and 11 in accordance with 5, 36. ,
Reference numeral 31 denotes a data read control circuit that outputs a read control signal 32 to the selection circuit 30 to read data stored in the four latches L0 to L3, and outputs selection signals 35 and 36 at the same time.

FIG. 2 is a block diagram showing the configuration of the data read control circuit 31. Reference numeral 33 denotes a register information circuit for holding register information corresponding to data stored in latches L0 to L3, and E0, E1, and E2. , E3 are read enable bits indicating whether data stored in the latches L0, L1, L2, L3 are to be read, respectively. When a register read is requested by the decode result 26, the corresponding data is latched in the latch L0. A control circuit that outputs the read control signal 32 if it is held at L3 and outputs the select signals 35 and 36 at the same time.

In the first embodiment, as in the conventional example shown in FIGS. 11 to 13, five stages of the IF stage, the DEC stage, the EX stage, the MEM stage, and the WB stage are used.
Processes instructions in two stages. Data read, data write, and operation instructions other than the multiple data read instruction are processed in the same manner as in the related art.

The processing of a multiple data read command will be described. The multiple data read command reads a plurality of data from the memory using the designated address, and reads the read data from the plurality of latches L of the data holding circuit 6.
Store it in 0 to L3. In a conventional example, a plurality of read data are stored in a register file, but in the first embodiment, they are not stored in a register file. The multiple data read instruction includes the register number of the write destination, and the data held in the read data holding circuit 6 is associated with the write destination register. In the subsequent instructions, when the associated register is designated as a read register, the corresponding data is read from the read data holding circuit 6.

The operation of the multiple data read instruction will be described with reference to FIGS. For example, the multiple data read instruction ldq (r4), r0 is an instruction to read four consecutive data with the register r4 as the start address, and the four read data are stored in the latches L0 to L3.
R0 is specified as the write destination register, and the latches L0 to L3 are associated with the registers r0 to r3, respectively. When the instruction ldq is read from the memory device 40, it is decoded by the decoder 1, and the decoded results 13, 14, 26 and the multiple data read signal 27 are output. When the multiple data read signal 27 is given, the memory control circuit 4 outputs the address 15 output from the arithmetic unit 3 to the memory device 40 as the address 16 in the MEM stage, and reads the multiple data from the memory device 40. Request. The read enable bits E0 to E3 of the data read control circuit 31 are all set to "1" when the multiple data read signal 27 is given.

In the case of the multiple data read instruction ldq, the WB stage is divided into a plurality of stages. For example, to read four data, four stages WB0, WB1,
The data is divided into WB2 and WB3, and the data is read to each stage one by one.
1, L2, and L3.

The number of registers in the register file 2 is represented by r
Assuming that there are eight registers from 0 to r7, the ldq instruction specifies the write destination registers as r0 to r3 or r4 to r4.
7 types. Therefore, the register information circuit 33 of the data read control circuit 31 holds 1-bit information as information of the write destination register. That is, "0" is stored when r0 to r3 are specified as the write destination registers, and "1" is stored when r4 to r7 are specified. This designation is included in the decoding result 26. In the case of the instructions ldq (r4), r0, “0” is stored in the register information circuit 33.

In the execution of the instruction following the multiple data read instruction ldq, the read enable bits E0 to E3
The value held in the register information circuit 33 is used. The decode result 26 of the instruction subsequent to the multiple data read instruction ldq includes the number of the read register. The control circuit 34 reads the read register number, the value held in the register information circuit 33, Using the enable bits E0 to E3, it is determined whether the instruction to be executed uses the data of the latches L0 to L3. The value held in the register information circuit 33 is “0”
In this case, if the read registers are r0 to r3 and the values of the corresponding read enable bits E0 to E3 are "1", the data of the latches L0 to L3 corresponding to the read registers is used.

When using the data of the latches L0 to L3, the control circuit 34 outputs a read control signal 32 to the selection circuit 30 to read the latches L0 to L3 corresponding to the read register. At the same time, control signals 35 and 36 are applied to selection circuits 22 and 2
3 and instructs the arithmetic unit 3 to output the read data of the latches L0 to L3. After the latches L0-L3 are read, the corresponding read enable bit E0
~ E3 is reset to "0". When the value of the read enable bits E0 to E3 is “0”, the corresponding latch L
0 to L3 are not read. That is, each of the latches L0 to L3 is read only once after the multiple data read command, and thereafter read from the register file 2.

An example in which a multiple data read instruction is used will be specifically described with reference to the timing chart of FIG. The first instruction is a four data read instruction ldq. Value A of register r0
, The four consecutive 32-bit data D0, D1, D2, D3 are read. The four read data are stored in the write stages WB0, WB1, WB2, and WB3, one data each, and are stored in the four latches L0, L1, L2, and L3 of the read data holding circuit 6, respectively. Since the write destination of the ldq instruction is the register r0, the four latches L0 to L3 are stored in the registers r0 to r3, respectively.
Is associated with. 4 read from the memory device 40
The two data are only stored in the latches L0 to L3, but are not stored in the registers r0 to r3.

Therefore, the WB stage of the next instruction and ldq
Even if the instruction WB0 to WB3 stages overlap, the next instruction can write data to the register file 2 without waiting. The third, fourth, fifth, and sixth instructions add are addition instructions, and r0, r1, r2, and r3 are specified in the read registers used for the operations, respectively, and the corresponding read enable bits E0 to E3 are set to "0". Since it is "1", the latches L0 to L3 are read instead of the registers r0 to r3, added to the value of the register r4, and the result is stored in the register r4. Therefore, the third, fourth, fifth and fifth
By the sixth instruction add, four data D0, D1, D2, D
3 is added, and the total value is written to the register r4.

After the latches L0 to L3 are read, the read enable bits E0 to E3 are reset to "0", respectively, and after the ldq instruction, the second and subsequent registers r0 to r3
In this case, the values of the registers r0 to r3 are read instead of the latches L0 to L3. The read register of the seventh instruction add is r0. At this time, since the read enable bit E0 is “0”, the value of the register r0 is read, and the value “16” is added to the result.
Stored in r0. At this time, the value read from the register r0 is the value A stored before the first instruction ldq.

As described above, in the present embodiment, even if a plurality of data are read from the memory device 40 by a plurality of data read commands, they are not stored in the register file 2, so that the completion of reading from the memory device 40 is not waited for. The next instruction can be executed. Furthermore, even if the WB stage of the multiple data read instruction and the WB stage of the subsequent instructions overlap, both WB stages can be executed simultaneously without increasing the number of write ports of the register file 2, and the circuit of the register file 2 can be executed. The processing performance can be improved without increasing. Further, since the data of the register file 2 cannot be rewritten by the multiple data read command, it is not necessary to save the data of the register file 2 to the memory device 40 in advance, and it is possible to prevent the processing performance from lowering. This is particularly effective in an information processing apparatus in which the number of registers in the register file 2 is small.

Further, an instruction to read data from a normal register can be used to read data stored in the read data holding circuit, and it is not necessary to prepare a new instruction, and the bit length of the instruction can be shortened. . Thus, the size of the program can be reduced and the capacity of the memory for storing the program can be reduced, which is effective for cost reduction.

In the example shown in FIG. 3, the memory device 40
One data is transferred by one transfer from
A plurality of data may be transferred by one transfer.

Referring to the timing chart of FIG. 4 and FIG. 1, an example of the operation when four data are transferred by one transfer will be described.

In FIG. 4, the first instruction ldq is a register r
The four data continuously stored in the memory device 40 are read at once with the value of 0 as the start address, and the four latches L0 of the read data holding circuit 6 are read to the WB stage.
To L3. Since r0 is specified as the write destination register, the latches L0 to L3 are associated with the registers r0 to r3. In the third instruction add, since r0 and r2 are specified as read registers, the corresponding latch L
The values of 0 and L2 are read out and added, and the result is stored in the register r4. Similarly, in the fourth instruction add, the data of the latches L1 and L3 corresponding to the read registers r1 and r3 are read, added by the arithmetic unit 3, and stored in the register r5 of the register file 2. In the fifth instruction add, r0 is specified as the read register. This is the second specification of the register r0 after the multiple data read instruction ldq, and the corresponding read enable bit E0 is “0”. , Latch L for this instruction
The value A of the register r0 of the register file 2 is read instead of 0.

By reading a plurality of data at a time, a plurality of data can be used immediately.
It is effective in improving processing performance.

In the examples shown in FIGS. 3 and 4, four data are stored in the four latches L0 to L3 of the read data holding circuit 6 by the ldq instruction, but the four latches L0 to L3 are divided and divided. Data may be separately stored in the parts.
The latches L0 to L3 for storing data are specified by the lower 2 bits of the number of the write destination register and the number of data to be stored. For example, when the write destination register is r6 and two data are stored, the data is stored in latches L2 and L3. The decode result 26 is further given to the read enable bits E0 to E3 of the data read control circuit 31 shown in FIG. 2 and, similarly to the designation of the latches L0 to L3,
The read enable bit E which is set to “1” according to the lower two bits of the write destination register number indicated by the decode result 26 and the number of data to be stored.
0 to E3 are specified.

Referring to the timing chart shown in FIG. 5, an instruction ldd for reading two data is used twice to first latch L
An example of an operation when data is stored in 0 and L1 and then data is stored in latches L2 and L3 will be described. In the examples shown in FIGS. 3 and 4, the register information circuit 33 of the data read control circuit 31 has 1-bit information indicating whether the latches L0 to L3 correspond to the registers r0 to r3 or the registers r4 to r7. In the example shown in FIG. 5, 1-bit register information W0 to W3 indicating register correspondence is held for each of the latches L0 to L3.

In FIG. 5, the first instruction ldd is a register r
Two consecutive data D0 and D1 are simultaneously read from the address A in the memory device 40 indicated by "0" and stored in the latches L0 and L1 in the WB stage. Since the number of data is two and r0 is indicated as the write destination register, the register information W corresponding to the latches L0 and L1
“0” is set to both 0 and W1, and the latches L0 and
"1" is set to the read enable bits E0 and E1 corresponding to L1. Similarly, the second instruction ldd has a register r
2, two data F0 and F1 are read from address B in the memory device and stored in latches L2 and L3.
When the number of data is 2 and it is a write destination register
Since r6 is shown, register information W2 and W3 corresponding to latches L2 and L3 and read enable bit E
"1" is set to 2, E3. Since the fourth instruction add specifies r0 and r6 as the read registers, the latches L0 and L2 store the registers r0 and r2 according to the register information W0 and W2.
6, the data D0 and F0 are read from the latches L0 and L2, respectively, added in the arithmetic unit 3, and the result is stored in the register r4. Similarly, since the fifth instruction add specifies r1 and r7 as the read registers, the data is read from the corresponding latches L1 and L3.
D1 and F1 are read, respectively, added in the arithmetic unit 3, and the result is stored in the register r5. Register r
The data of 4 and r5 are stored in the address of the value C and the address of the value (C + 4) of the register r1 by a sixth instruction st and a seventh instruction st, which are write instructions to the memory device 40, respectively.

As described above, since the data related to the two different addresses A and B can be simultaneously held in the latch of the read data holding circuit 6, the operation between the data having different addresses can be performed efficiently. Note that the register information circuit 33 is configured to have 1-bit information for each of the latches L0 to L3.
The number of bits may be increased so that the correspondence between the latches L0 to L3 and the register can be set more flexibly. Conversely, similar to the examples shown in FIGS. 3 and 4, the latches L0 to L3 may have common 1-bit information.

In this embodiment, the latches L0 to L
Although the registers corresponding to 3 are r0 to r3 or r4 to r7, the corresponding registers may be fixed to, for example, only r0 to r3. In this case, the register information circuit 33 of the data read control circuit 31 is unnecessary.

In this embodiment, the latches L0 to L
3 can be read only once after each of the multiple data read commands. However, the latch L can be read by a multiple data read command or another command in advance.
The number of times data 0 to L3 can be read may be specified.

In this embodiment, the selection circuit is provided for each of the two inputs of the arithmetic unit 3.
Only one of them may be provided to reduce the number of circuits.

Next, a second embodiment of the present invention will be described. In the following description, members corresponding to the members described with reference to FIGS. 1 and 2 are denoted by the same reference numerals, and detailed description is omitted.

In the second embodiment, when the register corresponding to the latches L0 to L3 is read from the execution of the multiple data read instruction to the execution of the multiple data read release instruction, data is always read from the corresponding latch L0 to L3. It is.

FIG. 6 is a block diagram showing the configuration of the data read control circuit 31 according to the second embodiment. Reference numeral 28 denotes a multiple data read release signal, and the instruction decoded by the decoder 1 is a multiple data read release instruction. This is a signal output from the decoder 1 at times. The first shown in FIG.
The difference from the data read control circuit 31 in the embodiment lies in that the read enable bit is only one bit E in common for the latches L0 to L3 and in the way of resetting the read enable bit E. In the example shown in FIG.
The control circuit 34 outputs the read control signal 32 and latches it.
When the data of L0 to L3 is read, the read latch L0
The read enable bits E0 to E3 corresponding to .about.L3 are reset to "0". In the second embodiment, when the multiple data read release signal 28 is given, the read enable bit E is reset to "0". Reset.
That is, the read enable bit E is set to “1” when the multiple data read instruction is executed, and is reset to “0” when the multiple data read release instruction is executed. During this time, the latches L0 to L3 Data can be read.

The operation of the second embodiment will be described with reference to the timing chart shown in FIG. In FIG. 7, the first instruction ldd
Simultaneously reads two consecutive data D0 and D1 from the address A in the memory device 40 indicated by the register r0 and stores them in the latches L0 and L1 in the WB stage. ME
At the M stage, the multiple data read signal 27 is output, and the read enable bit E is set to “1”. The third instruction add includes r0 and r as read registers.
1 and the read enable bit E is “1”, so that the data is read from the corresponding latch L0, L1.
D0 and D1 are read, respectively, added in the arithmetic unit 3, and the result is stored in the register r4. Similarly the fourth
The instruction sub specifies r0 and r1 as read registers, and since the read enable bit E is “1”, data D0 and D1 are read from the corresponding latches L0 and L1, respectively, and are subtracted by the arithmetic unit 3. The result is stored in the register r5. The fifth instruction resetld is a multiple data read release instruction. The multiple data read release signal 28 is output to the EX stage, and the read enable bit E is reset to “0”. The sixth instruction add
Although r0 is designated as the read register, since the read enable bit E is "0", the data of the register r0 of the register file 2 is read instead of the corresponding latch L0, and the data is added by the arithmetic unit 3. The result is stored in the register r0. The value of the register r0 read by the sixth instruction add is a multiple data read instruction ldd.
Is the value A held before the execution of.

As described above, the read enable bit E
Is reset by the multiple data read release signal 28 output by decoding the multiple data read release instruction, so that the data read by the multiple data read instruction can be used many times, and the processing performance can be improved. Great effect.

In the second embodiment, the read enable bit is set to one bit, but the four latches L0 to L3
May be set to four bits E0 to E3. The specification of the read enable bits E0 to E3 is performed by indicating the write destination register and the number of data to be read by the multiple data read instruction and the multiple data read release instruction.

Incidentally, depending on the configuration of the memory device 40, the time required for reading data may vary depending on the state at the time of execution. For example, when the memory device 40 has a two-layer structure of a cache memory and a main storage device, when data to be read is stored in the cache memory, the read time is short, but the data is not stored in the cache memory. In such a case, it takes a long time to read from the main storage device.

Therefore, the information processing apparatus according to the third embodiment of the present invention can cope with a case where the time required for reading data is long or a case where it is not known in advance.

FIG. 8 is a block diagram showing the configuration of an information processing apparatus according to the third embodiment of the present invention. In FIG. 8, the same elements as those described in the information processing apparatus shown in FIG. The detailed description is omitted by attaching the reference numerals, and different points will be mainly described.

In FIG. 8, reference numeral 50 denotes four valid flags V
This is an effective register that holds 0, V1, V2, and V3. 4
One of the valid flags V0 to V3 indicates whether data is stored in each of the latches L0 to L3, corresponding to the latches L0 to L3, respectively. When the values of the valid flags V0 to V3 are “1”, Data is stored in corresponding latches L0 to L3.

The data read control circuit 31 has the same configuration as that shown in FIG. 2, but the control circuit 34 is further provided with valid flags V0 to V3.

When a multiple data read instruction, for example, an instruction requesting the reading of four data is decoded by the decoder 1, all the four valid flags V0 to V3 are reset to "0" by the multiple data read signal 27.
As in the first embodiment, the memory control circuit 4 requests the memory device 40 to read a plurality of data. When data is read from the memory device 40, the latch L0
LL3. At the same time when data is stored in each of the four latches L0 to L3, "1" is set in the corresponding valid flags V0 to V3. Data read by the multiple data read command is not stored in the register file 2 as in the first embodiment. Latch L
0 to L3 are associated with the write destination register number of the multiple data read instruction, and when an attempt is made to read the register associated with the subsequent instruction, the corresponding latch L0 is used instead of the register file 2. ~ L3.

At this time, the control circuit 34 of the data read control circuit 31 determines the number of the read register specified by the decode result 26 given from the decoder 1 and
When the information held in the register information circuit 33 and the read enable bits E0 to E3 indicate that the register to be read corresponds to the latches L0 to L3, the values of the corresponding valid flags V0 to V3 are checked. When the value of the valid flag is “1”, the control circuit 34 outputs the read control signal 32 to the selection circuit 30 and outputs the corresponding latch V0 to V
3 and simultaneously outputs selection signals 35 and 36 to the selection circuits 22 and 23 so that the data output from the selection circuit 30 is selected and supplied to the arithmetic unit 3. When the value of the valid flag is “0”, the execution stop signal 5
1 is output to the execution control circuit 5 or the like to stop the execution of the instruction. Thereafter, data is read from the memory device 40 and stored in the corresponding latches L0 to L3. When the corresponding valid flags V0 to V3 are set to "1", the execution stop signal 51 is released, and the execution of the instruction is executed. To resume.

As described above, when data is read by a plurality of data read commands and the subsequent command uses the data, even if the time required for reading is changed, the instruction is executed until the data is read. By waiting, correct processing can be performed. Further, even if reading of all data is not completed, processing can be performed using data that has already been read.

Referring to the timing chart shown in FIG. 9, an example using a multiple data read instruction will be specifically described. First
The instruction is a multiple data read instruction ldq. Register r0
4 data D with the value of
Read 0, D1, D2, D3. The four read data are stored in four latches L0 and L of the read data holding circuit 6.
1, L2, and L3, respectively. The ldq instruction has four write stages, WB0, WB1, WB2, and WB3. One data is latched in each stage.
Stored in L0 to L3. Although the write destination of the ldq instruction is the register r0, the four data read from the memory device 40 are only stored in the read data holding circuit 6 as in the first embodiment. 2 is not stored. When the multiple data read command is executed, a multiple data read signal 27 is output,
All the valid flags V0 to V3 are reset to "0".

FIG. 9 is different from the operation of the timing chart shown in FIG.
In this case, an extra clock cycle is required to read each data from. The four data D0 to D3 read from the memory device 40 are stored in the latches L0 to L3 in cycles C6, C8, C10, and C12, respectively. The read register of the third instruction add is r0, and the data D0 of the latch L0 corresponding to the register r0 is read and added. However, in the cycle C5, the data D0 is still present.
Are not stored in the latch L0. At this time, the valid flag V0 of the valid register 50 of the read data holding circuit 6
To V3 remain “0”, and the control circuit 34
Outputs the execution stop signal 51 because the valid flag V0 of the latch L0 corresponding to the read register r0 specified by the decoding result 26 of the third instruction add is “0”, and outputs the execution stage of the third instruction add. (EX stage) waits for processing. Data D0 is latched in cycle C6
When stored in L0, the valid flag V0 is set to "1", the control circuit 34 releases the execution stop signal 51, and executes the EX stage of the third instruction add.

At this time, the data D0 of the latch L0 is selected by the selection circuit 30, and its output is selected by the selection circuit 23 and applied to the input 11 of the arithmetic unit 3. Arithmetic unit 3 is D
0 is added to the data of the register r4. Similarly, the fourth instruction add is a latch L corresponding to the read register r1.
1 is added to the data D1 of the register r4.
In cycle C7, data D1 has not been stored yet. Since the valid flag V1 corresponding to the latch L1 is “0”, the control circuit 34 outputs the execution stop signal 51 and
Causes the execution of the EX stage of the instruction add to wait. Cycle C8
When the data D1 is stored in the latch L1, the valid flag V1 is set to "1", the control circuit 34 releases the execution stop signal 51, and performs the processing of the EX stage of the fourth instruction add.

As described above, even if the data read by the multiple data read command is delayed, by outputting the execution stop signal 51 using the valid flags V0 to V3, the instruction using the data to be read by the multiple data read command is issued. It is possible to make the user wait, and it is possible to prevent a malfunction using erroneous data.

An instruction that does not use data to be read by the multiple data read instruction can be executed even if no data is stored in the latches L0 to L3.

FIG. 10 is a block diagram showing the configuration of an information processing apparatus according to a fourth embodiment of the present invention. In FIG. 10, the same elements as those described in the information processing apparatus shown in FIG. The detailed description is omitted by attaching the reference numerals, and different points will be mainly described. The information processing apparatus according to the fourth embodiment can efficiently perform processing when the bit length of each data read by the multiple data read instruction is shorter than the bit length of the register of the register file 2.

In FIG. 10, reference numeral 52 denotes a memory device 40
Is a data extracting circuit that separates and extracts each data according to the data size from a plurality of data connected and read on the data bus 17 and outputs the separated data to the corresponding latches L0 to L3.

The bit length of the register is 32 bits,
A case where four 8-bit data are read by a multiple data read instruction, for example, a case where an instruction called ldqb (r4), r0 is executed will be described. This instruction is a sequence of four consecutive 8 bits with the value of register r4, for example, A as the starting address.
This is an instruction for reading the bit data D0, D1, D2, and D3. Although r0 is specified as the write destination register, the read data is, as in the first embodiment,
The data is stored in the latches L0 to L3 of the read data holding circuit 6, and is not stored in the register file 2. Latch L0
To L3 are respectively associated with r0 to r3 designated as write destination registers. Assuming that the bit length of data read from the memory device 40 at one time is 32 bits, the four 8-bit data D0 to D3 read by the multiple data read command are read from the memory device 40 at one time as concatenated 32-bit data. .

That is, assuming that the read 32-bit data is RD [31: 0], RD [7: 0], RD [15: 8], RD [23: 1]
6] and RD [31:24] are D0, D1, D2 and D3, respectively. The data extracting circuit 52 converts the read 32-bit data RD [31: 0] into four 8-bit data RD [7:
0], RD [15: 8], RD [23:16], RD [31:24] are taken out and output to the latches L0, L1, L2, L3. Latch L
Each of 0 to L3 is a 32-bit latch. When storing 8-bit data, the remaining upper 24 bits are stored with 0 (zero) extension or sign extension. The data retrieval circuit 52 determines the type of data, that is,
The data is output with 0 extension or sign extension depending on whether it is unsigned data or signed data. This data type can be specified by a multiple data read command.

When four 16-bit data D0 to D3 are read by a multiple data read command, they are read from the memory device 40 in two separate steps. First data D
0 and D1 are read at once. At this time, RD [15: 0] and R
D [31:16] are D0 and D1, respectively, and the data extracting circuit 52 extracts and latches the respective data D0 and D1.
Output to L0 and L1. In the second read, data D2
And D3 are read at once. At this time, RD [15: 0] and RD
[31:16] are D2 and D3, respectively, and the data retrieval circuit 52 retrieves and latches the respective data D2 and D3.
Output to L2 and L3. The data extraction circuit 52 extends the remaining upper 16 bits by 0 or sign extension according to the type of data and outputs the result to the latches L0 to L3.

As described above, the data extracting circuit 52
A necessary portion is extracted from an appropriate position in the data read from the memory device 40 according to the size of the data, and is output to the latches L0 to L3.

In the fourth embodiment, 0 extension or sign extension is performed by the latch L0 from the data extracting circuit 52.
To L3, but the information of the data type is stored, and the latch L0 is output by a subsequent instruction.
The selection circuit 30 may perform the operation when reading data according to L3.

The operation of reading the data of the latches L0 to L3 according to the instruction after the multiple data read instruction and using the data for the operation is the same as the operation in the first embodiment.

As described above, when a plurality of data shorter than the bit length of the register are read at a time, each data is separated and stored in the latches L0 to L3, so that there is no need to separate the data by a subsequent instruction. Thus, it is possible to improve the processing capacity and reduce the amount of programs.

In the description of the fourth embodiment, the data read from the memory device 40 is 32 bits. However, the same operation as described above is performed with other bit lengths such as 64 bits or 128 bits.

[0080]

As described above, the information processing apparatus according to the present invention includes the read data holding means for holding a plurality of data and the data read means, so that the data can be read from the memory device by executing the plurality of data read instructions. Read data stored in the data holding means,
The data is not stored in the register file, and the corresponding data can be read out from the data holding means by designating the register by a later instruction, and can be used by reading the data. The processing of this instruction can be performed, the processing time can be reduced, and the processing performance can be improved, which is extremely useful.

Further, since a plurality of data read by the plurality of data read instructions are not written in the register file, there is no need to temporarily save the data in the register file to the memory device, and it is possible to prevent a reduction in processing performance. Very useful.

Further, by providing a data valid flag indicating whether or not reading of a plurality of data from the memory device by the plurality of data read command is completed, an incorrect value is read from the read data holding means before the data reading is completed. Can be prevented from being read out, which is extremely useful.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an information processing apparatus for explaining a first embodiment of the present invention;

FIG. 2 is a block diagram illustrating a configuration of a read data control circuit according to the first embodiment.

FIG. 3 is an operation timing chart of the information processing apparatus according to the first embodiment;

FIG. 4 is a timing chart showing another operation of the information processing apparatus according to the first embodiment;

FIG. 5 is a timing chart showing another operation of the information processing apparatus according to the first embodiment;

FIG. 6 is a block diagram showing a configuration of a read control circuit in an information processing apparatus for explaining a second embodiment of the present invention;

FIG. 7 is an operation timing chart of the information processing apparatus according to the second embodiment;

FIG. 8 is a block diagram showing a configuration of an information processing apparatus for explaining a third embodiment of the present invention.

FIG. 9 is an operation timing chart of the information processing apparatus according to the third embodiment;

FIG. 10 is a block diagram showing a configuration of an information processing apparatus for explaining a fourth embodiment of the present invention;

FIG. 11 is a block diagram showing a configuration of a conventional information processing apparatus.

FIG. 12 is a diagram showing a pipeline operation of a conventional data processing device.

FIG. 13 is a diagram showing a pipeline operation of a conventional data processing device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Decoder 2 Register file 3 Arithmetic unit 4 Memory control unit 5 Execution control circuit 6 Read data holding circuit 10, 11, 12, 17, 18, 24 Data 13, 14, 26 Decoding result 15, 16 Address 21 Immediate value 22, 23, 30 selection circuit 27 multiple data read signal 28 multiple data read release signal 31 data read control circuit 32 read control signal 33 register information circuit 34 control circuit 35, 36 selection signal 40 memory device 50 valid register 51 execution stop signal 52 data extraction circuit L0 , L1, L2, L3 Latch E0, E1, E2, E3 Read enable bit

Claims (10)

[Claims] 1. A memory device for storing a plurality of data, a register file having a plurality of registers for storing data, an operation means for performing an operation using given data, an instruction for decoding an instruction, When the decoded instruction is a multiple data read instruction, an instruction decoding unit that outputs a multiple data read signal, and in accordance with a decryption result output by the instruction decryption unit, performs an operation by the arithmetic unit and a data of the register file. Command execution control means for controlling read and write; memory control means for reading a plurality of data from the memory device when the plurality of data read signals are provided; and read from the memory device according to the plurality of data read signals. Data holding means for holding a plurality of pieces of data, and holding in the data holding means Data read means for reading data corresponding to a read register indicated by the decoding result and outputting a data selection signal, among the read data, data read from the register file according to the data selection signal, or the data An information processing apparatus, comprising: data selection means for selecting data read from the holding means and outputting the data to the arithmetic means. 2. The data read means, when given the plurality of data read signals, holds information of a write destination register indicated by the decoding result, and holds a read register number indicated by a decoding result of a subsequent instruction and a holding value. When data corresponding to a read register is included in the data holding means according to the information of the write destination register, the corresponding data is read from the data holding means and a data selection signal is output at the same time. The information processing apparatus according to claim 1. 3. The information according to claim 2, wherein said data reading means holds information of a write destination register indicated by said decryption result for each data stored in said data holding means. Processing equipment. 4. The data reading means reads the respective data stored in the data holding means a predetermined number of times after receiving the plurality of data reading signals,
2. A data selection signal for instructing the arithmetic means to supply the read data is output.
An information processing apparatus according to claim 1. 5. A memory device for storing a plurality of data, a register file having a plurality of registers for storing data, an operation means for performing an operation using given data, an instruction for decoding an instruction, Command decoding means for outputting a multiple data read signal when the decoded command is a multiple data read command and outputting a multiple data read release signal when the decoded command is a multiple data read release command; Command execution control means for controlling the operation by the operation means and the reading and writing of data to and from the register file in accordance with the decoding result output by the means; and Memory control means for reading data; and the memory according to the plurality of data read signals. A data holding unit for holding a plurality of data read from the device; and, from receiving the plurality of data read signals to receiving the plurality of data read release signals, among the data held by the data holding unit, Data reading means for reading data corresponding to the read register indicated by the result and outputting a data selection signal; data read from the register file or data read from the data holding means according to the data selection signal And a data selecting means for selecting and outputting to the arithmetic means. 6. A memory device for storing a plurality of data, a register file having a plurality of registers for storing data, an operation means for performing an operation using given data, an instruction for decoding an instruction, a decoding result, When the decoded instruction is a multiple data read instruction, an instruction decoding unit that outputs a multiple data read signal, and in accordance with a decryption result output by the instruction decryption unit, performs an operation by the arithmetic unit and a data of the register file. Command execution control means for controlling reading and writing; memory control means for reading a plurality of data from the memory device when the plurality of data read signals are provided; and a plurality of data read from the memory device according to the plurality of data read signals. Data holding means for holding the data of A data validity flag indicating that the data has been stored, and a data readout unit that reads out data corresponding to a readout register indicated by the decoding result from among the data held in the data holding unit, and outputs a data selection signal, Data reading means for selecting data read from the register file or data read from the data holding means according to the data selection signal, and outputting the selected data to the arithmetic means. When reading data from the data holding means, if the data valid flag indicates that data is not stored in the data holding means, an execution stop signal is output to stop processing of the instruction. Information processing device. 7. The data valid flag comprises a plurality of bits corresponding to each of a plurality of data stored in the data holding means, and indicates that each data is stored. 6. The information processing apparatus according to 6. 8. A memory device for storing a plurality of data, a register file having a plurality of registers for storing data, an operation means for performing an operation using given data, an instruction for decoding an instruction, When the decoded instruction is a multiple data read instruction, an instruction decoding unit that outputs a multiple data read signal, and in accordance with a decryption result output by the instruction decryption unit, performs an operation by the arithmetic unit and a data of the register file. Command execution control means for controlling reading and writing; memory control means for reading a plurality of data from the memory device when the plurality of data read signals are provided; and outputting the plurality of data to a data bus; A data extracting means for extracting data from a specific position on the bus and outputting the data; A data holding unit for holding a plurality of data output by the data extracting unit in accordance with a multiple data read signal; and, of data held in the data holding unit, data corresponding to a read register indicated by the decoding result. Data reading means for reading and outputting a data selection signal; data selection for selecting data read from the register file or data read from the data holding means and outputting to the arithmetic means according to the data selection signal An information processing apparatus comprising: means. 9. The data fetching means sign-extends or zero-extends the fetched data according to whether the data fetched from the data bus is signed data or unsigned data, and sends the data to the data holding means. The information processing apparatus according to claim 8, wherein the information is output. 10. The data holding means according to claim 1, wherein said data provided by said data extracting means is signed data.
9. The information processing apparatus according to claim 8, wherein the held data is sign-extended or zero-extended according to the unsigned data and output to the data selection unit.