JPH1131970A - Digital signal processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To compensate the phase delay value up to the high band frequency by using a phase compensation filter to compensate the delayed phase of a thinning filter. SOLUTION: A 1st LPF (low pass filter) 2 eliminates the alias noises out of analog signals which are inputted via an analog input terminal 1. An A/D converter 3 is prepared at the next stage of the LPF 2 to digitize the analog output signals of the LPF 2 at a 1st sampling time interval. Then a thinning filter 4 is prepared at the next stage of the converter 3 to thin the data at another sampling time interval. Furthermore, an FIL (phase compensation filter) means 5 has the characteristic to advance its phase at the low frequency using the output signal of the filter 4 as its input. An FIL (impedance filter) 6 is prepared at the next stage of the FIL 5 to perform the digital signal processing. In such a constitution, the FIL 6 can include the phases covering up to the high frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal processing technique, and more particularly, to a technique for compensating a phase delay to a high frequency.

[0002]

2. Description of the Related Art Conventional digital signal processing techniques include:
A / D (analog / digital) conversion of the analog signal on the subscriber line is performed by oversampling, and further, through a thinning filter, the sampling rate is reduced and digital signal processing is performed. D by sampling
/ A (digital / analog) conversion,
A technique for performing signal processing having an arbitrary filter characteristic is known.

An example of a document describing such a digital signal processing technique is Japanese Patent Publication No. 4-774.
No. 93, Japanese Patent Publication No. 57-24137, and Japanese Patent Publication No. 57-26941.

[0004]

The transfer function H _DEC of the thinning filter is as shown in the following equation (1).

H _DEC = K {sin (m · π · f · Ts) / sin (π · f · Ts)} ⁿ · exp (−jn (m−1) π · f · Ts)... , K, m, and n are arbitrary numbers that determine the characteristics of the thinning filter, Ts is the sampling time in oversampling, and f is the frequency of the signal.

What needs attention in Equation 1 is the term of exp (). By this term, the phase characteristic of the thinning filter is such that the phase is delayed by a linear phase with respect to the frequency. This exp () term also exists for interpolation filters,
The phase is also delayed there. Since the thinning filter and the interpolation filter have the characteristic that the phase delay increases as the frequency increases, it is difficult to realize an impedance filter that satisfies the phase characteristic even with a high frequency component using a digital signal processing circuit. Is difficult.

For this reason, the impedance filter is
The filter is mainly limited to the characteristic of passing low-frequency components, and is limited to the above-described thinning filter and a filter having a frequency characteristic such that the phase delay due to the interpolation filter can be ignored.
For high frequency components, refer to the Advanced Micro Devices data sheet, Telecommunication Products DataBoo.
k 1992/1993 ”, the method of compensating for the characteristics of the impedance filter by performing feedback in the analog portion that does not pass through the decimation filter and interpolation filter as shown in section 2-11 of Figure 2-11. However, this causes an increase in the circuit scale in the analog section.

Another object of the present invention is to provide a technique for compensating a phase delay up to a high frequency.

Another object of the present invention is to provide a technique for increasing a frequency range applicable to an impedance filter.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

A / D conversion means (3) for A / D converting an analog signal at every first sampling time interval.
A decimating filter (4) for sampling the output signal of the A / D converter at a second sampling time interval and decimating the data; and disposed at a stage subsequent to the decimating filter to have an arbitrary impedance characteristic. Digital filter (6), an interpolation filter (9) for interpolating the output signal of the digital filter at a third sampling time interval, and a D / D
When a digital signal processing circuit including a D / A conversion circuit (10) for A-conversion is provided, a phase compensation filter for compensating for the delay phase of the thinning filter is provided, and the phase delay is reduced to a high frequency range. To compensate.

As a specific mode, as a means for compensating for the phase delay caused by the interpolation filter, a filter having a leading phase characteristic as shown by the following transfer function H of the following equation 2 is added to the impedance filter.

H = 2−Z ⁻¹ (2) where Z ⁻¹ is exp (−j2 · π · f · Ts).

Alternatively, it can be achieved by adding a frequency conversion circuit having a built-in filter having a characteristic as shown by the following transfer function H of Formula 3.

H = 2 + Z ^{-1 (} 3) When the frequency f is low,
It has the characteristic that the phase advances. Further, the transfer function shown in Expression 3 has a characteristic that the phase advances when the frequency is close to the sampling frequency fs / 2 (= 2 / Ts), so that the phase can be advanced by frequency conversion. Therefore, the phase delay of the thinning filter and the interpolation filter can be compensated by the above characteristics. As a result, the frequency range achievable by the impedance filter characteristics to be realized by digital signal processing can be extended to high frequencies. Also,
Due to this frequency expansion, the signal that has been fed back by the analog section can be converted into a digital signal, which simplifies the circuit of the analog section.

[0017]

FIG. 1 shows a digital signal processing circuit according to the present invention.

The digital signal processing circuit 20 is connected to a subscriber line via an interface means 30.
The digital signal processing circuit 20 is provided with input terminals 1 and 2 for analog signals. A first LPF (low-pass filter) 2 for removing alias noise from an analog signal input via an analog input terminal 1 is provided, and a subsequent stage outputs an analog output signal of the first LPF 2 to a second LPF. An A / D (analog / digital) converter 3 for digitizing at one sampling time interval Ts1 is provided. In the subsequent stage, a thinning filter 4 for thinning the output data of the A / D converter 3 at the sampling time interval Ts2 is provided, and further, at a low frequency to which the output signal of the thinning filter 4 is input. A phase compensation filter means (FIL) 5 having a characteristic of leading the phase is provided, and an impedance filter (FIL) 6 to be realized by digital signal processing is provided at a subsequent stage.
Is provided. Further, there is provided an adder 7 for adding a signal 8 transmitted from a device provided above the digital signal processing device and an output signal from the impedance filter 6, and at a subsequent stage, an output signal of the adder 7 is provided. The sampling time interval Ts2 and the time interval T
An interpolation filter for data interpolation is provided at s3. In the subsequent stage, a D / A converter 10 for converting the digital signal output from the interpolation filter 9 into an analog signal
And a second LPF 11 for extracting a low frequency component from the output signal of the D / A converter 10 is provided. The output signal of the second LPF 11 is supplied to an output terminal 12.
Is output externally via

The interface means 30 has subscriber line side terminals 31 and 32, and incorporates a voltage control voltage source 35 and a current control current source 36. The voltage control voltage source 35 outputs a signal obtained by multiplying the voltage between the subscriber line terminals 31 and 32 by an arbitrary coefficient (A) to the output terminal 33 of the interface means 30 and interfaces with the input terminal 1 of the digital signal processing circuit 20. . The current control current source 36 outputs a current obtained by multiplying the current input to the input terminal 34 by an arbitrary coefficient (F) to the subscriber line side terminals 31 and 32. The resistor R _RX converts the output voltage signal of the digital signal processing circuit 20 into a current to the input terminal 34 of the interface means 30.

First, the fact that the impedance between the subscriber line side terminals 31 and 32 can be set from the subscriber line side by the impedance filter 6 of the digital signal processing circuit 20 will be described.

Here, in order to simplify the explanation, the transfer characteristics of the first LPF 2, A / D converter 3, D / A converter 10 and second LPF 11 in the digital signal processing circuit 20 are simplified to 1. Become The transfer function of the thinning filter 4 is H _DEC , the transfer function of the phase compensation filter 5 is H _FIL1 , the transfer function of the impedance filter 6 is H _FIL2 , and the transfer function of the interpolation filter 9 is H _INT . _Assuming that the voltage between the subscriber line side terminals is V31, ₃₂ , the first LPF 2, the A / D converter 3, the thinning filter 4, the D / A converter 10, the second The transfer function of the LPF 11 to the current output I _OUT of the current control current source 36 is as follows:
It becomes as shown in.

[0022] _{I OUT = (V 31,32 · A} · H DEC · H FIL1 · H FIL2 · H INT) / R RX · F ... number 4 Therefore, the impedance Z ₃₁ between the subscriber line terminals 31 and _{32, Since 32} is expressed by the following equation 5, substituting equation 4 results in equation 6.

Z _31,32 = V _31,32 / I _OUT = R _RX / (AF) / (H _DEC · H _FIL1 · H _FIL2 · H _INT ) where H _DEC and H _INT are , The transfer characteristic is temporarily set as H _DEC = H _INT =
1, and the characteristics of the phase compensation filter 5 are also set to H _FIL1 = 1. Further, the characteristic of the impedance filter 6 will be described as an arbitrary filter characteristic having the following equation (6). It should be noted that, for ease of explanation, it is expressed not by Z but by jω.

H _FIL2 = jωC _FIL2 · R _FIL2 / (1 + jωC _FIL2 · R _FIL2 ) _Equation 6 From the above assumption, _Equation 5 can be transformed into the following _Equation 7.

Z _31,32 = R _RX / (A · F) / (1 + 1 / jωC _FIL2 · R _FIL2 ) _Equation 7 Further, R _31,32 = R _RX / (A · F), C _31,32 = C _FIL2・ R
_{If FIL2} / R _RX · (A · F), _Equation 7 can be transformed into the following Equation 8, and the impedance between the subscriber line terminals 31 and 32 can be set.

Z _31,32 = R _31,32 + 1 / jωC _31,32 ... Equation 8 The condition necessary for this impedance setting is that the transfer characteristic required for the impedance filter 6 is the same as that of the HPF as shown in Equation 6. Passing a signal without phase delay at a high frequency in order to show characteristics. In contrast,
The transfer characteristics of the thinning filter 4 and the interpolation filter 9 are given by the following equation.
As shown in (1), it has a characteristic that the phase is delayed with the frequency, and cannot be simplified to the above-mentioned H _DEC = H _INT = 1. For this reason, the data sheet “Telecommunication Products Data Bo
ok 1992/1993 "was changed from Equation 6 to the following Equation 9.

H _FIL2 = 1−1 / (1 + jωC _FIL2 · R _FIL2 ) (9) It can be seen that the first term in _Expression 9 is a real number and does not need to be processed. The second term shows the LPF characteristic by C _FIL2 and R _FIL2 , which is a characteristic that passes through a low frequency region and attenuates a high frequency region. Therefore, since the first term is realized by feedback in the analog section before A / D conversion, and the second term is realized by digital signal processing by an impedance filter, a feedback circuit is required on the analog circuit side. Is done.

Therefore, the phase compensation filter 5 having the transfer characteristic shown in the above equation 2 is added to the impedance filter.

FIG. 2 shows a configuration example of digital signal processing of the phase compensation filter 5. The transfer characteristic H _FIL1 is given by:
This is the characteristic shown in FIG. In the figure, 41 is a delay circuit for an arbitrary time, 42 is a multiplier for multiplying an input signal by -1, 43 is a multiplier for doubling an input signal, and 44 is a multiplier for the -1 and 2 times multipliers 42 and 43. This is an adder for adding outputs. A signal obtained by doubling the input signal in the multiplier 43 and an input signal
The delay by 1 and the delay by the multiplier 41 and the product multiplied by the multiplier 42 are added by the adder 44, whereby the phase compensation filter 5 is realized.

FIG. 3 shows a vector diagram of characteristics of the phase compensation filter.

When the frequency is f = 0 with a radius of 1 around the coordinates (2,0), it has the characteristic of rotating clockwise starting from the coordinates (1,0). A characteristic φ (f) of the phase φ of the phase compensation filter with respect to the frequency f is expressed by the following equation (10).

Φ (f) = arc tan {sin (2π · f · Ts) / 2−cos (2π · f · Ts)} Equation 10 Equation 10 has a characteristic that the phase advances while the frequency is low. It is shown that. However, the gain increases little by little. When such a phase compensation filter 5 is added, the phase delay generated in the thinning filter 4 and the interpolation filter 9 (Equation 1)
) Can be compensated, so that the phase delay can be reduced.

On the other hand, the characteristic standard regarding the subscriber circuit impedance of the subscriber circuit is, for example, "CCITT BLUE BOO".
`` Return '' of `` K VOLUME III FASCICLE III.4-Rec.G.712 ''
As shown in "Loss", the frequency range is specified by the mismatch attenuation limited to 0.3 kHz to 3.4 kHz, and perfect impedance matching is not required. As a result, the frequency range applicable to the impedance filter 6 can be increased by adding the phase compensation filter 5, and depending on the type of impedance to be realized, the above-described analog feedback can be deleted and an impedance filter that can be realized only with a digital signal processing circuit. The effect that the range of application can be expanded is obtained.

FIG. 4 shows another example of the configuration of the phase compensation filter 5.

Reference numeral 51 denotes an input terminal of the phase compensation filter, and reference numeral 59 denotes an output terminal of the phase compensation filter. _{Reference numeral} 52 denotes a third LPF that cuts off an arbitrary frequency f _LPF3 , and receives a signal from the input terminal 51 as an input. 53 is a signal source of an arbitrary frequency fc,
A first multiplier 54 multiplies the signal of the signal source 53 by the output signal of the LPF 3. _{Reference numeral} 55 denotes a fourth LPF which receives the output signal of the multiplier 54 as an input and cuts off an arbitrary frequency f _LPF4 . Numeral 56 denotes a filter having the transfer characteristic of Equation 3, 57 denotes a second multiplier for multiplying the output signal of the filter 56 by the signal source 53, and 58 denotes an input signal of the multiplier 57. This is a fifth LPF that cuts off an arbitrary frequency f _LPF5 , and is a digital signal processing circuit that outputs to the output terminal 59.

The operation principle of the configuration example shown in FIG. 4 will be described below, but the third LPF 5 will be described in order to simplify the description.
2, the cutoff frequencies f _LPF3 , f _LPF4 , and f _LPF5 as transfer characteristics of the fourth LPF 55 and the fifth LPF ₅₈ are set to ideal characteristics shown by broken lines in FIGS. 7, 8, and 10, respectively. Then, the transmission gain G = 1 and the phase delay φ = 0
To simplify.

When the frequency of the input signal from the input 51 is converted, first, only the input signal component (M _IN ) is extracted by the third LPF 52 in order to remove alias noise as shown in FIG. The first multiplier 54 multiplies the signal of the frequency fc generated by the signal source 53 by the output signal of the third LPF 52. As a result, the output signal of the multiplier, the lower frequency fc as shown in FIG. 8, appears as an input signal to the upper and the lower side wave M _L, the upper side band M _U, is the frequency conversion. Here, the lower sideband M _L, the signal having the reverse spectrum is obtained from the frequency spectrum of the input to the input terminal 51 signal. Therefore, the digital filter 5 is taken out under the wave M _L by a fourth LPF55 having the filter characteristic shown in broken lines in FIG. 8, with the characteristic shown in Formula 3
Enter 6

FIG. 5 shows a configuration example of the digital filter 56.

The structure of the multiplier 42 shown in FIG.
Is changed to a 1-time multiplier 62. That is,
A signal obtained by doubling the input signal by the adder 43 and a signal obtained by delaying the input signal by the delay circuit 41 and multiplied by −1 by the multiplier 42 are added by the adder 44, which is shown in Expression 3. Thus, a filter 56 having the following characteristics is configured. Its characteristics are
The vector diagram shown in FIG. 6 has the characteristic that the delay of the phase φ decreases as the frequency f approaches fc. As a result, as shown in FIG. 9, the output characteristic of the filter 56 has a characteristic that the phase delay is 0 at the frequency fc and the phase delay increases (goes downward) as the frequency decreases. Therefore, the output signal of the filter 56 and the signal of the signal source 53 are multiplied by the multiplier 53 to perform frequency conversion.
When the signal is extracted by PF5, the output signal includes
As shown in FIG. 10, as the frequency increases, the characteristic that the phase advances is obtained, and the same characteristic as the phase compensation filter shown in FIG. 2 can be obtained.

As described above, since the phase delay can be compensated by adding the phase compensation filter 5 to the impedance filter, the frequency range applicable to the impedance filter can be increased.

Although the invention made by the present inventor has been specifically described based on the embodiment, it is needless to say that the present invention is not limited to the embodiment and can be variously modified without departing from the gist thereof. No.

In the above description, the case where the invention made by the present inventor is mainly applied to a digital signal processing circuit coupled to a subscriber line, which is the field of application, has been described, but the present invention is not limited to this. However, the present invention can be widely applied to various digital signal processing circuits.

The present invention can be applied on condition that at least a filter is provided.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, since the phase delay caused by the thinning filter and the interpolation filter can be compensated up to a high frequency, a digital signal processing circuit capable of realizing an impedance filter including a phase up to a high frequency can be obtained. Thus, as a digital signal processing circuit, a feedback circuit for compensating impedance / filter characteristics in an analog section can be simplified.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a configuration example of a digital signal processing device according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a phase compensation filter in the digital signal processing device.

FIG. 3 is a vector diagram showing characteristics of the phase compensation filter shown in FIG. 2;

FIG. 4 is a block diagram showing another configuration example of the phase compensation filter.

FIG. 5 is a circuit diagram illustrating a configuration example of a main part of the phase compensation filter illustrated in FIG. 4;

FIG. 6 is a vector diagram showing characteristics of the filter shown in FIG. 5;

FIG. 7 is a diagram illustrating a signal input through the input terminal illustrated in FIG. 4 and characteristics of a low-pass filter.

FIG. 8 is a diagram showing characteristics after frequency conversion by a multiplier.

FIG. 9 is a diagram showing characteristics when a phase rotation is applied by a filter.

FIG. 10 is a diagram illustrating characteristics after frequency conversion by a multiplier and an LPF.

[Explanation of symbols]

Reference Signs List 1 input terminal of digital signal processing circuit 20 2, 11 first and second LPF 3 A / D converter 4 thinning filter 5 phase compensation filter means 6 arbitrary impedance filter 7 adder 8 input signal from host device 9 interpolation Filter 10 D / A converter 12 Output terminal of digital signal processing circuit 20 Digital signal processing circuit 30 Interface means with subscriber line 31, 32 Subscriber line side terminal 33 Output of voltage control voltage source 35 Current control current source 36 inputs 35 voltage control voltage source 36 current control current source 37 voltage / current conversion resistor 41, 61 delay circuit 42-1 multiplier 43, 63 double multiplier 44, 64 adder 51 input terminal 52, 55, 58 Third, fourth, and fifth LPFs 53 oscillators 54, 57 multipliers 56 filters 59 output terminals 62 1 Coefficient R _RX voltage-current converting resistor coefficient F current controlled current source of the multiplier A voltage controlled voltage source

Claims (3)

[Claims] An A / D converter for A / D-converting an analog signal at every first sampling time interval, and an output signal of the A / D converter being sampled at a second sampling time interval to obtain data. A decimation filter for decimation, a digital filter arranged after the decimation filter and having an arbitrary impedance characteristic, and an interpolation filter for interpolating an output signal of the digital filter at a third sampling time interval. A D / A conversion circuit for D / A converting the output signal of the interpolation filter; and a digital signal processing circuit for setting an impedance by feeding back the analog signal after the D / A conversion to a subscriber line. Wherein the digital filter compensates for a lag phase between the decimation filter and the interpolation filter. A digital signal processing circuit including a phase compensation filter. 2. The phase compensation filter according to claim 1, wherein H = 2-Z ^-1.
2. The digital signal processing circuit according to claim 1, comprising a transfer function H represented by: 3. A first filter for cutting off an arbitrary frequency included in an input signal, and a first multiplication for multiplying an output signal of the first filter by a signal of an arbitrary frequency. , A second filter that cuts off an arbitrary frequency included in the output signal of the first multiplier, and a transfer function that is disposed after the second filter and that is represented by H = 2 + Z ^−1. A third filter provided with H; a second multiplier for multiplying an output signal of the third filter by a signal of an arbitrary frequency; and a second filter arranged at a subsequent stage of the second multiplier to cut an arbitrary frequency. The digital signal processing device according to claim 1, further comprising: a fourth filter that is turned off.