JPH11317669A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which includes plural semiconductor chips connected via a bus having small bus width. SOLUTION: This semiconductor device 100 is provided with a transmitting part CHIP0 and receiving part CHIP1 which are connected via a bus 110. The part CHIP0 includes an encoding part 120, which produces bit position information that shows the position of at least one selected bit among plural bits included in data by encoding the data including plural bits and an outputting part 122 which outputs the bit position information to the bus 110. The part CHIP1 includes an inputting part 130, which receives the bit position information from the bus 110 and a decoding part 132 which produces data by decoding the bit position information.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device connected via a bus having a large bus width (that is, having many bus lines) such as a data bus, an address bus, and a chip select bus. The present invention relates to a semiconductor device including a plurality of semiconductor chips.

[0002]

2. Description of the Related Art In recent years, a new field of multimedia has been developed. A major feature of this field is that it handles moving images. In order to handle moving images, it is necessary to transfer a large amount of data at high speed. In order to satisfy this demand, the width of a data bus for transferring data is generally increased.

However, increasing the width of the data bus leads to an increase in the size of the semiconductor device. 2. Description of the Related Art Conventionally, a technology has been developed to suppress an increase in the size of a semiconductor device by sharing a data bus and an address bus.

[0004]

However, in the prior art, the data bus and the address bus are merely shared, and the bus width of the data bus itself (or the address bus itself) cannot be reduced. .

An object of the present invention is to provide a semiconductor device including a plurality of semiconductor chips connected via a bus having a small bus width.

[0006]

According to the present invention, there is provided a semiconductor device comprising:
A semiconductor device comprising a transmitting unit and a receiving unit connected via a bus, wherein the transmitting unit encodes data including a plurality of bits, thereby transmitting the plurality of bits included in the data. An encoding unit that generates bit position information indicating a position of at least one bit selected among the bits;
An output unit that outputs the bit position information to the bus; an input unit that receives the bit position information from the bus; and a decoding unit that generates the data by decoding the bit position information. And a conversion part. Thereby, the above object is achieved.

[0007] The at least one selected bit may be a bit having a specific logical value.

[0008] The at least one selected bit may be a bit having a logical value changed as compared with previous data.

[0009] The transmitting unit indicates whether or not the number of bits having the specific logical value among the plurality of bits included in the data is larger than the number of bits having a logical value other than the specific logical value. The output unit further outputs the bit position information and the bit number comparison information to the bus, and the input unit outputs the bit position information and the bit position comparison information. The bit number comparison information may be received from the bus, and the decoding unit may generate the data by decoding the bit position information based on the bit number comparison information.

[0010] The encoding unit may generate a plurality of bit position information by encoding the data, and the output unit may serially output the plurality of bit position information to the bus.

Another semiconductor device according to the present invention is a semiconductor device connected to a bus, wherein data including a plurality of bits is encoded to select one of the plurality of bits included in the data. An encoding unit for generating bit position information indicating a position of at least one bit, and an output unit for outputting the bit position information to the bus, thereby achieving the above object.

Another semiconductor device of the present invention is a semiconductor device connected to a bus, wherein bit position information indicating the position of at least one selected bit among a plurality of bits included in data is transmitted from the bus. An input unit for receiving data and a decoding unit for generating the data by decoding the bit position information are provided, thereby achieving the above object.

The operation will be described below.

According to the semiconductor device of the present invention, bit position information indicating the position of at least one selected bit among a plurality of bits included in data is generated, and the bit position information is transmitted. The content of the data is transmitted from the transmitting unit to the receiving unit using bit position information having a smaller number of bits than the number of bits of the data to be transmitted.
Thus, the bit width of the bus connecting the transmitting unit and the receiving unit can be made smaller than the bit width of the data to be transmitted. For example, it becomes possible to transmit 8-bit data using a 3-bit bus. As a result, the size of the semiconductor device can be reduced.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) FIG. 1 shows a configuration of a semiconductor device 100 according to a first embodiment of the present invention. Semiconductor device 1
00 is the semiconductor chip CHIP0 and the semiconductor chip CHI.
P1. The semiconductor chip CHIP0 and the semiconductor chip CHIP1 are connected to each other via a bus 110. Bus 110 includes signal lines 110a, 110b and 110c. The width of the bus 110 is 3 bits. 3-bit bit position information (DB00, DB01,
DB02) is connected to the semiconductor chip CHIP via the bus 110.
0 is transferred to the semiconductor chip CHIP1.

The semiconductor chip CHIP0 has an internal circuit IN
T0 and an output circuit OUT0. Internal circuit INT0
Generates 8-bit data. Output circuit OUT0
Includes an encoding unit 120 that generates bit position information by encoding 8-bit data generated by the internal circuit INT0, and an output unit 122 that outputs the bit position information to the bus 110. Thus, the semiconductor chip CHIP0 functions as a transmission unit that transmits data.

The semiconductor chip CHIP1 has an input circuit IN
1 and an internal circuit INT1. The input circuit IN1 includes an input unit 130 that receives bit position information from the bus 110.
And a decoding unit 132 that generates 8-bit data by decoding the bit position information. The 8-bit data generated by the input circuit IN1 is output to the internal circuit INT1. Thus, the semiconductor chip CHIP1 functions as a receiving unit that receives data.

The bit position information indicates the position of at least one selected bit among the 8 bits included in the data generated by the internal circuit INT0. For example, the internal circuit INT0 uses 8-bit data (0, 1,
(0, 1, 0, 0, 1, 0) is assumed. In this case, the position of the bit having the logical value “1” is
(0,0,1), (0,1,1) and (1,1,0)
Represented by Therefore, when a bit having the logical value “1” is selected, the encoding unit 120 sets a plurality of bit position information (0, 0, 1) as information indicating the position of at least one selected bit. , (0,1,1) and (1,1,0), and the output unit 122 serially outputs the plurality of pieces of bit position information to the bus 110.

Similarly, 8-bit data (0, 1, 1)
(0,1,0,0,1,0), the positions of the bits having the logical value “0” are (0,0,0), (0,1,0),
(1,0,0), (1,0,1) and (1,1,1)
Represented by Therefore, when a bit having a logical value “0” is selected, the encoding unit 120 sets a plurality of pieces of bit position information (0, 0, 0) as information indicating the position of at least one selected bit. , (0,1,0),
(1,0,0), (1,0,1) and (1,1,1)
And the output unit 122 serially outputs the plurality of pieces of bit position information to the bus 110.

As described above, instead of transferring 8-bit data, information indicating the position of a bit having a specific logical value among the 8 bits included in the data (ie, bit position information) is transferred. In addition, data can be transferred using a bus having a bit width smaller than the bit width of the data to be transferred. As a result, the width of the bus can be reduced as compared with the conventional case. as a result,
The size of the semiconductor device 100 can be reduced.

Also, by transferring 3-bit bit position information instead of transferring 8-bit data, the data transfer efficiency can be improved. Hereinafter, an example in which the data transfer efficiency is improved will be described. Here, bit patterns 00 to 08 are defined as follows for 8-bit data.

Bit pattern 00: Logical value of all bits included in data is “1”: 1 way Bit pattern 01: Logical value of 1 bit included in data is “1”: 8 ways Bit pattern 02: Included in data The 2-bit logical value "1" is: 28 ways Bit pattern 03: The 3-bit logical value included in the data is "1": 56 ways Bit pattern 04: The 4-bit logical value contained in the data is "1" : 70 patterns Bit pattern 05: 5-bit logical value included in data is "1": 56 patterns Bit pattern 06: 6-bit logical value included in data is "1": 28 patterns Bit pattern 07: included in data 7-bit logical value "1": 8 bit patterns 08: Logical value of all bits included in data is "0": 1 bit pattern 00-bit One to nine cycles are required to transfer the pattern 08.
The appearance probabilities of the bit patterns 00 to 08 are 20%, 45%, 30%, 4%, 0.5%,
Under the conditions of 0.3%, 0.15%, 0.04% and 0.01%, a 3-bit data bus (ie,
Data is transferred in an average of 2.22 cycles using the bus 110). This is equivalent to transferring data in one cycle using a 6.66-bit data bus. Therefore, as compared with the case where data is transferred in one cycle using the 8-bit data bus, the data transfer efficiency is improved by one bit or more of the data bus.

The output circuit OUT0 determines whether the number of bits having a specific logical value among the 8 bits included in the data generated by the internal circuit INT0 is greater than the number of bits having a logical value other than the specific logical value It may further include a bit number comparison information generation unit 124 that generates bit number comparison information indicating whether or not the information is not valid. For example, the specific logical value is a logical value “1”.

In the following description, when the specific logical value is a logical value "1", the bit number comparison information is stored in the internal HL.
It is referred to as a bias determination signal IHLD. That is, the internal HL bias determination signal IHLD determines whether the number of bits having a logical value “1” among the 8 bits included in the data generated by the internal circuit INT0 is greater than the number of bits having a logical value “0”. It is a signal indicating whether or not.

When the number of bits having a logical value "1" out of the eight bits included in the data generated by the internal circuit INT0 is larger than the number of bits having a logical value "0", the internal HL bias determination signal The level of IHLD becomes high level ("H"). Otherwise, the internal HL
The level of the bias determination signal IHLD is low level ("L")
Becomes The internal HL deviation determination signal IHLD is
20 and the output unit 122.

It is preferable that the encoding unit 120 is configured to generate a smaller number of bit position information in accordance with the level of the internal HL bias determination signal IHLD.
With such a configuration, the number of times of transferring the bit position information from the semiconductor chip CHIP0 to the semiconductor chip CHIP1 can be reduced. For example, internal HL
The level of the bias determination signal IHLD is low ("L")
, Bit position information indicating the position of the bit having the logical value “1” is generated, and the internal HL bias determination signal IH is generated.
When the level of the LD is high (“H”), the internal HL bias determination signal IHLD is generated by generating bit position information indicating the position of a bit having a logical value “0”.
, The number of bit position information generated by the encoding unit 120 can be four or less.

The output unit 122 outputs the internal HL bias determination signal I
HLD is used as the HL deviation determination signal HLD as the signal line 11
Output to 2.

Encoding section 120 generates an internal data transfer control signal ITR for controlling the transfer of bit position information. The internal data transfer control signal ITR is
Supplied to The output unit 122 uses the internal data transfer control signal ITR as the data transfer control signal TR on the signal line 1.
14 is output.

The input unit 130 transmits the bit position information to the bus 1
10, the HL deviation determination signal HLD is received from the signal line 112, and the data transfer control signal TR is received from the signal line 114.

The decoding section 132 outputs the HL bias determination signal HL
The bit position information is decoded according to the level of D. For example, when the level of the HL bias determination signal HLD is low (“L”), the decoding unit 132 interprets the bit position information as indicating the position of a bit having a logical value “1”, and Decode the bit position information. When the level of the HL deviation determination signal HLD is high (“H”), the decoding unit 132 interprets the bit position information as indicating the position of a bit having a logical value “0”, and Decrypt the information. As described above, the interpretation of the HL deviation determination signal HLD needs to be determined in advance between the encoding unit 120 on the transmitting side and the decoding unit 132 on the receiving side.

Also, instead of transferring 8-bit data, transferring 1-bit HL deviation determination signal HLD and 3-bit bit position information can improve the data transfer efficiency. Hereinafter, an example in which the data transfer efficiency is improved will be described. Here, for 8-bit data, bit patterns 10 to 14 are defined as follows.

Bit pattern 10: The logical value of all bits included in the data is “0” or “1”: two ways Bit pattern 11: The logical value of one bit included in the data is “0” or “1”: 16 Bit pattern 12: Two-bit logical value included in data is “0” or “1”: 56 bit patterns 13: Three-bit logical value included in data is “0” or “1”: 112 bits Pattern 14: 4-bit logical value included in the data is "0" or "1": 70 patterns. One to five cycles are required to transfer bit patterns 10 to 14, respectively.
Under the condition that the appearance probabilities of the bit patterns 10 to 14 are 40%, 50%, 6%, 3.9%, and 0.1%, respectively, the 4-bit data bus (that is, the signal line 112 and the bus 110) to transfer data in an average of 1.74 cycles. This is equivalent to transferring data in one cycle using a 6.96-bit data bus. Therefore, as compared with the case where data is transferred in one cycle using the 8-bit data bus, the data transfer efficiency is improved by one bit or more of the data bus.

The logical values of all bits included in the data generated by the internal circuit INT0 are "1".
If it is (or logical value "0"), the bit position information is not transferred. In this case, the fact that bit position information is not transferred may be transmitted from output circuit OUT0 to input circuit IN1 using data transfer control signal TR.
The distinction of whether the logical values of all bits are “1” or “0” is
The determination can be made using the HL deviation determination signal HLD.

The bit position information (DB00, DB0
1, DB02), a signal line 112 for transmitting the HL deviation determination signal HLD, and a signal line 11 for transmitting the data transfer control signal TR.
4 may be shared with the address bus line. Semiconductor chip CHIP0 and semiconductor chip CH
By sharing the signal line with the IP1, the area required for providing the signal line can be reduced. As a result, the size of the semiconductor device 100 can be reduced.

In the example shown in FIG. 1, the internal circuit I
The number of bits of data generated by NT0 is 8, and the semiconductor chips CHIP0 to CHIP0
The number of bits of the bit position information transferred to 1 is 3.
However, the application of the present invention is not limited to these bit numbers. The internal circuit INT0 can generate data having an arbitrary number of bits. Also, bit position information having an arbitrary number of bits is transmitted from the semiconductor chip CHIP0 to the semiconductor chip C
HIP1.

FIG. 2 shows the semiconductor chip CH shown in FIG.
3 shows a configuration of an output circuit OUT0 of IP0.

The encoding section 120 has an output data holding circuit O
REG, a jumpable shift register JREG, and encoding elements ENC00 to ENC07.

The output unit 122 includes an output buffer OBUF
0, OBUF1 and OBUF2.

The bit number comparison information generation section 124 includes an HL bias determination circuit COMP.

The output circuit OUT0 is connected to the semiconductor chip CHI.
It receives 8-bit data output from the internal circuit INT0 of P0. In FIG. 2, each bit of the 8-bit data is described as IDB00 to IDB07. The 8-bit data is input to the output data holding circuit OREG and the HL bias determination circuit COMP.

The HL bias determination circuit COMP has eight bits included in the input data, the number of bits having a logical value of “1” (ie, “H” bit) and the number of bits having a logical value of “0” ( That is, the number of “L” bits) is compared. When the number of “H” bits is larger than the number of “L” bits, the HL bias determination circuit COMP
It outputs a high-level (ie, “H”) internal HL bias determination signal IHDL. If the number of “L” bits is larger than the number of “H” bits, the HL bias determination circuit COM
P outputs a low-level (ie, “L”) internal HL bias determination signal IHDL.

The output data holding circuit OREG latches the data output from the internal circuit INT0 at the timing when the internal data transfer control signal ITR becomes "H", and holds the data.

The internal data transfer control signal ITR is output from the jumpable shift register JREG. The timing at which the internal data transfer control signal ITR becomes "H" first is determined in response to the data latch signal TRR.
The timing when the internal data transfer control signal ITR becomes “H” thereafter is determined by the jumpable shift register JREG.
Is determined by

When receiving the internal HL deviation determination signal IHLD of "H", the output data holding circuit OREG inverts the logical values of the bits IDB00 to IDB07 included in the data and outputs the bit having the inverted logical value to the bit ROUT.
It outputs to the jumpable shift register JREG as 00 to ROUT07. On the other hand, the output data holding circuit ORE
When receiving the internal HL bias determination signal IHLD of “L”, G receives bits IDB00 to IDB07 included in the data.
Is output to the jumpable shift register JREG as bits ROUT00 to ROUT07 as it is.

Therefore, the bits IDB0 included in the data
When the number of "H" bits is large among 0 to IDB07, the "H" bit is inverted and output to "L" bit, and the "L" bit is inverted to "H" bit. Output. Bits IDB00 to IDB included in data
When the number of “L” bits out of 07 is large, such inversion operation is not performed.

The jumpable shift register JREG is
Bit RO output from output data holding circuit OREG
UT00 to ROUT07 are received and the clock signal CL
In synchronization with K, the bits of “H” among the bits ROUT00 to ROUT07 are sequentially selected, and the selection signal corresponding to the selected bit is set to “H”.

For example, bits ROUT00 to ROUT0
7, when only the bit ROUT00 is “H”, the jumpable shift register JREG stores the bit R
The selection signal REG00 corresponding to OUT00 is set to “H”.

Also, for example, bits ROUT00-RO
When only the bits ROUT01 and ROUT02 of the UT07 are “H”, the jumpable shift register JREG outputs the selection signals REG01 and REG02 corresponding to the bits ROUT01 and ROUT02 to the clock signal C.
Set to "H" sequentially in synchronization with LK.

Each of encoding elements ENC00-ENC07 outputs a 3-bit position signal indicating the position of its own encoding element in response to a corresponding one of selection signals REG00-REG07. That is, when the selection signal REG0k is “H”, the encoding element ENC0k is a 3-bit position signal Sk indicating its own position.
To the output buffer OBUF0. Where k is 0
-7.

This position signal indicates the position of the encoding element to which the "H" selection signal has been input. Therefore, this position signal indicates the position of the “H” bit among the bits ROUT00 to ROUT07. Bits ROUT00-R
The position of the “H” bit of OUT07 is determined by the position of “L” included in the data when the number of “H” bits among the bits IDB00 to IDB07 included in the data is larger than the number of “L” bits. Indicates the position of the bit, otherwise indicates the position of the "H" bit contained in the data.

When a 3-bit position signal is output from any one of the encoding elements ENC00 to ENC07,
The position signal is temporarily stored in the output buffer OBUF0. After the falling of the internal data transfer control signal ITR, the buffer OBU is synchronized with the clock signal CLK.
The position signal stored in F0 is bit position information (DB0
0, DB01, DB02).

Further, a plurality of position signals are output to the output buffer OB.
When sequentially input to UF0, these plurality of position signals are sequentially output as a plurality of bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK.

The internal HL bias determination signal IHLD is output as the HL bias determination signal HLD via the output buffer OBUF1. Internal data transfer control signal ITR is output as data transfer control signal TR via output buffer OBUF2.

Thus, the semiconductor chip CHIP0
Bit position information (D
B00, DB01, DB02) and the data transfer control signal T
R and the HL deviation determination signal HLD correspond to the semiconductor chip CHI.
Transferred to P1.

In this embodiment, 8-bit data is 3-bit bit position information (DB00, DB0).
1, DB02) and its bit position information (D
B00, DB01, and DB02) are transferred from the semiconductor chip CHIP0 to the semiconductor chip CHIP1 via the bus 110. The bit position information is information indicating the position of the “H” (or “L”) bit of the 8-bit data. Here, when the information indicating the position of the “H” bit of the 8-bit data is transferred as the bit position information, the information indicating the position of the “L” bit is not transferred.
Conversely, when information indicating the position of the “L” bit in the 8-bit data is transferred as bit position information, “
The information indicating the position of the "H" bit is not transferred, as long as the information indicating the position of the "H" (or "L") bit is transferred, the "L" (or "H") bit is not transferred. Is determined.

Also, among the bits included in the data,
It detects which of the number of “H” bits and the number of “L” bits is larger, and according to the detection result, the smaller of the number of “H” bits and the number of “L” bits By transferring the information indicating the bit position as the bit position information, the number of times the bit position information is transferred can be reduced, and as a result, the amount of data transferred between the semiconductor chips CHIP0 and CHIP1 can be reduced. Can be reduced.

FIG. 3 shows a configuration of the HL deviation determination circuit COMP shown in FIG. In FIG. 3, INP is an input voltage generation circuit, COM is a current mirror type comparison circuit,
EF is a reference voltage generation circuit, VDD is a first power supply, MP is P
MOS transistors, MN1 to MN4 are NMOS transistors, and / CS is a chip select signal.

The input voltage generation circuit INP has one PMO
An S-type transistor MP and eight NMOS-type transistors MN1 are provided. Each NMOS transistor MN1
Of the internal circuit INT of the semiconductor chip CHIP0
Bits IDB00 to IDB07 of data from 0 are applied. In response to the “H” bit, the NMOS transistor MN1 turns on. The greater the number of NMOS transistors MN1 that are turned on among the eight NMOS transistors MN1, the greater the number of NMOS transistors MN1 of the comparison circuit COM.
The gate voltage of the type transistor MN2 decreases.

The reference voltage generation circuit REF has one PMO
An S-type transistor MP and one NMOS-type transistor MN3 are provided. A constant voltage is applied to the gate of the NMOS transistor MN3. A constant voltage is also applied to the gate of the NMOS transistor MN4 of the comparison circuit COM.

Each NMO in input voltage generation circuit INP
Comparing the S-type transistor MN1 with the NMOS-type transistor MN3 in the reference voltage generation circuit REF,
The amount of current flowing through the NMOS transistor MN3 is NM
This corresponds to 4.5 times the amount of current flowing through the OS-type transistor MN1. Therefore, when four or less of the NMOS transistors MN1 in the input voltage generation circuit INP are turned on, the current flowing through the NMOS transistor MN3 in the reference voltage generation circuit REF is smaller than that in the input voltage generation circuit INP. 4 or less NMOS
Is larger than the current flowing through the NMOS transistor MN1, and in the comparison circuit COM, the NMOS transistor MN4
Is lower than the gate voltage of the NMOS transistor MN2. When five or more of the NMOS transistors MN1 in the input voltage generation circuit INP are turned on, the reference voltage generation circuit RE
F, the current flowing through the NMOS transistor MN3 is equal to or greater than five Ns in the input voltage generation circuit INP.
The current flowing through the MOS transistor MN1 is smaller than the current flowing through the MOS transistor MN1, and in the comparison circuit COM, the gate voltage of the NMOS transistor MN4 is
Gate voltage.

In such a configuration, when the chip select signal / CS becomes "L", each PMOS transistor MP is turned on, and the HL bias determination circuit COMP is activated. In this state, each bit IDB00 to IDB of data from the internal circuit INT0 of the semiconductor chip CHIP0 is
When four or less of the transistors 07 become “H”, four or less of the NMOS transistors MN1 in the input voltage generation circuit INP are turned on. As a result, the comparison circuit COM
In, the gate voltage of the NMOS transistor MN4 becomes lower than the gate voltage of the NMOS transistor MN2. In response to this, from the comparison circuit COM,
An internal HL bias determination signal IHLD indicating “L” is output.

Each bit IDB00 to IDB0 of data from the internal circuit INT0 of the semiconductor chip CHIP0 is
When five or more of the transistors 7 become "H", five or more of the NMOS transistors MN1 in the input voltage generation circuit INP are turned on. As a result, in the comparison circuit COM, the gate voltage of the NMOS transistor MN4 becomes higher than the gate voltage of the NMOS transistor MN2. In response to this, from the comparison circuit COM,
An “H” internal HL bias determination signal IHLD is output.

As described above, the HL bias determination circuit COMP
Compares the number of “H” bits and the number of “L” bits included in the data output from the internal circuit INT0,
When the number of “H” bits is larger than the number of “L” bits, the internal HL bias determination signal IHLD of “H” is output, and the number of “H” bits is “L”. Is smaller, the internal HL bias determination signal IHLD of “L”
Is output.

FIG. 4 shows a part of the configuration of output data holding circuit OREG shown in FIG. The circuit shown in FIG. 4 is provided so as to correspond to 1-bit IDB00 of data input to output data holding circuit OREG.
A circuit similar to the circuit shown in FIG. 4 is provided so as to correspond to each of the other 7 bits input to output data holding circuit OREG. Therefore, the output data holding circuit ORE
In G, eight circuits shown in FIG. 4 are provided.

In FIG. 4, INV is an inverter circuit,
CINV1 to CINV4 are clock control type inverter circuits.

When the internal data transfer control signal ITR becomes "H" in a state where the internal HL bias determination signal IHLD indicates "H", the 1-bit IDB00 of the data is changed from the clock control type inverter circuit CINV1 to the inverter circuit INV to the clock. The signal is transmitted and inverted on the path of the control type inverter circuit CINV3 and output as a bit ROUT00.

When the internal HL bias determination signal IHLD indicates "L", the internal data transfer control signal IHLD
When TR becomes "H", 1-bit data IDB00
Are clock-controlled inverter circuits CINV1 and CINV
It is output as a bit ROUT00 without being inverted via V4.

As described above, the output data holding circuit OREG
Are bits IDB00 to IDB07 included in the data when the internal HL bias determination signal IHLD is "H".
Are output as bits ROUT00 to ROUT07, and when the internal HL bias determination signal IHLD is "L", the bits IDB00 to IDB07 included in the data are left as they are. Output as bits ROUT00 to ROUT07.

FIG. 5 shows the configuration of the jumpable shift register JREG shown in FIG. In FIG.
EGC, JREGC00 to JREGC07 are circuits per stage of the jumpable shift register JREG, and NAN.
D is a two-input NAND circuit, NOR is a two-input NOR circuit,
INV is an inverter circuit, CINV is a clock control type inverter circuit, REG00 to REG07 are circuits JREG.
Outputs of C00 to JREGC07. REG0
0 to REG07 are not shown for simplicity.

The jumpable shift register JREG is
Circuits JREGC00-JREGC07 and JREGC
And These circuits are connected in series. The circuits JREGC00 to JREGC07 output the bits ROUT00 to RO output from the output data holding circuit OREG.
It is provided so as to correspond to UT07, respectively. Circuit JRE of the first stage of the jump register JREG
The GC is provided as a dummy. This first stage circuit J
A signal of “H” (voltage VDD) is always input to the REGC, instead of the bit from the output data holding circuit OREG. When the internal data transfer control signal ITR becomes “H”, the second and subsequent circuits JREGC00 to JREGC
07, a “H” bit is applied to the second and subsequent circuits JR from the next rising of the clock signal CLK.
The output operation of EGC00 to JREGC07 becomes possible.

The internal data transfer control signal ITR first becomes "H" in synchronization with the data latch signal TRR, and thereafter becomes "H" in response to a bit from the circuit JREGC07 of the last stage. First, when the data latch signal TRR becomes “H”, the NMOS transistor MN11 is turned on. As a result, the internal data transfer control signal ITR becomes "H". After that, the final stage circuit JREGC0
Each time the "H" bit is output from 7, the PMOS transistor MP11 is turned on. As a result, the internal data transfer control signal ITR becomes "H".

When the "H" bit is output from the first-stage circuit JREGC, the next-stage circuit JREGC00 inputs the "H" bit to the NAND circuit NAND and the NMOS transistor MN12. As a result, NMOS
The type transistor MN12 is turned on. NAND circuit NA
The “H” bit and the bit ROUT00 from the output data holding circuit OREG are input to ND. As a result, when the bit ROUT00 is “H”,
The NAND circuit NAND outputs an “L” bit. In response, at the next rise of the clock signal CLK,
An “H” selection signal REG00 is output from the NOR circuit NOR11. At the same time, the bit of “H” is set to the NOR circuit NOR.
12, and the “H” bit is output to the subsequent circuit JREGC0 via the NMOS transistor MN12.
1 is output.

When the bit ROUT00 is "L", an "H" bit is output from the NAND circuit NAND, and in response to this, at the next rising of the clock signal CLK, "L" is output. The selection signal REG00 is output from the NOR circuit NOR11.

On the other hand, when the bit ROUT00 is "L", the NMOS transistor MN12 is turned off, so that the "L" bit from the NOR circuit NOR12 is not output to the subsequent circuit JREGC02. Instead, the PMOS transistor MP22 is turned on, so that the “H” bit from the first-stage circuit JREGC is
Circuit JR at the subsequent stage via MOS transistor MP22
Output to EGC02. However, at this time, “H” is applied from the first-stage circuit JREGC to the second-stage circuit JREGC02.
Are immediately transmitted without waiting for the rise of the clock signal CLK.

Similarly, the circuits JREGC01 to JREGC01
In any of GC07, the output data holding circuit OR
When the “H” bit ROUT is input from the EG, the “H” selection signal REG is output at the next rising of the clock signal CLK after the “H” bit is input from the previous-stage circuit JREGC. At the same time, the "H" bit is output to the subsequent circuit JREGC. Also, when the “L” bit ROUT is input from the output data holding circuit OREG, the “H” bit is immediately transmitted to the circuit JREGC from the preceding stage to the subsequent stage JREGC, and at the next rising of the clock signal CLK, “ An L ″ bit REG is output.

As described above, the jumpable shift register JREG stores the bit R from the output data holding circuit OREG.
When OUT00 to ROUT07 are input, the bits ROUT00 to ROUT07 are synchronized with the clock signal CLK.
Are sequentially selected, and the selection signal REG corresponding to the selected bit is set to "H".

FIGS. 6A to 6H show circuit configurations of the encoding elements ENC00 to ENC07 shown in FIG. 6A to 6H, MN31 to MN33.
Indicates an NMOS transistor.

For each of the encoding elements ENC00 to ENC07, three NMOS transistors MN31 to MN33 are used.
One of the ground potential and the power supply potential is selectively applied to the input side of the NMOS transistors MN31 to MN
The combinations of the potentials on the input side of the 33 are different.
For example, in the encoding element ENC00 shown in FIG. 6A, three NMOS transistors MN31 to MN31 are used.
The ground potential is applied to all of the input sides of N33. In the encoding element ENC05 shown in FIG. 6F, two NMOS transistors MN31 and MN3 are used.
3, a ground potential is applied to the input side, and a power supply potential is applied to the input side of one NMOS transistor MN32.

In any of encoding elements ENC00 to ENC07, jumpable shift register JRE
When an “H” selection signal REG from G is input to the gates of the three NMOS transistors MN31 to MN33,
These NMOS transistors MN31 to MN33 are turned on, and these NMOS transistors MN31
.. MN33 are output as 3-bit position signals.

Thus, the encoding elements ENC00 to ENC00
Each of ENC07 is provided with a selection signal REG00-REG.
When the corresponding selection signal of “07” becomes “H”, a 3-bit position signal indicating the position of its own encoding element is output.

With such a configuration, the bit position information indicating the position of the smaller one of the “H” bit and the “L” bit included in the 8-bit data is output, and the bit position information is output. An HL bias determination signal HLD indicating whether the bit position indicated by the information is the “H” bit position or the “L” bit position can be output.

FIG. 7 shows a configuration of the input circuit IN1 shown in FIG. The input circuit IN1 is a semiconductor chip CHIP
3 bit position information (DB00,
DB01, DB02) into 8-bit data,
The 8-bit data is transferred to the internal circuit INT1.

The input circuit IN1 includes an input section 130 and a decoding section 132 (see FIG. 1).

The input unit 130 has an input buffer IBUF
0, IBUF1 and IBUF2.

The decoding unit 132 is provided with the input data holding circuit I
REG and decode elements DEC10-DEC17.

Output circuit OUT of semiconductor chip CHIP0
The bit position information (DB00, DB01, DB02) of three bits transferred from the bus 0 through the bus 110 is input to the decode element DEC10 via the input buffer IBUF0.
To DEC17. Every time 3-bit bit position information (DB00, DB01, DB02) is input,
Bit position information (DB00, DB01, DB02)
Decoding is performed by one of the decoding elements DEC10 to DEC17. As a result, bit INDEC10
One of the INDECs 17 becomes "H" and is input to the input data holding circuit IREG. Here, INDEC1
0 to INDEC 17 are decoding elements DEC10 to DEC
17 shows the bits output from 17 respectively.

Output circuit OUT of semiconductor chip CHIP0
The HL bias determination signal HLD transferred from 0 through the signal line 112 is input to the input buffer IBUF1, and is output to the input data holding circuit IREG as the internal HL bias determination signal IHLD.

Output circuit OUT of semiconductor chip CHIP0
The data transfer control signal TR transferred from 0 via the signal line 114 is input to the input buffer IBUF2 and output to the input data holding circuit IREG as the internal data transfer control signal TRD.

The input data holding circuit IREG receives the internal HL deviation determination signal IHLD of "H" (that is, the logical value of each bit of the data is inverted and transferred from the semiconductor chip CHIP0). Is the bit I output from the decoding elements DEC10-DEC17.
By inverting the logical values of NDEC10 to INDEC17, a bit ID having the same logical value as the original data is obtained.
B10 to IDB17 are generated. Bit IDB10-I
DB17 is an internal circuit INT of the semiconductor chip CHIP1.
1 is output.

When the internal HL deviation determination signal IHLD of "L" is input (that is, when each bit of data is transferred from the semiconductor chip CHIP0 as it is), the input data holding circuit IREG outputs the decode element DE.
Bit INDEC1 output from C10 to DEC17
Bits INDEC10 to INDEC17 are changed to bit IDB10 without inverting the logical values of 0 to INDEC17.
Output as IDB17. Thereby, bits IDB10 to IDB17 having the same logical value as the original data
Is obtained. Bits IDB10 to IDB17 are output to internal circuit INT1 of semiconductor chip CHIP1.

Input data holding circuit IREG is reset in response to a period in which internal data transfer control signal TRD is at a high level. After that, the input data holding circuit IRE
G operates in response to the bits INDEC10 to INDEC17 output from the decoding elements DEC10 to DEC17.

The input timing of the internal data transfer control signal TRD to the input data holding circuit IREG is determined by the bit INDEC10 from the decode elements DEC10 to DEC17.
To match the input timing of INDEC 17, input buffer IBUF2 is used to delay data transfer control signal TR by a predetermined delay time. The data transfer control signal TR thus delayed is output as the internal data transfer control signal TRD.

Bit IDB1 from input data holding circuit IREG to internal circuit INT1 of semiconductor chip CHIP1
0 to IDB17 latch the internal data transfer control signal T
This is performed at the timing of resetting the input data holding circuit IREG by RD.

As described above, the input circuit IN1 of the semiconductor chip CHIP1 outputs the 3-bit bit position information (DB00, DB01, DB02) from the semiconductor chip CHIP0.
Is input, the bit position information (position signal DB
00, DB01, DB02) to decode element DEC10
To DEC17 to generate bits INDEC10 to INDEC17, and set the logical values of bits INDEC10 to INDEC17 to internal H.
Bits IDB10 to IDB17 having the same logical value as the original data are generated by inverting or not inverting according to the L bias determination signal IHLD.

FIGS. 8A to 8H show circuit configurations of the decoding elements DEC10 to DEC17 shown in FIG.

For example, the decoding element DEC shown in FIG.
Reference numeral 10 denotes three inverter circuits INV0 and a NAND circuit N
An AND circuit and an inverter circuit INV1 are provided, and correspond to the encoding element ENC00 in FIG. FIG.
When the 3-bit bit position information (DB00, DB01, DB02) generated by the encoding element ENC00 of FIG. 6A is input, the decoding element DEC10 of FIG. Bit INDE
C10 is output.

The decoding element DEC1 shown in FIG.
1 denotes two inverter circuits INV0 and a NAND circuit NA
6 includes an ND and an inverter circuit INV1.
This corresponds to the encoding element ENC01 in (b). FIG.
When the 3-bit bit position information (DB00, DB01, DB02) generated by the encoding element ENC01 of FIG. 6B is input, the decoding element DEC11 of FIG. 6B responds to this input by “H”. Bit INDE
C11 is output.

Thus, the decoding element DEC10
DEC 17 converts the 3-bit bit position information into 8-bit data.

FIG. 9 shows a part of the configuration of input data holding circuit IREG shown in FIG. In FIG. 9, NOR
Is a NOR circuit, CINV is an inverter controlled by a clock, and INV is an inverter.

The circuit shown in FIG.
It is provided so as to correspond to the bit INDEC10 output from C10. Circuits similar to those shown in FIG. 9 are provided so as to correspond to bits INDEC11 to INDEC17 output from other decoding elements DEC11 to DEC17, respectively. Therefore, eight circuits shown in FIG. 9 are provided in the input data holding circuit IREG.

The circuit shown in FIG. 9 is reset at the rise of internal data transfer control signal TRD and outputs "L" bit IDB10. In a state where the “L” internal HL bias determination signal IHLD is input, when the “L” bit INDEC10 is input from the decoding element DEC10, the “L” bit IDB10 is output as it is, and the decoding element DEC10 outputs "H" bit I
When the NDEC 10 is input, the logical value of the bit IDB10 is inverted, and the “H” bit IDB10 is output.

When the circuit shown in FIG. 9 is reset at the rise of internal data transfer control signal TRD,
When the internal HL bias determination signal IHLD of “H” is being input, the internal data transfer control signal TRD
, The logical value of the bit IDB10 is inverted, and the “H” bit IDB10 is output. The “L” bit IN is supplied from the decode element DEC10.
When DEC10 is input, “H” bit IDB10
Is output as it is, and when the "H" bit INDEC10 is input from the decoding element DEC10, the logical value of the bit IDB10 is inverted and the "L" bit IDB
10 is output.

This operation is performed by the decoding element DEC1
0 to INDEC10 output from DEC17
This is performed for each INDEC 17. As a result, the bits INDEC10 to INDEC are output from the input data holding circuit IREG.
17 is output.

In the circuit of FIG. 9, the bias determination signal IH
LD is a bit INDEC input to the data input terminal.
It is used to control whether the signal 10 is output to the output terminal IDB10 in the normal direction or the inverted state.

Specifically, when the bias determination signal IHLD is "H", the bit INDEC10 input to the data input terminal is input via the inverter CINV5, and when the bias determination signal IHLD is "L". In some cases, the bit INDEC10 input to the data input terminal
Is input via a two-stage inverter of an inverter INV4 and an inverter CINV3.

When the data appearing at node A is "H", inverters CINV2 and CINV8 are activated, and inverters CINV6 and CINV7 are inactivated. As a result, internal data transfer control signal TRD
Becomes “H”, and after the reset is applied, the bit I
DB10 becomes "H".

When the data appearing at node A is at "L", inverters CINV2 and CINV8 are deactivated, and inverters CINV6 and CINV7 are activated. As a result, internal data transfer control signal TRD
Becomes “H”, and after the reset is applied, the bit I
DB10 becomes "L".

FIG. 10 is a timing chart showing the operation of the output circuit OUT0 of the semiconductor chip CHIP0 and the operation of the input circuit IN1 of the semiconductor chip CHIP1.

In the semiconductor chip CHIP0, when the internal data transfer control signal ITR becomes "H", the bits ROUT00 to ROUT07 are output from the output data holding circuit OREG, and from the next rising of the clock signal CLK,
The selection signals REG00 to REG00 are synchronized with the clock signal CLK.
The selection signal of “H” in REG07 is sequentially output from the jumpable shift register JREG. Each time the “H” selection signal is output from the jumpable shift register JREG, 3-bit bit position information (DB00, DB
01, DB02).

In semiconductor chip CHIP1, internal data transfer control signal TRD is generated by delaying data transfer control signal TR. Internal data transfer control signal T
When RD becomes “L”, 3-bit bit position information (D
B00, DB01, and DB02), the “H” bit of the bits INDEC10 to INDEC17 is sequentially input to the input data holding circuit IREG. The input data holding circuit IREG continues to output the bits IDB10 to IDB17 having the same logical value as the original data until the internal data transfer control signal TRD becomes “H”.

In FIG. 10, after falling of internal data transfer control signal TRD, bit INDEC 10
Some time elapses before 〜INDEC 17 appears. This is because the internal HL bias determination signal IHLD of "H"
Is input (that is, when the number of “H” bits among the bits included in the data is greater than the number of “L” bits), the decoding elements DEC10 to DEC17 at the rise of the internal data transfer control signal TRD After resetting the bits INDEC10 to INDEC17 output from the terminal to "L", the bits IDB10 to IDB17 are simultaneously rewritten to "H". "H" for data
When a large number of bits are included, only the information indicating the position of the “L” bit is transferred, and the information indicating the position of the “H” bit is not transferred. By using the above timing, the input data holding circuit IREG shown in FIG. 9 operates well.

In FIG. 10, the third data transfer period is a period during which all “L” data (that is, data in which the logical values of all bits are “0”) is transferred. In the third data transfer period, the HL deviation determination signal HLD and the data transfer control signal TR are output from the transmitting semiconductor chip CHIP0, but the bit position information is not output. The bit position information is UNKNOWN. In this state, in the semiconductor chip CHIP1 on the receiving side, all data of the input data holding circuit IREG is reset in response to the internal data transfer control signal TRD. As a result, the input data holding circuit IRE
The bits IDB10 to IDB17 output from G are all "L". In response to the input of the next data transfer control signal TR, the data of the input data holding circuit IREG is reset again. Simultaneously with this reset, the data of the input data holding circuit IREG is latched in the internal circuit INT1. As a result, all "L" data has been transferred. The same applies to the case of transferring all “H” data. However, in this case, after receiving the HL bias determination signal HLD, the bits IDB10 to
It is necessary to take a timing margin until all the IDBs 17 become "H" until the next data transfer control signal TR is input.

In the first embodiment, when all the bits IDB00 to IDB07 included in the data are "L", only the reset operation by the data transfer control signal TR is performed without transferring the bit position information. ing. That is, the internal HL deviation determination signal IHLD of “L”
Is input to the input data holding circuit IREG, the input data holding circuit IREG outputs the “L” bits IDB00 to IDB after the reset by the data transfer control signal TR.
B07 is output as it is.

Further, the bit IDB00 included in the data
When IDB07 to IDB07 are all "H", the internal HL deviation determination signal IHLD of "H" is output from the input data holding circuit IRE.
G is input to the input data holding circuit IREG.
After the reset by the data transfer control signal TR, the logical values of the bits IDB00 to IDB07 are simultaneously inverted to output the "H" bits IDB00 to IDB07.

As is apparent from the above description, in the semiconductor device of the first embodiment, 8-bit data is encoded into 3-bit bit position information. The 3-bit bit position information is transferred via the bus. Then, the 3-bit bit position information is decoded into 8-bit data. Therefore, the number of signal lines required for transferring data can be reduced.

Further, the number of "H" bits is compared with the number of "L" bits, and information indicating the position of the smaller bit is transferred together with the HL bias determination signal HLD according to the comparison result. Therefore, efficient data transfer becomes possible.

The circuits shown in FIGS. 2 to 9 are merely examples, and various modifications are possible. Alternatively, a circuit having a similar function may be applied instead of these circuits.

(Embodiment 2) FIG. 11 shows a configuration of a semiconductor device 200 according to Embodiment 2 of the present invention. The semiconductor device 200 includes a semiconductor chip CHIP2 and a semiconductor chip CHIP3.
This provides an advantage that a signal line for transferring the HL deviation determination signal HLD is not required. Thereby, the area required for providing the signal line is reduced. As a result, the size of the semiconductor device 200 is reduced.

In the semiconductor device 200, the logical value of each bit of the data transferred this time is compared with the logical value of each bit of the data transferred last time. As a result, a bit having a changed logical value as compared with the previously transferred data is selected, and information indicating the position of the selected bit is transferred.

The semiconductor device 200 includes a semiconductor chip CHI.
P2 and a semiconductor chip CHIP3 are included. The semiconductor chip CHIP2 and the semiconductor chip CHIP3 are connected to the bus 210
Are connected to each other. Bus 210 includes signal lines 210a, 210b and 210c. Bus 2
The width of 10 is 3 bits. The 3-bit bit position information (DB00, DB01, DB02) is transferred from the semiconductor chip CHIP2 to the semiconductor chip CHIP via the bus 210.
3 is transferred.

The semiconductor chip CHIP2 has an internal circuit IN
T2 and an output circuit OUT2. Internal circuit INT2
Generates 8-bit data. Output circuit OUT2
Includes an encoding unit 220 that generates bit position information by encoding 8-bit data generated by the internal circuit INT2, and an output unit 222 that outputs the bit position information to the bus 210. Thus, the semiconductor chip CHIP2 functions as a transmitting unit that transmits data.

The semiconductor chip CHIP3 is connected to the input circuit IN
3 and an internal circuit INT3. The input circuit IN3 receives the bit position information from the bus 210,
And a decoding unit 232 that generates 8-bit data by decoding the bit position information. The 8-bit data generated by the input circuit IN3 is output to the internal circuit INT3. Thus, the semiconductor chip CHIP3 functions as a receiving unit that receives data.

The bit position information indicates the position of a bit having a changed logical value as compared with the data transferred last time. For example, the previously transmitted 8-bit data is (0,
1,0,1,0,0,1,0), and the 8-bit data to be transferred this time is (0,1,0,1,1,0,
1, 0). In this case, the position of the bit whose logical value has changed is represented by (1, 0, 0). Accordingly, the encoding unit 220 generates bit position information (1, 0, 0), and the output unit 222 outputs this bit position information to the bus 210.

The 8-bit data to be transferred this time is generated by the internal circuit INT2, and is output from the output circuit O2.
Provided to UT2. The previously transferred 8-bit data is held inside the encoding unit 220 of the output circuit OUT2.

Encoding section 220 generates an internal data transfer control signal ITR for controlling the transfer of bit position information. The internal data transfer control signal ITR is output from the output unit 222.
Supplied to The output unit 222 uses the internal data transfer control signal ITR as the data transfer control signal TR on the signal line 2.
14 is output.

As described above, instead of transferring 8-bit data, information indicating the position of a bit having a logical value that has changed compared to the previously transferred data among the 8 bits included in the data (ie, By transferring the (bit position information), data can be transferred using a bus having a bit width smaller than the bit width of the data to be transferred. As a result, the width of the bus can be reduced as compared with the conventional case. As a result, the size of the semiconductor device 200 can be reduced.

Also, by transferring 3-bit bit position information instead of transferring 8-bit data, data transfer efficiency can be improved. Hereinafter, an example in which the data transfer efficiency is improved will be described. Here, bit patterns 20 to 28 are defined as follows for 8-bit data.

Bit pattern 20: 0 bit changes compared to previously transferred data: 1 way Bit pattern 21: 1 bit changes compared to last transferred data: 8 ways Bit pattern 22: Last transferred 2 bits changed compared to the transferred data: 28 patterns Bit pattern 23: 3 bits changed compared to the previously transferred data: 56 patterns Bit pattern 24: 4 bits changed compared to the previously transferred data : 70 patterns Bit pattern 25: 5 bits changed compared to the previously transferred data: 56 patterns Bit pattern 26: 6 bits changed compared to the previously transferred data: 28 patterns Bit pattern 27: previously transferred 7 bits change compared to transferred data: 8 ways Bit pattern 28: 8 bits change compared to previously transferred data : 1 cycle to 9 cycles are required respectively in order to transfer one street bit pattern 20 bit pattern 28.
The appearance probabilities of the bit patterns 20 to 28 are 50%, 40%, 8%, 1.5%, 0.4%,
0.08%, 0.015%, 0.004%, 0.001
%, The data is transferred on average over 1.63 cycles using a 3-bit data bus (ie, bus 210). This is equivalent to transferring data in one cycle using a 4.89-bit data bus. Therefore, the data transfer efficiency is improved by 3 bits or more of the data bus as compared with the case where data is transferred in one cycle using the 8-bit data bus.

FIG. 12 shows the output circuit OU shown in FIG.
3 shows the configuration of T2. Output circuit OUT2 shown in FIG.
Is composed of an HL bias determination circuit COMP and an output buffer O
BUF1 is deleted, and a previous data holding circuit BD for holding each bit of previously transferred data.
The configuration of the output circuit OUT0 shown in FIG. 2 is that an exclusive OR circuit XOR for comparing the REG with each bit of data transferred this time and each bit of data transferred last time is added. Is different.

In FIG. 12, components having the same functions as those of output circuit OUT2 shown in FIG. 2 are denoted by the same reference numerals, and description thereof will be simplified.

In the output circuit OUT2 of FIG. 12, first, the previous data holding circuit BDREG and the output data holding circuit OREG1 are initialized by the reset signal RESET. Thereby, the previous data holding circuit BDR
Each bit of the data held in the EG and each bit of the data held in the output data holding circuit OREG1 are "
L ”.

Next, the data generated by the internal circuit INT of the semiconductor chip CHIP2 is input to and held in the output data holding circuit OREG1. Exclusive OR circuit X
The OR compares each bit of the data held in the previous data holding circuit BDREG and each bit of the data held in the output data holding circuit OREG1 with corresponding bits in the order of the bit arrangement. As a result of the comparison, if the logical value of the bit held in the output data holding circuit OREG1 is different from the logical value of the bit held in the previous data holding circuit BDREG, the exclusive OR circuit XOR
Sets the bit corresponding to the bit whose logical value has changed to "
H ”to output this bit to the jumpable shift register JREG. The bits output from the exclusive OR circuit XOR are bits ROUT00 to ROUT0.
Notation 7

The jumpable shift register JREG is
The bits ROUT00 to ROUT00 are synchronized with the clock signal CLK.
“H” bits are sequentially selected from ROUT07, and a selection signal corresponding to the selected bit is set to “H”.

The previous data holding circuit BDREG updates the data held in the previous data holding circuit BDREG by inverting the logical value of the bit corresponding to the "H" selection signal among the selection signals REGC00-07. In this way, the data previously held in the data holding circuit BDREG is sequentially updated.

Each of the encoding elements ENC00 to ENC07 responds to the selection signal REG00 to REG07 having the corresponding selection signal attaining "H", and outputs a 3-bit position signal indicating the position of its own encoding element. Output.

A 3-bit position signal output from any of encoding elements ENC00 to ENC07 is temporarily stored in output buffer OBUF0. Thereafter, the 3-bit position signal stored in the output buffer OBUF0 is transferred to the bus 210 as bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK after the falling of the internal data transfer control signal ITR. Is output.

A plurality of position signals are output to the output buffer OB.
When stored in UF0, these plurality of position signals are sequentially output as a plurality of bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK.

FIG. 13 shows a part of the configuration of output data holding circuit OREG1 shown in FIG. The circuit shown in FIG. 13 is provided so as to correspond to 1-bit IDB00 of data input to output data holding circuit OREG1. A circuit similar to the circuit shown in FIG. 13 is provided so as to correspond to the other seven bits input to output data holding circuit OREG1. Therefore, eight circuits shown in FIG. 13 are provided in the output data holding circuit OREG1.

In the circuit shown in FIG. 13, when the data control signal ITR becomes "H", the clock control type inverter circuit CINV1 is turned on. As a result, 1-bit IDB00 of data is stored in clock-controlled inverter circuit CI.
Bit R via the inverter NV1 and the inverter circuit INV1.
Output as OUT00.

FIG. 14 shows a part of the structure of the previous data holding circuit BDREG shown in FIG. The circuit shown in FIG. 14 is provided so as to correspond to the selection signal REGC00 input to the previous data holding circuit BDREG. A circuit similar to the circuit shown in FIG. 14 is provided so as to correspond to the other seven selection signals input to the previous data holding circuit BDREG. Therefore, eight circuits shown in FIG. 14 are provided in the previous data holding circuit BDREG.

In the circuit shown in FIG. 14, when the reset signal RESET goes "H", the output of the NOR circuit NOR1 goes "L". At this time, the “L” selection signal REG0
If 0 is input, the inverter circuit CI
NV6 and CINV7 are turned on. As a result, the output from NOR circuit NOR1 (that is, bit ROUT00)
Are kept at “L”.

When the selection signal REG00 is inverted to “H”, the inverter circuits CINV6 and CINV6 become inactive.
INV7 is turned off and the inverter circuits CINV2 and CINV2 are turned off.
INV8 turns on. At this time, the output of the NOR circuit NOR2 is "L". When the output of the NOR circuit NOR2 is input to the NOR circuit NOR1 via the inverter INV1 and the inverter circuit CINV2, the output of the NOR circuit NOR1 is inverted. As a result, the bit ROUT00 becomes “H”. Even if the selection signal REG00 is inverted again and returns to “L”, the bit IDB10 is kept at “H”. However, the inverter circuits CINV6, CIN
V7 is turned on, and the output of the NOR circuit NOR2 becomes "H".

Further, the selection signal REG00 is further inverted again to "H", and the inverter circuits CINV2 and CI
When the NV8 turns on, the output of the NOR circuit NOR1 is inverted because the output of the NOR circuit NOR2 is "H". As a result, the bit ROUT00 becomes “L”.

FIG. 15 shows the input circuit IN shown in FIG.
3 is shown.

The input circuit IN3 is a semiconductor chip CHIP
3 bit position information (DB00,
DB01, DB02) into 8-bit data,
The 8-bit data is output to the internal circuit INT3.

The configuration of input circuit IN3 is substantially the same as the configuration of input circuit IN1 shown in FIG. However, the configuration of both is different in that the output buffer OBUF1 is deleted and in the configuration of the input data holding circuit IREG1.

In FIG. 15, components having the same functions as those of input circuit IN1 shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be simplified.

In the input circuit IN3, first, in response to the reset signal RESET, the input data holding circuit IRE
G1 is initialized. Thereby, each bit of the data held in the input data holding circuit IREG1 is initialized to “L”.

Output circuit OUT of semiconductor chip CHIP2
The bit position information (DB00, DB01, DB02) of 3 bits transferred from the bus 2 through the bus 210 receives the decode element DEC via the input buffer circuit IBUF0.
10 to DEC17. Each time the 3-bit bit position information (DB00, DB01, DB02) is input, the bit position information (DB00, DB01, DB02)
Is decoded by one of the decoding elements DEC10 to DEC17. As a result, bit INDEC1
Any of 0 to INDEC 17 becomes "H". The bits INDEC10 to INDEC17 are input to the input data holding circuit IREG.

The input data holding circuit IREG1 has the structure shown in FIG.
Has the same configuration as the previous data holding circuit BDREG shown in FIG. When the reset signal RESET goes to "H", the bit IDB10 is set to "L". As long as the "L" bit INDEC10 is input from the decoding element DEC10, the bit IDB10 is kept at "L".

When the bit INDEC10 is inverted to become a "H" bit, the bit IDB10 is inverted to become "H". Even if the bit INDEC10 is inverted again and returns to “L”, the bit ICB10 is kept at “H”. However, when the bit INDEC10 is further inverted to “H”, the bit IDB10 is returned to “L”.

The circuit corresponding to each bit held in the input data holding circuit IREG1 is shown in FIG.
This circuit is a register circuit in which data is updated (inverted) only when the input becomes "H". Therefore, except that the data is cleared at the initial reset,
The held data is not updated unless it becomes H. When a bit address different from the previous transmission data is transmitted, the decoder circuit outputs “H” for each bit of the input address. Is output.

In the input data holding circuit IREG1, the same output is held for bits having a logical value that has not changed compared to the previously transferred data. Therefore,
By transferring only bits of data different from the previously transferred data, all bits of data are transferred. As a result, the receiving-side semiconductor chip CHI
The original data can be reproduced at P3.

In FIG. 15, the internal data transfer control signal TRD is not input anywhere in the figure, but, for example, the internal data transfer control signal TRD is supplied to the internal circuit INT3 of the semiconductor chip CHIP3 to control the internal data transfer control. In response to signal TRD, bit I from input circuit IN3
DB10 to IDB17 may be input to the internal circuit INT3 of the semiconductor chip CHIP3.

As is clear from the above description, in the semiconductor device 200 of the second embodiment, the semiconductor chip CHIP2
Instead of directly transmitting and receiving 8-bit data between the chip and the semiconductor chip CHIP3, each bit of the data transferred this time is compared with each bit of the data transferred last time, and compared with the data transferred last time. The information indicating the position of the bit having the changed logical value is transferred. Thereby, the number of signal lines required for data transfer can be reduced. Further, since there is no need to charge and discharge unnecessary signal lines, more efficient data transfer becomes possible.

The circuits shown in FIGS. 11 to 15 are merely examples, and various modifications can be made. Alternatively, a circuit having a similar function may be applied instead of these circuits.

[0158]

According to the semiconductor device of the present invention, bit position information indicating the position of at least one bit selected from a plurality of bits included in data is generated, and the bit position information is transmitted. The content of the data is transmitted from the transmitting unit to the receiving unit using bit position information having a smaller number of bits than the number of bits of the data to be transmitted. Thus, the bit width of the bus connecting the transmitting unit and the receiving unit can be made smaller than the bit width of the data to be transmitted. For example, it becomes possible to transmit 8-bit data using a 3-bit bus. As a result, the size of the semiconductor device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to a first embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of an output circuit OUT0 in the semiconductor chip CHIP0 shown in FIG.

FIG. 3 is a circuit diagram showing a configuration of an HL bias determination circuit COMP shown in FIG. 2;

FIG. 4 is a circuit diagram showing a configuration of a part of output data holding circuit OREG shown in FIG. 2;

FIG. 5 shows a jumpable shift register J shown in FIG. 2;
FIG. 3 is a circuit diagram illustrating a configuration of a REG.

6 (a) to 6 (h) are circuit diagrams showing configurations of encoding elements ENC00 to ENC07 shown in FIG.

FIG. 7 is a block diagram showing a configuration of an input circuit IN1 in the semiconductor chip CHIP1 shown in FIG.

8 (a) to 8 (h) are circuit diagrams showing configurations of the decoding elements DEC10 to DEC17 shown in FIG.

9 is a circuit diagram showing a configuration of a part of input data holding circuit IREG shown in FIG. 7;

FIG. 10 is a timing chart showing the operation of the output circuit OUT0 and the input circuit IN1 shown in FIG.

FIG. 11 is a block diagram showing a configuration of a semiconductor device 200 according to a second embodiment of the present invention.

12 is a block diagram showing a configuration of an output circuit OUT2 in the semiconductor chip CHIP2 shown in FIG.

13 is an output data holding circuit ORE shown in FIG.
FIG. 3 is a circuit diagram illustrating a partial configuration of G1.

14 is a previous data holding circuit BDR shown in FIG.
FIG. 3 is a circuit diagram illustrating a partial configuration of an EG.

FIG. 15 is a block diagram showing a configuration of an input circuit IN3 in the semiconductor chip CHIP3 shown in FIG.

[Explanation of symbols]

 CHIP0, CHIP2 Semiconductor chip CHIP1, CHIP3 Semiconductor chip OUT0, OUT2 Output circuit IN1, IN3 Input circuit OREG, OREG1 Output data holding circuit JREG Jumpable shift register ENC0 to ENC7 Encoding element COMP HL bias determination circuit OBUF0, OBUF1, OBUF2 Output buffer IREG , IREG1 Input data holding circuit DEC10-DEC17 Decoding element IBUF0-IBUF2 Input buffer circuit XOR Exclusive OR circuit BDREG Previous data holding circuit

Claims (7)

[Claims] 1. A semiconductor device comprising a transmitting unit and a receiving unit connected via a bus, wherein the transmitting unit is included in the data by encoding data including a plurality of bits. An encoding unit configured to generate bit position information indicating a position of at least one bit selected from the plurality of bits; and an output unit configured to output the bit position information to the bus. A semiconductor device, comprising: an input unit that receives bit position information from the bus; and a decoding unit that generates the data by decoding the bit position information. 2. The semiconductor device according to claim 1, wherein said at least one selected bit is a bit having a specific logical value. 3. The semiconductor device according to claim 1, wherein said at least one selected bit is a bit having a logical value changed as compared with previous data. 4. The transmission unit according to claim 2, wherein, among a plurality of bits included in the data, a number of bits having the specific logical value is larger than a number of bits having a logical value other than the specific logical value. The output unit further outputs the bit position information and the bit number comparison information to the bus, and the input unit outputs the bit position comparison information. The method according to claim 2, wherein information and the bit number comparison information are received from the bus, and the decoding unit generates the data by decoding the bit position information based on the bit number comparison information. Semiconductor device. 5. The encoding unit generates a plurality of bit position information by encoding the data, and the output unit serially outputs the plurality of bit position information to the bus. Item 2. The semiconductor device according to item 1. 6. A semiconductor device connected to a bus, wherein a position of at least one bit selected from among the plurality of bits included in the data is encoded by encoding data including a plurality of bits. A semiconductor device comprising: an encoding unit that generates bit position information to be indicated; and an output unit that outputs the bit position information to the bus. 7. An input unit for receiving, from the bus, bit position information indicating a position of at least one bit selected from a plurality of bits included in data, the semiconductor device being connected to a bus; A semiconductor device comprising: a decoding unit that generates the data by decoding position information.