JP3976923B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device, and in particular, a semiconductor including a plurality of semiconductor chips connected via a bus having a large bus width (that is, having many bus lines) such as a data bus, an address bus, and a chip select bus. Relates to the device.
[0002]
[Prior art]
In recent years, a new field of multimedia has been developed. A major feature of this field is the handling of moving images. In order to handle moving images, it is required to transfer a large amount of data at high speed. In order to satisfy this requirement, the bus width of the data bus for transferring data is generally increased.
[0003]
However, increasing the bus width of the data bus leads to an increase in the scale of the semiconductor device. Conventionally, a technique for suppressing an increase in the scale of a semiconductor device by sharing a data bus and an address bus has been developed.
[0004]
[Problems to be solved by the invention]
However, in the conventional technique, the data bus and the address bus are simply shared, and the bus width of the data bus itself (or the address bus itself) cannot be reduced.
[0005]
An object of the present invention is to provide a semiconductor device including a plurality of semiconductor chips connected via a bus having a small bus width.
[0006]
[Means for Solving the Problems]
The semiconductor device according to the present invention is a semiconductor device including a transmission unit and a reception unit connected via a bus, and the transmission unit encodes data including a plurality of bits into the data. An encoding unit that generates bit position information indicating a position of at least one selected bit among the plurality of bits included; and an output unit that outputs the bit position information to the bus; , An input unit that receives the bit position information from the bus, and a decoding unit that generates the data by decoding the bit position information. As a result, the above object is achieved.
[0007]
The at least one selected bit may be a bit having a specific logical value.
[0008]
The selected at least one bit may be a bit having a logic value changed as compared with the previous data.
[0009]
The transmission unit compares the number of bits indicating whether or not the number of bits having the specific logical value among a plurality of bits included in the data is greater than the number of bits having a logical value other than the specific logical value A bit number comparison information generation unit for generating information; the output unit outputs the bit position information and the bit number comparison information to the bus; and the input unit includes the bit position information and the bit number. The comparison information may be received from the bus, and the decoding unit may generate the data by decoding the bit position information based on the bit number comparison information.
[0010]
The encoding unit may generate a plurality of bit position information by encoding the data, and the output unit may serially output the plurality of bit position information to the bus.
[0011]
Another semiconductor device of the present invention is a semiconductor device connected to a bus and encodes data including a plurality of bits to thereby select at least one selected from the plurality of bits included in the data. An encoding unit that generates bit position information indicating a bit position and an output unit that outputs the bit position information to the bus are provided, thereby achieving the above object.
[0012]
Another semiconductor device of the present invention is a semiconductor device connected to a bus, and receives from the bus bit position information indicating the position of at least one bit selected from a plurality of bits included in data. And a decoding unit that generates the data by decoding the bit position information, thereby achieving the above object.
[0013]
The operation will be described below.
[0014]
According to the semiconductor device of the present invention, bit position information indicating the position of at least one selected bit among a plurality of bits included in data is generated, and the bit position information is transmitted. The content of the data is transmitted from the transmission unit to the reception unit using bit position information having a smaller number of bits than the number of bits of data to be transmitted. Thereby, the bit width of the bus connecting the transmission unit and the reception unit can be made smaller than the bit width of the data to be transmitted. For example, 8-bit data can be transmitted using a 3-bit bus. As a result, the scale of the semiconductor device can be reduced.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0016]
(Embodiment 1)
FIG. 1 shows a configuration of a semiconductor device 100 according to the first embodiment of the present invention. The semiconductor device 100 includes a semiconductor chip CHIP0 and a semiconductor chip CHIP1. The semiconductor chip CHIP0 and the semiconductor chip CHIP1 are connected to each other via the bus 110. Bus 110 includes signal lines 110a, 110b and 110c. The width of the bus 110 is 3 bits. The 3-bit bit position information (DB00, DB01, DB02) is transferred from the semiconductor chip CHIP0 to the semiconductor chip CHIP1 via the bus 110.
[0017]
The semiconductor chip CHIP0 includes an internal circuit INT0 and an output circuit OUT0. The internal circuit INT0 generates 8-bit data. The output circuit OUT0 includes an encoding unit 120 that generates bit position information by encoding 8-bit data generated by the internal circuit INT0, and an output unit 122 that outputs the bit position information to the bus 110. . Thus, the semiconductor chip CHIP0 functions as a transmission unit that transmits data.
[0018]
The semiconductor chip CHIP1 includes an input circuit IN1 and an internal circuit INT1. The input circuit IN1 includes an input unit 130 that receives bit position information from the bus 110, and a decoding unit 132 that generates 8-bit data by decoding the bit position information. The 8-bit data generated by the input circuit IN1 is output to the internal circuit INT1. Thus, the semiconductor chip CHIP1 functions as a receiving unit that receives data.
[0019]
The bit position information indicates the position of at least one bit selected from the 8 bits included in the data generated by the internal circuit INT0. For example, it is assumed that 8-bit data (0, 1, 0, 1, 0, 0, 1, 0) is generated by the internal circuit INT0. In this case, the position of the bit having the logical value “1” is represented by (0, 0, 1), (0, 1, 1) and (1, 1, 0). Therefore, when a bit having a logical value “1” is selected, the encoding unit 120 uses a plurality of pieces of bit position information (0, 0, 1) as information indicating the position of at least one selected bit. , (0, 1, 1) and (1, 1, 0), and the output unit 122 serially outputs the plurality of bit position information to the bus 110.
[0020]
Similarly, the positions of the bits having the logical value “0” in the 8-bit data (0, 1, 0, 1, 0, 0, 1, 0) are (0, 0, 0), (0, 1 , 0), (1, 0, 0), (1, 0, 1) and (1, 1, 1). Therefore, when a bit having a logical value “0” is selected, the encoding unit 120 uses a plurality of pieces of bit position information (0, 0, 0) as information indicating the position of at least one selected bit. , (0, 1, 0), (1, 0, 0), (1, 0, 1) and (1, 1, 1), and the output unit 122 buses these pieces of bit position information. 110 is serially output.
[0021]
In this way, instead of transferring 8-bit data, it is transferred by transferring information indicating the position of a bit having a specific logical value (ie, bit position information) among the 8 bits included in the data. Data can be transferred using a bus having a bit width smaller than the bit width of the data. Thereby, the width of the bus can be reduced as compared with the conventional one. As a result, the scale of the semiconductor device 100 can be reduced.
[0022]
In addition, the transfer efficiency of data can be improved by transferring the bit position information of 3 bits instead of transferring the data of 8 bits. Hereinafter, an example in which the data transfer efficiency is improved will be described. Here, bit pattern 00 to bit pattern 08 are defined as follows for 8-bit data.
[0023]
Bit pattern 00: Logical values of all bits included in data are “1”: 1 way
Bit pattern 01: 1-bit logical value included in data is “1”: 8 types
Bit pattern 02: 2-bit logical value included in data is “1”: 28 ways
Bit pattern 03: 3-bit logical value included in data is “1”: 56
Bit pattern 04: 4-bit logical value included in data is “1”: 70
Bit pattern 05: 5-bit logical value included in data is “1”: 56
Bit pattern 06: 6-bit logical value included in data is “1”: 28 ways
Bit pattern 07: 7-bit logical value included in data is “1”: 8 types
Bit pattern 08: Logical values of all bits included in data are “0”: 1 way
In order to transfer bit pattern 00 to bit pattern 08, 1 to 9 cycles are required. Appearance probabilities of bit pattern 00 to bit pattern 08 are 20%, 45%, 30%, 4%, 0.5%, 0.3%, 0.15%, 0.04%, and 0.01%, respectively. Under these conditions, data is transferred in an average of 2.22 cycles using a 3-bit data bus (that is, bus 110). This is equivalent to transferring data in one cycle using a 6.66 bit data bus. Therefore, compared with the case where data is transferred in one cycle using an 8-bit data bus, the data transfer efficiency for one bit or more of the data bus is improved.
[0024]
The output circuit OUT0 determines whether or not the number of bits having a specific logical value among the 8 bits included in the data generated by the internal circuit INT0 is larger than the number of bits having a logical value other than the specific logical value. A bit number comparison information generation unit 124 that generates the bit number comparison information shown may be further included. For example, the specific logical value is the logical value “1”.
[0025]
In the following description, when the specific logical value is the logical value “1”, the bit number comparison information is referred to as an internal HL bias determination signal IHLD. That is, whether the internal HL bias determination signal IHLD is greater in the number of bits having the logical value “1” than the number of bits having the logical value “0” among the 8 bits included in the data generated by the internal circuit INT0. It is a signal which shows.
[0026]
If the number of bits having the logical value “1” among the 8 bits included in the data generated by the internal circuit INT0 is greater than the number of bits having the logical value “0”, the level of the internal HL bias determination signal IHLD Becomes a high level ("H"). In other cases, the level of the internal HL deviation determination signal IHLD is low ("L"). The internal HL bias determination signal IHLD is supplied to the encoding unit 120 and the output unit 122.
[0027]
The encoding unit 120 is preferably configured to generate a smaller number of bit position information in accordance with the level of the internal HL bias determination signal IHLD. This is because such a configuration can reduce the number of times the bit position information is transferred from the semiconductor chip CHIP0 to the semiconductor chip CHIP1. For example, when the level of the internal HL bias determination signal IHLD is a low level (“L”), bit position information indicating the position of the bit having the logical value “1” is generated, and the level of the internal HL bias determination signal IHLD is generated. When the signal is at the high level (“H”), the bit position information indicating the position of the bit having the logical value “0” is generated, so that the encoding is performed regardless of the level of the internal HL bias determination signal IHLD. The number of bit position information generated by the unit 120 can be four or less.
[0028]
The output unit 122 outputs the internal HL deviation determination signal IHLD to the signal line 112 as the HL deviation determination signal HLD.
[0029]
The encoding unit 120 generates an internal data transfer control signal ITR for controlling the transfer of bit position information. The internal data transfer control signal ITR is supplied to the output unit 122. The output unit 122 outputs the internal data transfer control signal ITR to the signal line 114 as the data transfer control signal TR.
[0030]
The input unit 130 receives the bit position information from the bus 110, receives the HL bias determination signal HLD from the signal line 112, and receives the data transfer control signal TR from the signal line 114.
[0031]
The decoding unit 132 decodes the bit position information according to the level of the HL deviation determination signal HLD. For example, when the level of the HL bias determination signal HLD is low level (“L”), the decoding unit 132 interprets that the bit position information indicates the position of the bit having the logical value “1”, and Decode bit position information. When the level of the HL bias determination signal HLD is high (“H”), the decoding unit 132 interprets that the bit position information indicates the position of the bit having the logical value “0”, and the bit position. Decrypt information. Thus, the interpretation of the HL bias determination signal HLD needs to be negotiated in advance between the encoding unit 120 on the transmission side and the decoding unit 132 on the reception side.
[0032]
Further, instead of transferring 8-bit data, the transfer efficiency of data can be improved by transferring a 1-bit HL deviation determination signal HLD and 3-bit bit position information. Hereinafter, an example in which the data transfer efficiency is improved will be described. Here, bit pattern 10 to bit pattern 14 are defined as follows for 8-bit data.
[0033]
Bit pattern 10: Logical values of all bits included in data are “0” or “1”: 2 types
Bit pattern 11: 1-bit logical value included in data is “0” or “1”: 16 types
Bit pattern 12: 2-bit logical value included in data is “0” or “1”: 56 ways
Bit pattern 13: 3-bit logical value included in data is “0” or “1”: 112 types
Bit pattern 14: 4-bit logical value included in data is “0” or “1”: 70 types
In order to transfer the bit pattern 10 to the bit pattern 14, 1 cycle to 5 cycles are required. Under the condition that the occurrence probability of bit pattern 10 to bit pattern 14 is 40%, 50%, 6%, 3.9%, and 0.1%, respectively, a 4-bit data bus (ie, signal line 112 and bus) 110) is used to transfer data in an average of 1.74 cycles. This is equivalent to transferring data in one cycle using a 6.96 bit data bus. Therefore, compared with the case where data is transferred in one cycle using an 8-bit data bus, the data transfer efficiency for one bit or more of the data bus is improved.
[0034]
Note that when the logical values of all the bits included in the data generated by the internal circuit INT0 are “1” (or logical value “0”), the bit position information is not transferred. In this case, it is only necessary to transmit from the output circuit OUT0 to the input circuit IN1 that the bit position information is not transferred using the data transfer control signal TR. Whether the logical values of all bits are “1” or “0” can be determined using the HL bias determination signal HLD.
[0035]
At least one of the bus 110 for transferring the bit position information (DB00, DB01, DB02), the signal line 112 for transferring the HL bias determination signal HLD, and the signal line 114 for transferring the data transfer control signal TR. The part may be shared with the address bus line. By sharing the signal line between the semiconductor chip CHIP0 and the semiconductor chip CHIP1, the area necessary for providing the signal line can be reduced. As a result, the scale of the semiconductor device 100 can be reduced.
[0036]
In the example shown in FIG. 1, the number of bits of data generated by the internal circuit INT0 is 8, and the number of bits of bit position information transferred from the semiconductor chip CHIP0 to the semiconductor chip CHIP1 is 3. However, the application of the present invention is not limited to these numbers of bits. The internal circuit INT0 can generate data having an arbitrary number of bits. Also, bit position information having an arbitrary number of bits can be transferred from the semiconductor chip CHIP0 to the semiconductor chip CHIP1.
[0037]
FIG. 2 shows a configuration of the output circuit OUT0 of the semiconductor chip CHIP0 shown in FIG.
[0038]
The encoding unit 120 includes an output data holding circuit OREG, a jumpable shift register JREG, and encoding elements ENC00 to ENC07.
[0039]
The output unit 122 includes output buffers OBUF0, OBUF1, and OBUF2.
[0040]
The bit number comparison information generation unit 124 includes an HL deviation determination circuit COMP.
[0041]
The output circuit OUT0 receives 8-bit data output from the internal circuit INT0 of the semiconductor chip CHIP0. In FIG. 2, each bit of 8-bit data is expressed as IDB00 to IDB07. The 8-bit data is input to the output data holding circuit OREG and the HL deviation determination circuit COMP.
[0042]
The HL bias determination circuit COMP includes the number of bits having a logical value “1” (that is, “H” bits) and the bits having a logical value “0” (that is, “0”) among the 8 bits included in the input data. L ”bits). When the number of “H” bits is larger than the number of “L” bits, the HL bias determination circuit COMP outputs a high level (ie, “H”) internal HL bias determination signal IHDL. When the number of “L” bits is greater than the number of “H” bits, the HL bias determination circuit COMP outputs a low level (ie, “L”) internal HL bias determination signal IHDL.
[0043]
The output data holding circuit OREG latches the data output from the internal circuit INT0 at the timing when the internal data transfer control signal ITR becomes “H”, and holds the data.
[0044]
The internal data transfer control signal ITR is output from the jumpable shift register JREG. The timing at which the internal data transfer control signal ITR first becomes “H” is determined in response to the data latch signal TRR. The timing at which the internal data transfer control signal ITR subsequently becomes “H” is determined by the interleaving shift register JREG.
[0045]
When the output data holding circuit OREG receives the “H” internal HL deviation determination signal IHLD, the output data holding circuit OREG inverts the logical values of the bits IDB00 to IDB07 included in the data, and sets the bits having the inverted logical values as the bits ROUT00 to ROUT07. Output to the jumpable shift register JREG. On the other hand, when receiving the “L” internal HL deviation determination signal IHLD, the output data holding circuit OREG outputs the bits IDB00 to IDB07 included in the data as they are as bits ROUT00 to ROUT07 to the jumpable shift register JREG.
[0046]
Therefore, when the number of “H” bits among the bits IDB00 to IDB07 included in the data is large, the “H” bit is inverted and output to the “L” bit, and the “L” bit is “ Inverted to H ”bit and output. When the number of “L” bits among the bits IDB00 to IDB07 included in the data is large, such inversion operation is not performed.
[0047]
The interleaving shift register JREG receives the bits ROUT00 to ROUT07 output from the output data holding circuit OREG, and sequentially selects the “H” bits of the bits ROUT00 to ROUT07 in synchronization with the clock signal CLK. The selection signal corresponding to the selected bit is set to “H”.
[0048]
For example, when only the bit ROUT00 among the bits ROUT00 to ROUT07 is “H”, the interleaving shift register JREG sets the selection signal REG00 corresponding to the bit ROUT00 to “H”.
[0049]
Further, for example, when only the bits ROUT01 and ROUT02 of the bits ROUT00 to ROUT07 are “H”, the interleaving shift register JREG synchronizes the selection signals REG01 and REG02 corresponding to the bits ROUT01 and ROUT02 with the clock signal CLK. To “H” sequentially.
[0050]
Each of the encoding elements ENC00 to ENC07 outputs a 3-bit position signal indicating the position of its own encoding element in response to a corresponding one of the selection signals REG00 to REG07. That is, when the selection signal REG0k is “H”, the encoding element ENC0k outputs a 3-bit position signal Sk indicating its position to the output buffer OBUF0. Here, k is an integer of 0-7.
[0051]
This position signal indicates the position of the encoding element to which the “H” selection signal is input. Therefore, this position signal indicates the position of the “H” bit among the bits ROUT00 to ROUT07. The position of the “H” bit in the bits ROUT00 to ROUT07 is included in the data when the number of “H” bits in the bits IDB00 to IDB07 included in the data is greater than the number of “L” bits. L indicates the position of the bit, and otherwise indicates the position of the “H” bit included in the data.
[0052]
When a 3-bit position signal is output from any one of the encoding elements ENC00 to ENC07, the position signal is temporarily stored in the output buffer OBUF0. After the falling edge of the internal data transfer control signal ITR, the position signal stored in the buffer OBUF0 is output as bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK.
[0053]
When a plurality of position signals are sequentially input to the output buffer OBUF0, the plurality of position signals are sequentially output as a plurality of bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK. Is done.
[0054]
The internal HL bias determination signal IHLD is output as the HL bias determination signal HLD via the output buffer OBUF1. Internal data transfer control signal ITR is output as data transfer control signal TR via output buffer OBUF2.
[0055]
In this way, the bit position information (DB00, DB01, DB02), the data transfer control signal TR, and the HL bias determination signal HLD output from the output circuit OUT0 of the semiconductor chip CHIP0 are transferred to the semiconductor chip CHIP1.
[0056]
In the present embodiment, 8-bit data is encoded into 3-bit bit position information (DB00, DB01, DB02), and the bit position information (DB00, DB01, DB02) is transmitted to the semiconductor chip via the bus 110. The data is transferred from CHIP0 to the semiconductor chip CHIP1. The bit position information is information indicating the position of the “H” (or “L”) bit in the 8-bit data. Here, when information indicating the position of the “H” bit among the 8-bit data is transferred as the bit position information, the information indicating the position of the “L” bit is not transferred. Conversely, when information indicating the position of the “L” bit among the 8-bit data is transferred as the bit position information, the information indicating the position of the “H” bit is not transferred. This is because the position of the “L” (or “H”) bit is determined as long as the information indicating the position of the “H” (or “L”) bit is transferred.
[0057]
Further, it is detected whether the number of “H” bits or the number of “L” bits among the bits included in the data is larger, and the number of “H” bits and “L” are determined according to the detection result. The number of times of transferring the bit position information can be reduced by transferring the information indicating the position of the smaller bit out of the number of "" as the bit position information. As a result, the amount of data transferred between the semiconductor chip CHIP0 and the semiconductor chip CHIP1 can be reduced.
[0058]
FIG. 3 shows a configuration of the HL deviation determination circuit COMP shown in FIG. In FIG. 3, INP is an input voltage generation circuit, COM is a current mirror type comparison circuit, REF is a reference voltage generation circuit, VDD is a first power supply, MP is a PMOS transistor, MN1 to MN4 are NMOS transistors, and / CS is Chip select signal.
[0059]
The input voltage generation circuit INP includes one PMOS transistor MP and eight NMOS transistors MN1. Bits IDB00 to IDB07 of data from the internal circuit INT0 of the semiconductor chip CHIP0 are applied to the gates of the NMOS transistors MN1. In response to the “H” bit, the NMOS transistor MN1 is turned on. As the number of NMOS transistors MN1 that are turned on among the eight NMOS transistors MN1 increases, the gate voltage of the NMOS transistor MN2 of the comparison circuit COM decreases.
[0060]
The reference voltage generation circuit REF includes one PMOS transistor MP and one NMOS transistor MN3. A constant voltage is applied to the gate of the NMOS transistor MN3. A constant voltage is also applied to the gate of the NMOS transistor MN4 of the comparison circuit COM.
[0061]
When comparing each NMOS transistor MN1 in the input voltage generation circuit INP with the NMOS transistor MN3 in the reference voltage generation circuit REF, the amount of current flowing through the NMOS transistor MN3 is 4.5 of the amount of current flowing through the NMOS transistor MN1. It is equivalent to twice. For this reason, when four or less of the NMOS transistors MN1 in the input voltage generation circuit INP are on, the current flowing through the NMOS transistor MN3 in the reference voltage generation circuit REF is greater in the input voltage generation circuit INP. It is larger than the current flowing through each of the four or less NMOS transistors MN1, and in the comparison circuit COM, the gate voltage of the NMOS transistor MN4 is lower than the gate voltage of the NMOS transistor MN2. When five or more of the NMOS transistors MN1 in the input voltage generation circuit INP are on, the current flowing through the NMOS transistor MN3 in the reference voltage generation circuit REF is 5% in the input voltage generation circuit INP. In comparison circuit COM, the gate voltage of NMOS type transistor MN4 becomes higher than the gate voltage of NMOS type transistor MN2.
[0062]
In such a configuration, when the chip select signal / CS becomes “L”, each PMOS transistor MP is turned on, and the HL bias determination circuit COMP is activated. In this state, when four or less of the bits IDB00 to IDB07 of the data from the internal circuit INT0 of the semiconductor chip CHIP0 become “H”, four or less of the NMOS transistors MN1 in the input voltage generation circuit INP Turn on. As a result, in the comparison circuit COM, the gate voltage of the NMOS transistor MN4 is lower than the gate voltage of the NMOS transistor MN2. In response to this, the comparison circuit COM outputs an internal HL deviation determination signal IHLD indicating “L”.
[0063]
When five or more of the bits IDB00 to IDB07 of the data from the internal circuit INT0 of the semiconductor chip CHIP0 become “H”, five or more of the NMOS transistors MN1 in the input voltage generation circuit INP are turned on. Become. As a result, in the comparison circuit COM, the gate voltage of the NMOS transistor MN4 becomes higher than the gate voltage of the NMOS transistor MN2. In response to this, the comparison circuit COM outputs an “H” internal HL deviation determination signal IHLD.
[0064]
Thus, the HL deviation determination circuit COMP compares the number of “H” bits included in the data output from the internal circuit INT0 with the number of “L” bits, and the number of “H” bits is determined. When the number of “L” bits is larger, the “H” internal HL bias judgment signal IHLD is output, and when the number of “H” bits is smaller than the number of “L” bits, “ The L "internal HL deviation determination signal IHLD is output.
[0065]
FIG. 4 shows a partial configuration of the output data holding circuit OREG shown in FIG. The circuit shown in FIG. 4 is provided to correspond to 1-bit IDB00 of data input to the output data holding circuit OREG. Circuits similar to those shown in FIG. 4 are provided so as to correspond to the other 7 bits input to the output data holding circuit OREG. Therefore, the output data holding circuit OREG is provided with eight circuits shown in FIG.
[0066]
In FIG. 4, INV is an inverter circuit, and CINV1 to CINV4 are clock control type inverter circuits.
[0067]
When the internal data transfer control signal ITR becomes “H” in a state where the internal HL bias determination signal IHLD indicates “H”, the 1-bit IDB00 of the data is converted into the clock control type inverter circuit CINV1 → the inverter circuit INV → the clock control type inverter. The signal is transmitted through the path of the circuit CINV3, inverted, and output as the bit ROUT00.
[0068]
When the internal data transfer control signal ITR becomes “H” in the state where the internal HL deviation determination signal IHLD indicates “L”, the 1-bit IDB00 of the data is inverted via the clock control type inverter circuits CINV1 and CINV4. Without being output as bit ROUT00.
[0069]
As described above, when the internal HL bias determination signal IHLD is “H”, the output data holding circuit OREG inverts the logical values of the bits IDB00 to IDB07 included in the data, and has the inverted logical value. Are output as bits ROUT00 to ROUT07, and when the internal HL deviation determination signal IHLD is “L”, the bits IDB00 to IDB07 included in the data are output as bits ROUT00 to ROUT07 as they are.
[0070]
FIG. 5 shows a configuration of the interlaceable shift register JREG shown in FIG. In FIG. 5, JREGC, JREGC00 to JREGC07 are circuits per stage of the jumpable shift register JREG, NAND is a two-input NAND circuit, NOR is a two-input NOR circuit, INV is an inverter circuit, CINV is a clock-controlled inverter circuit, REG00 to REG00 REG07 is an output of the circuits JREGC00 to JREGC07. REG00 to REG07 are not shown for simplicity.
[0071]
The interleaving shift register JREG includes circuits JREGC00 to JREGC07 and a circuit JREGC. These circuits are connected in series. The circuits JREGC00 to JREGC07 are provided so as to correspond to the bits ROUT00 to ROUT07 output from the output data holding circuit OREG, respectively. The first circuit JREGC of the interleaving shift register JREG is provided as a dummy. In the first stage circuit JREGC, an “H” signal (voltage VDD) is always input instead of the bit from the output data holding circuit OREG. When the internal data transfer control signal ITR becomes “H”, a bit “H” is given to the second and subsequent circuits JREGC00 to JREGC07, so that the second and subsequent circuits JREGC00 to JREGC07 from the next rising edge of the clock signal CLK. Output operation becomes possible.
[0072]
The internal data transfer control signal ITR first becomes “H” in synchronization with the data latch signal TRR, and thereafter becomes “H” in response to a bit from the circuit JREGC07 at the final stage. When the data latch signal TRR first becomes “H”, the NMOS transistor MN11 is turned on. As a result, the internal data transfer control signal ITR becomes “H”. Thereafter, the PMOS transistor MP11 is turned on each time a “H” bit is output from the final-stage circuit JREGC07. As a result, the internal data transfer control signal ITR becomes “H”.
[0073]
When the “H” bit is output from the first-stage circuit JREGC, the next-stage circuit JREGC00 inputs the “H” bit to the NAND circuit NAND and the NMOS transistor MN12. As a result, the NMOS transistor MN12 is turned on. The NAND circuit NAND receives the “H” bit and the bit ROUT00 from the output data holding circuit OREG. As a result, when the bit ROUT00 is “H”, the NAND circuit NAND outputs an “L” bit. In response to this, the “H” selection signal REG00 is output from the NOR circuit NOR11 at the next rise of the clock signal CLK. At the same time, the “H” bit is also output from the NOR circuit NOR12, and the “H” bit is output to the subsequent circuit JREGC01 via the NMOS transistor MN12.
[0074]
When the bit ROUT00 is “L”, a “H” bit is output from the NAND circuit NAND, and in response thereto, the “L” selection signal REG00 at the next rising edge of the clock signal CLK. Is output from the NOR circuit NOR11.
[0075]
On the other hand, when the bit ROUT00 is “L”, the NMOS transistor MN12 is turned off, so that the “L” bit from the NOR circuit NOR12 is not output to the subsequent circuit JREGC02. Instead, since the PMOS transistor MP22 is turned on, the “H” bit from the first stage circuit JREGC is output to the subsequent circuit JREGC02 via the PMOS transistor MP22. However, the transmission of the “H” bit from the initial stage circuit JREGC to the subsequent stage circuit JREGC02 at this time is performed immediately without waiting for the rising edge of the clock signal CLK.
[0076]
Similarly, in any of the circuits JREGC01 to JREGC07, if the “H” bit ROUT is input from the output data holding circuit OREG, the next to the clock signal CLK after the “H” bit is input from the preceding circuit JREGC. At the rising edge, the “H” selection signal REG is output, and at the same time, the “H” bit is output to the circuit JREGC at the subsequent stage. Further, when the “L” bit ROUT is input from the output data holding circuit OREG, the “H” bit is immediately transmitted from the preceding stage to the subsequent circuit JREGC, and at the next rising edge of the clock signal CLK thereafter, “ The L "bit REG is output.
[0077]
As described above, when the bits ROUT00 to ROUT07 are input from the output data holding circuit OREG, the interleaving shift register JREG sequentially selects the “H” bits of the bits ROUT00 to ROUT07 in synchronization with the clock signal CLK. The selection signal REG corresponding to the selected bit is set to “H”.
[0078]
6A to 6H show circuit configurations of the encoding elements ENC00 to ENC07 shown in FIG. 6A to 6H, MN31 to MN33 denote NMOS transistors.
[0079]
For each of the encoding elements ENC00 to ENC07, either the ground potential or the power supply potential is selectively applied to the input sides of the three NMOS transistors MN31 to MN33, and the potentials on the input sides of the three NMOS transistors MN31 to MN33 are changed. The combination is different. For example, in the encoding element ENC00 shown in FIG. 6A, the ground potential is applied to all the input sides of the three NMOS transistors MN31 to MN33. In the encode element ENC05 shown in FIG. 6F, the ground potential is applied to the input sides of the two NMOS transistors MN31 and MN33, and the power supply potential is applied to the input side of the one NMOS transistor MN32. .
[0080]
In any of the encoding elements ENC00 to ENC07, when the “H” selection signal REG from the interlaceable shift register JREG is input to the gates of the three NMOS transistors MN31 to MN33, these NMOS transistors MN31 to MN33 are turned on. Each potential on the input side of these NMOS transistors MN31 to MN33 is output as a 3-bit position signal.
[0081]
Thus, each of the encoding elements ENC00 to ENC07 outputs a 3-bit position signal indicating the position of its own encoding element when the corresponding selection signal among the selection signals REG00 to REG07 becomes “H”.
[0082]
With such a configuration, the bit position information indicating the position of the smaller number of the “H” bits and “L” bits included in the 8-bit data is output and indicated by the bit position information. It is possible to output an HL bias determination signal HLD indicating whether the position of the bit to be read is the position of the “H” bit or the “L” bit.
[0083]
FIG. 7 shows a configuration of the input circuit IN1 shown in FIG. The input circuit IN1 decodes the 3-bit bit position information (DB00, DB01, DB02) input to the semiconductor chip CHIP1 into 8-bit data, and transfers the 8-bit data to the internal circuit INT1.
[0084]
The input circuit IN1 includes an input unit 130 and a decoding unit 132 (see FIG. 1).
[0085]
Input unit 130 includes input buffers IBUF0, IBUF1, and IBUF2.
[0086]
Decoding unit 132 includes an input data holding circuit IREG and decoding elements DEC10 to DEC17.
[0087]
The 3-bit bit position information (DB00, DB01, DB02) transferred from the output circuit OUT0 of the semiconductor chip CHIP0 via the bus 110 is input to the decoding elements DEC10 to DEC17 via the input buffer IBUF0. Each time 3-bit bit position information (DB00, DB01, DB02) is input, the bit position information (DB00, DB01, DB02) is decoded by one of the decoding elements DEC10 to DEC17. As a result, one of the bits INDEC10 to INDEC17 becomes “H” and is input to the input data holding circuit IREG. Here, INDEC10 to INDEC17 indicate bits output from the decoding elements DEC10 to DEC17, respectively.
[0088]
The HL bias determination signal HLD transferred from the output circuit OUT0 of the semiconductor chip CHIP0 via the signal line 112 is input to the input buffer IBUF1, and is output to the input data holding circuit IREG as the internal HL bias determination signal IHLD.
[0089]
The data transfer control signal TR transferred from the output circuit OUT0 of the semiconductor chip CHIP0 via the signal line 114 is input to the input buffer IBUF2, and is output to the input data holding circuit IREG as the internal data transfer control signal TRD.
[0090]
When the “H” internal HL bias determination signal IHLD is input (that is, when the logical value of each bit of data is inverted and transferred from the semiconductor chip CHIP0), the input data holding circuit IREG decodes Bits IDB10 to IDB17 having the same logical value as the original data are generated by inverting the logical values of the bits INDEC10 to INDEC17 output from the elements DEC10 to DEC17. Bits IDB10 to IDB17 are output to the internal circuit INT1 of the semiconductor chip CHIP1.
[0091]
When the “L” internal HL bias determination signal IHLD is input (that is, when each bit of data is transferred as it is from the semiconductor chip CHIP0), the input data holding circuit IREG receives from the decoding elements DEC10 to DEC17. The bits INDEC10 to INDEC17 are output as bits IDB10 to IDB17 without inverting the logical values of the output bits INDEC10 to INDEC17. Thereby, bits IDB10 to IDB17 having the same logical value as the original data are obtained. Bits IDB10 to IDB17 are output to the internal circuit INT1 of the semiconductor chip CHIP1.
[0092]
The input data holding circuit IREG is reset in response to a period during which the internal data transfer control signal TRD is at a high level. Thereafter, the input data holding circuit IREG operates in response to the bits INDEC10 to INDEC17 output from the decoding elements DEC10 to DEC17.
[0093]
In order to match the input timing of the internal data transfer control signal TRD to the input data holding circuit IREG with the input timing of the bits INDEC10 to INDEC17 from the decoding elements DEC10 to DEC17, the input buffer IBUF2 has a predetermined data transfer control signal TR. Used to delay by the specified delay time. The delayed data transfer control signal TR is output as the internal data transfer control signal TRD.
[0094]
The latching of the bits IDB10 to IDB17 from the input data holding circuit IREG to the internal circuit INT1 of the semiconductor chip CHIP1 is performed at the reset timing of the input data holding circuit IREG by the internal data transfer control signal TRD.
[0095]
As described above, the input circuit IN1 of the semiconductor chip CHIP1 receives the bit position information (position signals DB00, DB01, DB02) every time 3-bit bit position information (DB00, DB01, DB02) is input from the semiconductor chip CHIP0. ) Is decoded by any one of the decoding elements DEC10 to DEC17, and bits INDEC10 to INDEC17 are generated, and the logical values of the bits INDEC10 to INDEC17 are inverted or not inverted according to the internal HL bias determination signal IHLD. Bits IDB10 to IDB17 having the same logical value as that of the data are generated.
[0096]
8A to 8H show circuit configurations of the decoding elements DEC10 to DEC17 shown in FIG.
[0097]
For example, the decode element DEC10 in FIG. 8A includes three inverter circuits INV0, a NAND circuit NAND, and an inverter circuit INV1, and corresponds to the encode element ENC00 in FIG. When the 3-bit bit position information (DB00, DB01, DB02) generated by the encoding element ENC00 of FIG. 6A is input, the decoding element DEC10 of FIG. The bit INDEC10 of H ”is output.
[0098]
8B includes two inverter circuits INV0, a NAND circuit NAND, and an inverter circuit INV1, and corresponds to the encode element ENC01 in FIG. 6B. When the 3-bit bit position information (DB00, DB01, DB02) generated by the encoding element ENC01 of FIG. 6B is input, the decoding element DEC11 of FIG. The bit INDEC11 of H ”is output.
[0099]
In this manner, the decoding elements DEC10 to DEC17 convert the 3-bit bit position information into 8-bit data.
[0100]
FIG. 9 shows a partial configuration of the input data holding circuit IREG shown in FIG. In FIG. 9, NOR is a NOR circuit, CINV is an inverter controlled by a clock, and INV is an inverter.
[0101]
The circuit shown in FIG. 9 is provided so as to correspond to the bit INDEC10 output from the decoding element DEC10. Circuits similar to those shown in FIG. 9 are provided so as to correspond to the bits INDEC11 to INDEC17 output from the other decoding elements DEC11 to DEC17, respectively. Accordingly, the input data holding circuit IREG is provided with eight circuits shown in FIG.
[0102]
The circuit shown in FIG. 9 is reset at the rising edge of the internal data transfer control signal TRD, and outputs the bit IDB10 of “L”. In a state where the “L” internal HL bias determination signal IHLD is input, when the “L” bit INDEC10 is input from the decoding element DEC10, the “L” bit IDB10 is output as it is, and the decoding element DEC10 outputs the same. When the “H” bit INDEC 10 is input, the logical value of the bit IDB 10 is inverted, and the “H” bit IDB 10 is output.
[0103]
When the circuit shown in FIG. 9 is reset at the rising edge of the internal data transfer control signal TRD, if the internal HL deviation determination signal IHLD of “H” is being input, the internal data transfer control signal TRD In response to the falling edge, the logic value of the bit IDB10 is inverted, and the bit IDB10 of “H” is output. When the “L” bit INDEC10 is input from the decoding element DEC10, the “H” bit IDB10 is output as it is, and when the “H” bit INDEC10 is input from the decoding element DEC10, the logical value of the bit IDB10 is output. Are inverted, and the bit IDB10 of "L" is output.
[0104]
Such an operation is performed for each of the bits INDEC10 to INDEC17 output from the decoding elements DEC10 to DEC17. As a result, bits INDEC10 to INDEC17 are output from the input data holding circuit IREG.
[0105]
In the circuit of FIG. 9, the bias determination signal IHLD is used to control whether the bit INDEC10 input to the data input terminal is forwardly output to the output terminal IDB10 or output after being inverted.
[0106]
Specifically, when the bias determination signal IHLD is “H”, the bit INDEC10 input to the data input terminal is input via the inverter CINV5, and when the bias determination signal IHLD is “L”. The bit INDEC10 input to the data input terminal is input via the two-stage inverters of the inverter INV4 and the inverter CINV3.
[0107]
When the data appearing at the node A is “H”, the inverters CINV2 and CINV8 are activated and the inverters CINV6 and CINV7 are deactivated. As a result, the internal data transfer control signal TRD becomes “H”, and after resetting, the bit IDB10 becomes “H”.
[0108]
When the data appearing at the node A is “L”, the inverters CINV2 and CINV8 are inactivated, and the inverters CINV6 and CINV7 are activated. As a result, the internal data transfer control signal TRD becomes “H”, and after resetting, the bit IDB 10 becomes “L”.
[0109]
FIG. 10 is a timing chart showing operations of the output circuit OUT0 of the semiconductor chip CHIP0 and the input circuit IN1 of the semiconductor chip CHIP1.
[0110]
In the semiconductor chip CHIP0, when the internal data transfer control signal ITR becomes “H”, the bits ROUT00 to ROUT07 are output from the output data holding circuit OREG and selected in synchronization with the clock signal CLK from the next rising edge of the clock signal CLK. Among the signals REG00 to REG07, an “H” selection signal is sequentially output from the interleaving shift register JREG. Each time an “H” selection signal is output from the interlaceable shift register JREG, 3-bit bit position information (DB00, DB01, DB02) is transmitted.
[0111]
In the semiconductor chip CHIP1, the internal data transfer control signal TRD is generated by delaying the data transfer control signal TR. When the internal data transfer control signal TRD becomes “L”, every time 3-bit bit position information (DB00, DB01, DB02) is input, the “H” bit of the bits INDEC10 to INDEC17 is changed to the input data holding circuit IREG. Are sequentially input. The input data holding circuit IREG continues to output bits IDB10 to IDB17 having the same logical value as the original data until the internal data transfer control signal TRD becomes “H”.
[0112]
In FIG. 10, some time elapses before the bits INDEC10 to INDEC17 appear after the falling edge of the internal data transfer control signal TRD. This is because, when the “H” internal HL bias determination signal IHLD is input (that is, when the number of “H” bits among the bits included in the data is greater than the number of “L” bits), the internal This is because, after the bits INDEC10 to INDEC17 output from the decoding elements DEC10 to DEC17 are reset to “L” at the rising edge of the data transfer control signal TRD, the bits IDB10 to IDB17 are simultaneously rewritten to “H”. When the data includes many “H” bits, only information indicating the position of the “L” bit is transferred, and information indicating the position of the “H” bit is not transferred. By using the timing described above, the input data holding circuit IREG shown in FIG. 9 operates well.
[0113]
In FIG. 10, the third data transfer period is a period in which all “L” data (that is, data in which the logical values of all bits are “0”) is transferred. In the third data transfer period, the HL deviation determination signal HLD and the data transfer control signal TR are output from the semiconductor chip CHIP0 on the transmission side, but no bit position information is output. The bit position information is in the state of UNKNOWN. In this state, in the receiving-side semiconductor chip CHIP1, all data in the input data holding circuit IREG is reset in response to the internal data transfer control signal TRD. As a result, the bits IDB10 to IDB17 output from the input data holding circuit IREG are all “L”. In response to the input of the next data transfer control signal TR, the data of the input data holding circuit IREG is reset again. Simultaneously with this reset, the data of the input data holding circuit IREG is latched in the internal circuit INT1. As a result, all “L” data is transferred. The same applies when all “H” data is transferred. However, in this case, it is necessary to take a timing margin from when the HL deviation determination signal HLD is received until the bits IDB10 to IDB17 all become “H” until the next data transfer control signal TR is input.
[0114]
In the first embodiment, when all the bits IDB00 to IDB07 included in the data are “L”, only the reset operation by the data transfer control signal TR is performed without transferring the bit position information. That is, since the “L” internal HL bias determination signal IHLD is input to the input data holding circuit IREG, the input data holding circuit IREG sets the “L” bits IDB00 to IDB07 after reset by the data transfer control signal TR. Output as is.
[0115]
When all the bits IDB00 to IDB07 included in the data are “H”, the “H” internal HL deviation determination signal IHLD is input to the input data holding circuit IREG, so that the input data holding circuit IREG After resetting by the transfer control signal TR, the logic values of the bits IDB00 to IDB07 are inverted all at once, thereby outputting the “H” bits IDB00 to IDB07.
[0116]
As is clear from the above description, in the semiconductor device of the first embodiment, 8-bit data is encoded into 3-bit bit position information. This 3-bit bit position information is transferred via the bus. Then, the 3-bit bit position information is decoded into 8-bit data. For this reason, the number of signal lines required to transfer data can be reduced.
[0117]
Further, the number of “H” bits and the number of “L” bits are compared, and information indicating the position of the smaller bit is transferred together with the HL bias determination signal HLD according to the comparison result. Therefore, efficient data transfer becomes possible.
[0118]
The circuits in FIGS. 2 to 9 are merely examples, and various modifications can be made. Alternatively, a circuit having a similar function may be applied instead of these circuits.
[0119]
(Embodiment 2)
FIG. 11 shows the configuration of the semiconductor device 200 according to the second embodiment of the present invention. The semiconductor device 200 provides an advantage that a signal line line for transferring the HL deviation determination signal HLD between the semiconductor chip CHIP2 and the semiconductor CHIP3 is unnecessary. This reduces the area required to provide the signal line. As a result, the scale of the semiconductor device 200 is reduced.
[0120]
In the semiconductor device 200, the logical value of each bit of the data transferred this time is compared with the logical value of each bit of the data transferred last time. As a result, a bit having a logical value changed compared to the previously transferred data is selected, and information indicating the position of the selected bit is transferred.
[0121]
The semiconductor device 200 includes a semiconductor chip CHIP2 and a semiconductor chip CHIP3. The semiconductor chip CHIP2 and the semiconductor chip CHIP3 are connected to each other via the bus 210. Bus 210 includes signal lines 210a, 210b and 210c. The width of the bus 210 is 3 bits. The 3-bit bit position information (DB00, DB01, DB02) is transferred from the semiconductor chip CHIP2 to the semiconductor chip CHIP3 via the bus 210.
[0122]
The semiconductor chip CHIP2 includes an internal circuit INT2 and an output circuit OUT2. The internal circuit INT2 generates 8-bit data. The output circuit OUT2 includes an encoding unit 220 that generates bit position information by encoding 8-bit data generated by the internal circuit INT2, and an output unit 222 that outputs the bit position information to the bus 210. . Thus, the semiconductor chip CHIP2 functions as a transmission unit that transmits data.
[0123]
The semiconductor chip CHIP3 includes an input circuit IN3 and an internal circuit INT3. The input circuit IN3 includes an input unit 230 that receives bit position information from the bus 210, and a decoding unit 232 that generates 8-bit data by decoding the bit position information. The 8-bit data generated by the input circuit IN3 is output to the internal circuit INT3. Thus, the semiconductor chip CHIP3 functions as a receiving unit that receives data.
[0124]
The bit position information indicates the position of a bit having a logical value that has changed compared to the previously transferred data. For example, the previously transferred 8-bit data is (0, 1, 0, 1, 0, 0, 1, 0), and the 8-bit data to be transferred this time is (0, 1, 0, 1, Suppose the case of (1, 0, 1, 0). In this case, the position of the bit whose logical value has changed is represented by (1, 0, 0). Accordingly, the encoding unit 220 generates bit position information (1, 0, 0), and the output unit 222 outputs this bit position information to the bus 210.
[0125]
The 8-bit data to be transferred this time is generated by the internal circuit INT2 and provided to the output circuit OUT2. The previously transferred 8-bit data is held in the encoding unit 220 of the output circuit OUT2.
[0126]
The encoding unit 220 generates an internal data transfer control signal ITR for controlling the transfer of bit position information. The internal data transfer control signal ITR is supplied to the output unit 222. The output unit 222 outputs the internal data transfer control signal ITR to the signal line 214 as the data transfer control signal TR.
[0127]
In this way, instead of transferring 8-bit data, information indicating the position of a bit having a logical value changed compared to the previously transferred data among the 8 bits included in the data (that is, bit position information) ) Is transferred, it is possible to transfer data using a bus having a bit width smaller than the bit width of the transferred data. Thereby, the width of the bus can be reduced as compared with the conventional one. As a result, the scale of the semiconductor device 200 can be reduced.
[0128]
In addition, the transfer efficiency of data can be improved by transferring the bit position information of 3 bits instead of transferring the data of 8 bits. Hereinafter, an example in which the data transfer efficiency is improved will be described. Here, the bit pattern 20 to the bit pattern 28 are defined as follows for 8-bit data.
[0129]
Bit pattern 20: 0 bit changes compared to previously transferred data: 1 way
Bit pattern 21: 1 bit changes compared to previously transferred data: 8 ways
Bit pattern 22: 2 bits change compared to previously transferred data: 28 ways
Bit pattern 23: 3 bits change compared to previously transferred data: 56 ways
Bit pattern 24: 4 bits change compared to previously transferred data: 70 ways
Bit pattern 25: 5 bits change compared to previously transferred data: 56 ways
Bit pattern 26: 6 bits change compared to previously transferred data: 28 ways
Bit pattern 27: 7 bits change compared to previously transferred data: 8 ways
Bit pattern 28: 8 bits change compared to previously transferred data: 1 way
In order to transfer the bit pattern 20 to the bit pattern 28, 1 cycle to 9 cycles are required, respectively. Appearance probabilities of bit pattern 20 to bit pattern 28 are 50%, 40%, 8%, 1.5%, 0.4%, 0.08%, 0.015%, 0.004%, and 0.001%, respectively. In this condition, data is transferred in an average of 1.63 cycles using a 3-bit data bus (that is, the bus 210). This is equivalent to transferring data in one cycle using a 4.89 bit data bus. Therefore, the data transfer efficiency is improved by 3 bits or more of the data bus as compared with the case where data is transferred in one cycle using the 8-bit data bus.
[0130]
FIG. 12 shows a configuration of the output circuit OUT2 shown in FIG. The configuration of the output circuit OUT2 shown in FIG. 12 is that the HL deviation determination circuit COMP and the output buffer OBUF1 are deleted, the previous data holding circuit BDREG for holding each bit of the previously transferred data, and the current time 2 is different from the configuration of the output circuit OUT0 shown in FIG. 2 in that an exclusive OR circuit XOR for comparing each bit of transferred data and each bit of previously transferred data is added. Yes.
[0131]
In FIG. 12, the same reference numerals are given to the constituent elements having the same functions as those of the output circuit OUT2 shown in FIG.
[0132]
In the output circuit OUT2 of FIG. 12, first, the previous data holding circuit BDREG and the output data holding circuit OREG1 are initialized by the reset signal RESET. As a result, each bit of data held in the previous data holding circuit BDREG and each bit of data held in the output data holding circuit OREG1 are initialized to “L”.
[0133]
Next, the data generated by the internal circuit INT of the semiconductor chip CHIP2 is input and held in the output data holding circuit OREG1. The exclusive OR circuit XOR compares each bit of data held in the previous data holding circuit BDREG with each bit corresponding to the bits held in the output data holding circuit OREG1 in the order of the bit arrangement. As a result of the comparison, when the logical value of the bit held in the output data holding circuit OREG1 is different from the logical value of the bit held in the previous data holding circuit BDREG, the exclusive OR circuit XOR The bit corresponding to the bit changed to “H” is set to “H”, and this bit is output to the jumpable shift register JREG. The bits output from the exclusive OR circuit XOR are expressed as bits ROUT00 to ROUT07.
[0134]
The interlaceable shift register JREG sequentially selects “H” bits among the bits ROUT00 to ROUT07 in synchronization with the clock signal CLK, and sets the selection signal corresponding to the selected bits to “H”.
[0135]
The previous data holding circuit BDREG updates the data held in the previous data holding circuit BDREG by inverting the logical value of the bit corresponding to the “H” selection signal among the selection signals REGC00 to 07. In this way, the data held in the previous data holding circuit BDREG is sequentially updated.
[0136]
Each of the encoding elements ENC00 to ENC07 outputs a 3-bit position signal indicating the position of its own encoding element in response to the corresponding selection signal of the selection signals REG00 to REG07 becoming “H”.
[0137]
The 3-bit position signal output from any of the encoding elements ENC00 to ENC07 is temporarily stored in the output buffer OBUF0. Thereafter, the 3-bit position signal stored in the output buffer OBUF0 is sent to the bus 210 as bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK after the falling edge of the internal data transfer control signal ITR. Is output.
[0138]
When a plurality of position signals are stored in the output buffer OBUF0, the plurality of position signals are sequentially output as a plurality of bit position information (DB00, DB01, DB02) in synchronization with the clock signal CLK.
[0139]
FIG. 13 shows a partial configuration of the output data holding circuit OREG1 shown in FIG. The circuit shown in FIG. 13 is provided to correspond to 1-bit IDB00 of data input to the output data holding circuit OREG1. A circuit similar to the circuit shown in FIG. 13 is provided to correspond to the other seven bits input to the output data holding circuit OREG1. Therefore, eight circuits shown in FIG. 13 are provided in the output data holding circuit OREG1.
[0140]
In the circuit shown in FIG. 13, when the data control signal ITR becomes “H”, the clock control type inverter circuit CINV1 is turned on. As a result, 1-bit IDB00 of data is output as bit ROUT00 via the clock-controlled inverter circuit CINV1 and the inverter circuit INV1.
[0141]
FIG. 14 shows a partial configuration of the previous data holding circuit BDREG shown in FIG. The circuit shown in FIG. 14 is provided so as to correspond to the selection signal REGC00 input to the previous data holding circuit BDREG. Circuits similar to those shown in FIG. 14 are provided to correspond to the other seven selection signals input to the previous data holding circuit BDREG. Accordingly, the previous data holding circuit BDREG is provided with eight circuits shown in FIG.
[0142]
In the circuit shown in FIG. 14, when the reset signal RESET becomes “H”, the output of the NOR circuit NOR1 becomes “L”. At this time, if the “L” selection signal REG00 is input, the inverter circuits CINV6 and CINV7 are turned on. As a result, the output from the NOR circuit NOR1 (that is, the bit ROUT00) continues to be held at “L”.
[0143]
When the selection signal REG00 is inverted to become “H”, the inverter circuits CINV6 and CINV7 are turned off, and the inverter circuits CINV2 and CINV8 are turned on. At this time, the output of the NOR circuit NOR2 is “L”. When the output of the NOR circuit NOR2 is input to the NOR circuit NOR1 via the inverter INV1 and the inverter circuit CINV2, the output of the NOR circuit NOR1 is inverted. As a result, the bit ROUT00 becomes “H”. Even if the selection signal REG00 is inverted again and returns to "L", the bit IDB10 is kept at "H". However, the inverter circuits CINV6 and CINV7 are turned on, and the output of the NOR circuit NOR2 becomes “H”.
[0144]
Further, when the selection signal REG00 is further inverted again to become “H” and the respective inverter circuits CINV2 and CINV8 are turned on, the output of the NOR circuit NOR2 is “H”, so that the output of the NOR circuit NOR1 is inverted. . As a result, the bit ROUT00 becomes “L”.
[0145]
FIG. 15 shows a configuration of the input circuit IN3 shown in FIG.
[0146]
The input circuit IN3 decodes the 3-bit bit position information (DB00, DB01, DB02) input to the semiconductor chip CHIP3 into 8-bit data, and outputs the 8-bit data to the internal circuit INT3.
[0147]
The configuration of the input circuit IN3 is substantially the same as the configuration of the input circuit IN1 shown in FIG. However, both configurations differ in that the output buffer OBUF1 is deleted and in the configuration of the input data holding circuit IREG1.
[0148]
In FIG. 15, the same reference numerals are given to the constituent elements that perform the same functions as those of the input circuit IN1 shown in FIG.
[0149]
In the input circuit IN3, first, the input data holding circuit IREG1 is initialized by the reset signal RESET. As a result, each bit of data held in the input data holding circuit IREG1 is initialized to “L”.
[0150]
The 3-bit bit position information (DB00, DB01, DB02) transferred from the output circuit OUT2 of the semiconductor chip CHIP2 via the bus 210 is input to the decoding elements DEC10 to DEC17 via the input buffer circuit IBUF0. Each time 3-bit bit position information (DB00, DB01, DB02) is input, the bit position information (DB00, DB01, DB02) is decoded by one of the decoding elements DEC10 to DEC17. As a result, one of the bits INDEC10 to INDEC17 becomes “H”. Bits INDEC10 to INDEC17 are input to the input data holding circuit IREG.
[0151]
The input data holding circuit IREG1 has the same configuration as the previous data holding circuit BDREG shown in FIG. When the reset signal RESET becomes “H”, the bit IDB10 is set to “L”. As long as the “L” bit INDEC 10 is input from the decoding element DEC 10, the bit IDB 10 is kept at “L”.
[0152]
Further, when the bit INDEC10 is inverted to become the “H” bit, the bit IDB10 is inverted to become “H”. Even if the bit INDEC10 is inverted again and returns to "L", the bit ICB10 is kept at "H". However, when the bit INDEC10 is inverted again to “H”, the bit IDB10 is returned to “L”.
[0153]
A circuit corresponding to each bit held in the input data holding circuit IREG1 is shown in FIG. This circuit is a register circuit in which data is updated (inverted) only when the input becomes “H”. Therefore, the data held is not updated unless the input becomes “H” except that the data is cleared at the initial reset. When an address having a bit different from the previous transmission data is transmitted, the decoder circuit is configured to output “H” for each bit of the input address.
[0154]
In the input data holding circuit IREG1, the same output is held for bits having a logical value that has not changed compared to the previously transferred data. Therefore, by transferring only bits of data different from the previously transferred data, all bits of data are transferred. As a result, the original data can be reproduced in the semiconductor chip CHIP3 on the receiving side.
[0155]
In FIG. 15, the internal data transfer control signal TRD is not input anywhere in the figure. For example, the internal data transfer control signal TRD is supplied to the internal circuit INT3 of the semiconductor chip CHIP3, and the internal data transfer control signal TRD is supplied. In response, the bits IDB10 to IDB17 from the input circuit IN3 may be input to the internal circuit INT3 of the semiconductor chip CHIP3.
[0156]
As is clear from the above description, in the semiconductor device 200 of the second embodiment, each bit of the data transferred this time is not transferred as it is between the semiconductor chip CHIP2 and the semiconductor chip CHIP3. Is compared with each bit of the previously transferred data, and information indicating the position of the bit having the logical value changed compared to the previously transferred data is transferred. Thereby, the number of signal lines necessary for data transfer can be reduced. Further, since there is no need to charge / discharge unnecessary signal lines, more efficient data transfer is possible.
[0157]
The circuits in FIGS. 11 to 15 are merely examples, and various modifications can be made. Alternatively, a circuit having a similar function may be applied instead of these circuits.
[0158]
【The invention's effect】
According to the semiconductor device of the present invention, bit position information indicating the position of at least one selected bit among a plurality of bits included in data is generated, and the bit position information is transmitted. The content of the data is transmitted from the transmission unit to the reception unit using bit position information having a smaller number of bits than the number of bits of data to be transmitted. Thereby, the bit width of the bus connecting the transmission unit and the reception unit can be made smaller than the bit width of the data to be transmitted. For example, 8-bit data can be transmitted using a 3-bit bus. As a result, the scale of the semiconductor device can be reduced.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a semiconductor device 100 according to a first embodiment of the present invention.
2 is a block diagram showing a configuration of an output circuit OUT0 in the semiconductor chip CHIP0 shown in FIG.
FIG. 3 is a circuit diagram showing a configuration of an HL deviation determination circuit COMP shown in FIG. 2;
4 is a circuit diagram showing a partial configuration of an output data holding circuit OREG shown in FIG. 2;
FIG. 5 is a circuit diagram showing a configuration of a jumpable shift register JREG shown in FIG. 2;
FIGS. 6A to 6H are circuit diagrams showing configurations of encoding elements ENC00 to ENC07 shown in FIG.
7 is a block diagram showing a configuration of an input circuit IN1 in the semiconductor chip CHIP1 shown in FIG.
FIGS. 8A to 8H are circuit diagrams showing configurations of the decoding elements DEC10 to DEC17 shown in FIG.
9 is a circuit diagram showing a configuration of part of the input data holding circuit IREG shown in FIG. 7;
10 is a timing chart showing operations of the output circuit OUT0 and the input circuit IN1 shown in FIG.
FIG. 11 is a block diagram showing a configuration of a semiconductor device 200 according to a second embodiment of the present invention.
12 is a block diagram showing a configuration of an output circuit OUT2 in the semiconductor chip CHIP2 shown in FIG.
13 is a circuit diagram showing a configuration of part of the output data holding circuit OREG1 shown in FIG.
14 is a circuit diagram showing a partial configuration of a previous data holding circuit BDREG shown in FIG. 12;
15 is a block diagram showing a configuration of an input circuit IN3 in the semiconductor chip CHIP3 shown in FIG.
[Explanation of symbols]
CHIP0, CHIP2 Semiconductor chip
CHIP1, CHIP3 Semiconductor chip
OUT0, OUT2 output circuit
IN1, IN3 input circuit
OREG, OREG1 output data holding circuit
JREG interleaving shift register
ENC0 to ENC7 Encoding element
COMP HL bias judgment circuit
OBUF0, OBUF1, OBUF2 output buffer
IREG, IREG1 Input data holding circuit
DEC10 to DEC17 decoding element
IBUF0 to IBUF2 input buffer circuit
XOR exclusive OR circuit
BDREG Previous data holding circuit

Claims (5)

A semiconductor device comprising a transmitter and a receiver connected via a bus,
The transmission unit encodes data including a plurality of bits, thereby generating bit position information indicating a position of at least one bit selected from the plurality of bits included in the data; An output unit for outputting the bit position information to the bus,
The receiving unit includes an input unit that receives the bit position information from the bus, and a decoding unit that generates the data by decoding the bit position information ,
The selected at least one bit is a bit having a specific logic value;
The transmission unit compares the number of bits indicating whether or not the number of bits having the specific logical value among a plurality of bits included in the data is greater than the number of bits having a logical value other than the specific logical value A bit number comparison information generating unit for generating information, and the output unit outputs the bit position information and the bit number comparison information to the bus;
The input unit in the receiving unit receives the bit position information and the bit number comparison information from the bus, and the decoding unit decodes the bit position information based on the bit number comparison information. A semiconductor device that generates the data . 2. The semiconductor device according to claim 1, wherein the selected at least one bit is a bit having a logical value that has changed compared to previous data transferred from the transmission unit to the reception unit . The encoding unit generates a plurality of bit position information by encoding the data,
The semiconductor device according to claim 1, wherein the output unit serially outputs the plurality of bit position information to the bus. A semiconductor device connected to a bus,
An encoding unit that generates bit position information indicating a position of at least one selected bit among the plurality of bits included in the data by encoding data including a plurality of bits;
An output unit for outputting the bit position information to the bus;
The selected at least one bit is a bit having a specific logic value;
A bit for generating bit number comparison information indicating whether or not the number of bits having the specific logical value among a plurality of bits included in the data is larger than the number of bits having a logical value other than the specific logical value A number comparison information generation unit;
The semiconductor device according to claim 1, wherein the output unit outputs the bit position information and the bit number comparison information to the bus . A semiconductor device connected to a bus,
An input unit for receiving from the bus bit position information indicating a position of at least one selected bit among a plurality of bits included in the data;
A decoding unit that generates the data by decoding the bit position information ,
The selected at least one bit is a bit having a specific logic value;
The input unit determines whether or not the number of bits having the specific logical value among the plurality of bits included in the bit position information and the data is larger than the number of bits having a logical value other than the specific logical value. Bit number comparison information indicating whether or not from the bus,
The decoding device generates the data by decoding the bit position information based on the bit number comparison information .

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