JPH11317651A - Variable digital delay line - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a delay cell which enables cascading of plural delay cells. SOLUTION: This variable digital delay cell (100) which is provided with a 1st input (IN- A) which receives a 1st input signal (INPUT) to be delayed, a 1st output (DEL- OUT) which sends a 1st output signal (OUTPUT), that is delayed to the 1st input signal and a control signal (CTRL) which controls a delay time of a delay cell is released. Furthermore, the delay cell consists of a 2nd input (IN- B) which receives a 2nd input signal that is delayed to the 1st input signal and a 2nd output (BUF OUT) which sends a 2nd output signal that is delayed with respect to the 1st input signal by only a fixed delay time. In addicting, although the delay cell can be driven as a single device, it is also possible to cascade an 'unlimited' number of delay cells, without increasing basic delay in comparison with a single delay cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention generally relates to variable digital delay lines and cascades thereof.

[0002]

2. Description of the Related Art A delay line (or a synonymous delay cell) is often used to delay an output signal by a predetermined delay time with respect to an input signal. There are a delay line with a fixed delay time and a variable delay line that allows different delay times within a predetermined range.

FIG. 1 shows a structure of a variable digital delay cell 5 which receives an input signal INPUT and sends out an output signal OUTPUT delayed by a variable delay time t _{DEL with} respect to the input signal INPUT. The value of the delay time t _DEL is determined by the control signal CTRL
It is possible to set by.

[0004] FIG. 2 shows a structural diagram of an embodiment of the variable digital delay cell 5. The input signal INPUT is the first
Signal processor 10 and delay stage 2 with fixed delay time T _D
Added to 0. Delay stage 20 can be any delay circuit known in the art, for example, a passive circuit such as an RC coupling, or an active circuit such as a buffer amplifier. The output signal of the delay stage 20 is connected to a second signal processing device 30. The output signals of the first signal processor 10 and the second signal processor 30 are applied to a third signal processor 40, which combines these signals and then outputs The signal OUTPUT is processed, but the output signal OUTPUT is variable delay time t _{DEL with} respect to the input signal INPUT.
Only be delayed. Either the first signal processing device 10 and the second signal processing device 30 or the third signal processing device 40, or all of these signal processing devices,
And sets the variable delay time t _DEL of the variable delay cell 5 according to the added control signal CTRL.

FIG. 3 shows an example of a variable digital delay cell 5 embodied by an ECL (Emitter Coupled Logic Element) that receives and processes a differential signal. However, the variable digital delay cell 5 can obviously be implemented with other logic elements or different logic such as single line logic. The first signal processing device 10, the second signal processing device 30 and the control device 50 are implemented as current switches, and the third signal processing device 40 is implemented as a summing stage.

The input signal INPUT (V _A ) is supplied to the current switch 10
And a delay stage 20 which produces a fixed delay time T _D.
The output signal V _B of the delay stage 20 is connected to the current switch 30. The output signal of the current switch 10 (complementary currents I _AC and I _AN ) and the output signal of the current switch 30 (complementary currents I _BC and I _BN ) are added by the summing stage 40, and the sum is
The output signal OUTPUT of the variable delay cell 5 is shown.

[0007] current I _Ref is by the control device 50 is divided into a current I _B to be added to the current I _A and the current switch 30 which is applied to the current switch 10. By varying the ratio of the current I _A pair I _B, it is possible to vary the delay time t _DEL of the output signal OUTPUT to the input signal INPUT. The shortest value t _DELmin of the delay time t _DEL is obtained when I _A = I _Ref and I _B = 0, so that t _DELmin is determined by the propagation delay through the current switch 10 and the summing stage 40 of the variable delay cell 5. Basic delay. The intermediate value t _DELmed is I
It is possible to set when _{A = I Ref / 2 = I} B, maximum value t _DELmax may be obtained in the case of I _B = I _Ref in I _A = 0. Maximum value t _DELmax is approximately equal to a value obtained by adding a propagation delay through the current switch 30 and the total stage 40 to a fixed delay time of the delay stage 20 T _D. The ratio of I _A pair I _B is
It can be controlled by a control signal CTRL implemented as an analog voltage.

[0008] FIG 4 is a signal diagram is shown in a typical I _A pair in the circuit of Figure 3 relates to the ratio of I _B. Of course, the intersection of the difference signals, and thus the intersection of the intermediate values of the signal differences or the complementary currents, represents a time mark for comparing the timing of the signals. Voltage V _B is delayed by a fixed delay time T _D of the delay stage 20 to the voltage V _A. The output signal OUTPUT received from the sum of the currents (I _AC + I _BC ) and (I _AN + I _BN ) is delayed from the input signal INPUT by an effective delay time t _DEL .

For the circuits of FIGS. 2 and 3, the maximum applicable delay time T _D of delay stage 20 is limited to the transition time t _T of the output signals of current switches 10 and 30 (compare FIG. 4). Therefore, T _D is selected such that T _D <t _T.
However, on the other hand, since the delay time t _DEL is limited to the delay time T _D, the delay time t _DEL of the circuit of FIG. 1, t _DEL ≦ T _D
It is limited to ≦ t _T. The delay time t _DEL selected to be longer than the transition time t _T is determined by the output signal OUTPUT during the transition.
This generally results in a "horizontal step" and thus jitter, and should generally be avoided.

In the case of a modern bipolar circuit such as an ECL circuit, the basic delay (as the shortest delay time t _DELmin ) of such a delay cell 5 is generally in the range of about 50 to 100 ps, and the transition time of the digital output signal is Is generally 100-200 p
within the range of s. That is, the typical delay range of the delay cell 5 is between the minimum value of 50-100 ps and the maximum value of 100-200 ps, and the applicable ratio (t _DELmin / t _DELmax ) is about 1: 2. Become.

In order to obtain a larger value of the longest delay t _DELmax , a plurality of delay cells can be arranged in a continuous cascade. FIG. 5 shows an example of two delay cells 5 according to FIG. 1 arranged in series as a cascade. Output signal OUT _ 1 of the first delay cell 5.1 serves for the input signal IN _ 2 of the second delay cell 5.2. Subsequent delay cells can be arranged accordingly.
However, by connecting the n delay cells 5 in series, the longest delay t _DELmax may increase n times, but the basic delay, and thus the shortest delay time t _DELmin, also increases n times. That is, the cascade not only inevitably causes at least a time delay (n × t _DELmin ) but also produces a ratio (t
_DELmin / _tDELmax ) is also 1: 2.

A digital multiplexer-controlled delay generator using a current switching element group to vary the propagation delay of a connection input voltage to a load is disclosed in US Pat.
There are several cascaded delay cells known in the prior art, such as -A-5210450. In US-A-4797586,
A high frequency signal control delay circuit is disclosed that adjusts the gain of each amplifier in accordance with a control signal such that the gain of at least one and no more than two amplifiers is not zero.

[0013]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a delay cell which allows a plurality of delay cells to be cascaded.

[0014]

SUMMARY OF THE INVENTION A variable digital delay cell according to the present invention has a first input for receiving a first input signal to be delayed, and a delay cell delay with respect to the first input signal. A first output for sending out a first output signal delayed by a time and a control signal for controlling a delay time of the delay cell are included. The delay cell further includes a second input for receiving a second input signal delayed with respect to the first input signal, and a second input delayed by a fixed delay time with respect to the first input signal. A second output for sending an output signal is included.

Although the delay cells according to the present invention can be driven as a single device, it is also possible to cascade an "unlimited" number of delay cells without increasing the basic delay compared to a single delay cell. It is. The number of delay cells in a cascade is only limited by "external" factors such as the number of available gates, power consumption, and the like.

In a preferred embodiment of the delay cell, a first signal processing unit has its input coupled to the first input so as to receive and process the first input signal, the delay stage comprising: , The input of the delay stage being coupled to the first input so as to receive the first input signal and delay by a fixed delay time, Is coupled to the second output to provide a first input signal delayed by a fixed delay time as a second output signal. The second signal processing device includes:
To receive the second input signal and process it,
That input is coupled to a second input. The third signal processing device receives output signals from the first and second signal processing devices so as to further process the first output signal for the first output. The control device controls the delay time of the delay cell according to the first control signal according to the applied control signal.
And a second signal processing device and / or a third signal processing device.

The advantages of the delay cells of the present invention are particularly evident in a cascaded plurality of individual delay cells grouped in series (or sequentially) according to a prescribed scheme. The first delay cell in the cascade receives the cascade input signal at its first input and sends out the cascade output signal at its first output. The second output of the last delay cell in the cascade is coupled to its second input. A first input of each delay cell of the cascade, except the first delay cell, is coupled to a second output of its preceding delay cell. Except for the first delay cell, a first output of each delay cell is coupled to a second input of its preceding delay cell.

The basic delay of the cascade (as the shortest delay) is independent of the number of delay cells in the cascade,
It only depends on the elementary delay of the first delay cell in the cascade. However, the longest delay time of the cascade is determined by the number of delay cells in the cascade, and is determined as the sum of the individual delay times in the cascade. An arbitrary value can be selected for the delay time between the basic delay of the first delay cell and the sum of the individual delay times in the cascade. That is, the ratio of the shortest delay time to the longest delay time (t _DELmin / t _DELmax ) is determined by the number of delay cells and each delay time. If the longest delay times of all delay cells in a cascade of n delay cells are approximately equal, the cascade ratio (t _DELmin /
t _DELmax ) is a value obtained by dividing the basic delay by n times the longest delay time.

In a preferred embodiment, the control signal (for each individual delay cell) includes a first control signal for setting the delay cell to a fixed or variable mode, and a delay time for the delay cell which is the shortest delay time. Alternatively, a second control signal for setting the longest delay time and a third control signal for setting the delay time of the delay cell to a value between the shortest delay time and the longest delay time are included. In the fixed mode, the delay time can be set to the shortest delay time or the longest delay time by the second control signal. In the variable mode, the delay time can be set by the third control signal to a value between the shortest delay time and the longest delay time of the delay cell.

By dividing the control signal into a plurality of control signals, precise control of the individual delay cells is possible, and in particular, it is possible to divide the control signal into digital and analog signals, thereby providing a third control signal. Can be implemented as analog signals. As a result, the circuit for transmitting the control signal is greatly simplified.

If only one particular delay cell in the cascade yields a value between the shortest and the longest delay time, only one third control signal has to be added. The delay time of a particular delay cell is set to a variable mode by a respective first control signal and is adjusted by a third control signal. Each of the other delay cells is set to a fixed mode by a respective first control signal;
As a result, the delay cells following the particular delay cell are set to the shortest delay time by the respective second control signals,
Each delay cell preceding a particular delay cell is set to the longest delay time by a respective second control signal.

A particular application of the delay cell as a single device or a cascaded device according to the invention is that the first output signal of the delay line or cascade is coupled via an inverter circuit and the first output signal of the delay line or cascade. The oscillator circuit is returned to the input signal of The oscillator circuit generates an oscillator frequency f〜1 / t _DEL . Therefore, the improved ratio of the cascaded delay cells (t
According to _DELmin / _tDELmax ), an oscillator having a wide applicable frequency range can be obtained.

[0023]

FIG. 6 is a structural diagram of a variable delay cell 100 according to the present invention. Delay cell 100 includes a first input I for receiving an input signal INPUT to be delayed.
And N _ A, for example, a second input IN _ B for receiving the delayed signal from the subsequent delay cell. The delay cell 100 is
A first output DEL _ OUT as an output for delivering an output signal OUTPUT as the delayed input signal INPUT, first input IN _
It added to A, but has a second output BUF _ OUT for delivering example continuous signals delayed by the maximum delay time t _DELmax delay cell 100 for the delay cell has. The delay time t _DEL of the delay cell 100 is controlled by the control signal CTRL.

The delay cell 100 as a single delay cell operates essentially according to the delay cell 5 in FIG. 1 and thus has an additional second input IN. B and the second output BUF _ OUT are coupled to each other. First input signal IN applied to the input IN _ A
PUT the control signal CTRL by a preset delay time t _DEL controlled by the delayed and output at the first output DEL _ OUT as an output signal OUTPUT.

FIG. 7 shows a structural diagram of an embodiment of the variable digital delay cell 100 according to the present invention, and uses the same components as in FIG. The input signal INPUT is the first
Input IN _ first signal processing apparatus in A 10, and applied to the delay stage 20 with a fixed delay time T _D. Variable digital delay cell 100 according to the present invention, the output signal of the delay stage 20 is fed at the second output BUF _ OUT, a second input IN _
B is distinguished from the variable digital delay cell 5 in that B is provided as an input to the second signal processing device 30. According to the variable digital delay cell 5 of FIG. 2, the output signals of the first signal processing device 10 and the second signal processing device 30 are applied to the third signal processing device 40, and the third signal processing device combines the output signals applied, then the processing to the output signal oUTPUT at the first output DEL _ OUT addition, delaying the variable delay time t _DEL to the input signal iNPUT. Either the first signal processing device 10 and the second signal processing device 30 or the third signal processing device 40, or all the signal processing devices, control the variable delay time of the variable delay cell 100 according to the applied control signal CTRL. A control signal is received from controller 50 to set t _DEL .

As will become apparent when comparing delay cells 5 and 100 of FIGS. 2 and 7, delay cell 5 has a second input IN.
_ B and can be received from the delay cells and 100 by connecting the second output BUF _ OUT directly.

FIG. 8 shows two delay cells 100 according to FIG. 7 arranged sequentially as a cascade 110 of delay cells. Input signal INPUT is applied to the first input IN _ A1 of the first delay cell 100.1, delay time t _{DEL _ 110} Cascade 110 is delayed, the first delay cell as the output signal OUTPUT of the cascade 110 the first output DEL _ O of 100.1
UT Output at 1.

In a second output BUF _ OUT _ 1, the first delay cell 100.1, for the first input IN _ A2 of the second delay cell 100.2, which is arranged following the first delay cell 100.1 Send out a signal. Signal in BUF _ OUT _ 1, the first input I
Although represents the input signal INPUT applied to N _ A1, first
Approximately equal to the longest delay time t _{DELmax _ 1} delay cell 100.1, and by a fixed delay time t _{DELfix _ 1} are delayed.
Signal at the first input IN _ A2, the second delay cell 100.2
The delay time is set by the control signal CTRL _ 2 of t _{DEL _ 2}
Only the delayed is output at the output DEL _ OUT _ 2,
It is returned to the second input IN _ B1 of the first delay cell 100.1. Signal in the second input IN _ B1, only the delay time t _{DEL _ 1} set by the control signal CTRL _ 1 of the first delay cell 100.1 is delayed, a first output DEL of the first delay cell 100.1
It is outputted as the output signal OUTPUT at _ OUT _ 1. Second
Input IN _ B2 of the longest delay time t of the second delay cell 100.2
As _{DELmax _ 2} only signal delayed second output BU
To receive a signal from the F _ OUT _ 2.

The operation of the cascade 110 of FIG.
In FIG. 9 where the embodiment of FIG. 7 is used for delay cells 100.1 and 100.2, two examples, cascade 110
A first example of the delay time t _{DEL _ 110} becomes _{t DEL _ 110 ≦ t DELmax _} 1 of, t _{DEL _ 110} is _{t DELmax _ 1 <t DEL _} 110 ≦ t
Second examples to be _{DELmax _ 1} + t _{DELmax _ 2} is revealed.

In the case of the first example, to produce the longest delay time t _{DELmax _ 1} following the delay time t _{DEL _ 110} cascade 110 of the first delay cell 100.1, first the first delay cell 100.1
Input signal is applied to the input IN _ A1 of INPUT, the delay stage 20.1
As a result, the fixed delay time t of the first delay cell 100.1.
_{DELfix _ 1} of the delay is made and output at BUF _ OUT _ 1 to the input IN _ A2 of the second delay cell 100.2. Control signal CTRL _ 2
But since it is set to produce a minimum delay time t _{DELmin _ 2,} the signal at the first input IN _ A2, the first signal processing unit 10.2 and the third signal processing apparatus of the second delay cell 100.2 coupled to the output DEL _ OUT _ 2 through 40.2, returned to the second input iN _ B1 of the first delay cell 100.1. Also, the input signal INPUT applied to the first processing unit 10.1 of the first delay cell 100.1 undergoes processing there and is processed by the third processing unit 40.
Coupled to 1, the third processing unit, from the returned signal at the input IN _ B1 is further delayed, the second processing unit 30.
Receive the signal processed by one. The second input IN _ B1
Signal, only the longest delay time t _{DELmax _ 1} because it is delayed relative to the input signal INPUT at a delay time t
_{DEL _ 110} is a control signal CTRL _ 1 of the first delay cell 100.1, maximum delay time of the first delay cell 100.1 t _{DELmax _ 1}
It can be set to any value less than.

The shortest delay time as the basic delay of the cascade 110 is determined only by the propagation delay of the first processing unit 10 and the third processing unit 40, the shortest delay time t _{DELmin _ 1} of the first delay cell 100.1 It is possible to set.

In the case of the second example, the delay time t _{DEL _ 110} cascade 110, the longest delay time of the first delay cell 100.1 t
_{DELmax _ 1} and the first delay cell 100.1 and the second delay cell 10
It can be set between the sum of the delay times of _{0.2 (t DELmax _ 1 + t} DELmax _ 2). According at the above, the input signal INPUT is coupled to the first processing unit 10.1, also delay the fixed delay time t _{DELfix _ 1} is performed by the delay stage 20.1 for the input IN _ A2 of the second delay cell 100.2 BUF Te _
Output from OUT_1 .

[0033] The second input IN _ B2 and the second output BUF _ OUT Two
Are coupled to each other so that the second delay cell 100.2
Operate according to the delay cell 5 in FIG. Signal at the first input IN _ A2 according to the setting of the control signal CTRL _ 2, is delayed in the second delay cell 100.2 delay time t _{DEL _ 2,} are outputted at output DEL _ OUT _ 2. At that time, the signal at DEL _ OUT _ 2, the input signal INPUT
, The longest delay time t of the first delay cell 100.1
_{DELmax _ 1,} and the delay time of the second delay cell 100.2 t _{DEL _ 2}
And the second input I of the first delay cell 100.1.
It is returned to the N _ B1.

[0034] The first delay cell 100.1, therefore input IN _ A1
Receiving an input signal INPUT in, in IN _ B1, INPU
Only receive signal delayed _{(t DELmax _ 1 + t DEL} _ 2) with respect to T. Control signal CTRL _ 1, the signal at IN _ B1 is coupled directly to the DEL _ OUT _ 1, the resulting output signal OUTPU
T is set to occur. Of course the first delay cell 1
IN _ B with the longest delay beyond the delay time t _{DELmax _ 1} of 00.1
It will be appreciated that the mixing of the signal at 1 with the input signal INPUT also results in a "horizontal step" in the output signal OUTPUT during the transition, and thus usually also jitter that should be avoided.

[0035] t _{DEL _ 2} If the is set to be the longest delay time t _{DELmax _ 2,} it is possible to select the longest delay time of the cascade _{110 (t DELmax _ 1 + t} DELmax _ 2). However the control signal CTRL _ 1 and CTRL _ 2, it is possible to select the entire range of delay values that might up _{(t DELmax _ 1 + t DELmax} _ 2).

FIG. 10 shows a plurality of delay cells 100 according to FIG.
A cascade 120 of is shown. The principle of cascading the delay cells 100.i can be described as follows. The first delay cell 100.1 receives an input signal INPUT at its input IN _ A1, sends the output signal OUTPUT at its output DEL _ OUT _ 1. Each delay cell 100.i has its input IN From the received signal at ai, the control signal CTRL _
Delay time t _DEL according to the setting of i Input IN _ A _{that i} only delayed
As the signal at i, sending a first output DEL _ OUT _ i, fixed delay time of the delay cell 100.i t _DELfix as the signal at the input IN_Ai was delayed _i, a second output BUF _ OUT
Send out _i. Except the first delay cell 100.1, first output DEL _ OUT _ i of each delay cell 100.i is, the preceding delay cell 10
0. coupled to (i-1) of the input IN _ B (i-1). Cascade 110
Except for the last delay cell 100.n, the second output BUF _ OUT _ i
Is coupled to the input IN _ A subsequent delay cell 100. (i + 1) (i + 1). Only the end of the delay cell 100.n, the output BUF _ OUT
_n is coupled to the input IN _ Bn directly.

As is apparent from the above, the cascade 120
Is not intended to be limited to a predetermined number of delay cells 100.I, the delay time t _{DEL _ 120} cascades up, set to the sum of all the maximum delay time t _{DELmax _ i} delay cell 100.I It is possible to However cascade 120
The shortest delay time as the basic delay of (110) is the same as the basic delay of the single delay cell 100 determined only by the propagation delay of the first processing device 10 and the third processing device 40.

[0038] It is apparent that all of the longest delay time t _{DELmax _ i} of the individual delay cell 100.i there is a possibility that different. However, for simplicity or to reduce production costs,
Individual maximum delay time t _{DELmax _ i} of the delay cell 100.i is preferably all the same within a predetermined tolerance.

[0039] some applications, especially when the analog signal is used, it may limit the number of signals of the control signal CTRL _ i is desirable. In the case where the control signal CTRL _ i,
For setting the delay cell 100.I individual signal VARFIX _ i for setting the fixed mode or variable mode, the shortest delay time the delay time of the delay cell 100.i t _{DELmin _ i} or longest delay time t _{DELmax _ i} common signal COM is included for setting the delay time of Another individual signal MINMAX _ i and cascade. Individual signal VAR applied to each delay cell 100.i
By FIX _ i, the delay cell 100.i, the delay time t
_{DEL _} or _i is set to a fixed mode that is set to the minimum delay time of the delay cell t _{DELmin _ i} or longest delay time t _{DELmax _ i,} or by a common signal COM, the shortest delay of the delay cell delay time would be set to a value t _{DEL _ i} between time and the longest delay time is set in the variable mode possible. In the fixed mode, the delay cell 100.i is
The individual signal MINMAX _ i, to the input IN _ Ai, the shortest delay time t _{DELmin _ i} or longest delay time t _{DELmax _ i} only
Set the signal at the output DEL _ OUT _ i to delay. The common signal COM only has an effect when the delay cell 100.i is in the variable mode.

[0040] Figure 11 is an embodiment of the delay cell of Figure 7 is shown in differential logic, the control signal CTRL, which contains common signal COM and the individual signal VARFIX _ i and MINMAX _ i I have. The delay cell in FIG. 11 is basically configured according to the delay cell in FIG.
And the second signal processing device 30 and the delay stage 20 receive the differential input signal. However, the control device 50 controls the control signal VA.
RFIX _ i, is replaced by a control unit 200 which receives the MINMAX _ i and COM. The control device 200 includes a control signal VAR
The first control circuit 210 that receives FIX _ i, control signal MINMAX _ i
And a third control circuit 230 for receiving the control signal COM.

The control circuit 210, when set to fixed mode through the control signal VARFIX _ i, start the second control circuit 220 to stop the third control circuit 230. When the second control circuit 220 is set to the shortest delay time via the control signal MINMAX_i, the first signal processing device 10 is started and the third signal processing device 30 is stopped, so that the input IN_A signal in is (directly) to DEL _ OUT is coupled. Second control circuit 220
But, when set to maximum delay time through the control signal MINMAX_i, the first signal processing unit 10 is stopped, since the start of the third signal processing unit 30, the signal at the input IN _ B is, DE
(Direct) is output to the L _ OUT.

The control circuit 210, when it is set in the variable mode through the control signal VARFIX _ i, the second control circuit 220 is stopped, activates the third control circuit 230, the third control circuit Controls the first signal processing device 10 and the second signal processing device 30 according to the control of the control device 50 of FIG.

FIG. 12 (dotted box) shows a more detailed embodiment of the delay cell of FIG. Signal processing device
10.i and 30.i and the control devices 210.i, 220.i and 230.i
Implemented as a current switch, the third signal processing device 40.i
Is implemented as a summation stage.

FIG. 13 shows a combination with FIG.
The cascading of the two delay cells of FIG. 12 is shown.
In this case, IN _ Bi is connected to a DEL _ OUT _ i + 1, BUF _ OUT _
i will be connected to IN_A (i + 1). Of course, the figure
It is understood that the number of delay cells aligned according to 13 is not limited to two. Obviously, a plurality of delay cells arranged like the right delay cells in FIG. 13 and connected to their respective left delay cells can be grouped on the right side of FIG. In any case,
Last input IN _ Bn and the output B of the delay cell n (rightmost)
UF _ OUT _ n is to be coupled to each other.

FIG. 14 is a schematic diagram showing a configuration of the plurality of delay cells of FIG. 11 grouped according to the configuration shown in FIG. However, in the case of FIG.
Is supplied by a (single) control line 250, for example, as an analog signal, to each of the plurality of delay cells 100.i. In contrast, the individual control signal MINMAX _ i and VA
RFIX _ i is supplied to each delay cell 100.i individually. Fig. 14
As shown in the individual control signal MINMAX _ i and VARFIX _ i is
For example, it can be supplied by the control bus 260 as a digital signal.

[0046] In the preferred embodiment, the delay time of a particular only one delay cell 100.I, control signal VARFIX _ i
Is set in the variable mode, and is adjusted by the control signal COM. All other delay cells are driven in a fixed mode, so that delay cell 100.i + 1 is set to the shortest delay time, and if x <i, then all delay cells 100.x (or in other words, For example, the delay cell preceding the delay cell 100.i) is set to the longest delay time. If y> i + 1, then each state does not affect the delay time of cascade 120 because delay cell 100.y is "short cut" by delay cell 100.i + 1. With this method,
It is ensured that a "horizontal step" in the output signal OUTPUT during the transition is avoided and only one control signal COM is required.

In the following, exemplary embodiments comprising combinations of various constituent elements of the present invention will be described.

1. A variable delay cell (100): a first input for receiving a first input signal to be delayed (INPUT) (IN _ A), the delay time of the delay cell (100) (t _DEL) a first output for delivering a first output signal that is delayed relative to the first input signal (oUTPUT) and (DEL _ OUT), the delay time of the delay cell (100) (t _DEL)
And a control signal (CTRL) for controlling the
Further to the delay cell (100): a second for receiving a second input signal delayed with respect to the first input signal (INPUT).
And input (IN _ B), a fixed delay time (T _D) by a second output for delivering a second output signal that is delayed relative to the first input signal (INPUT) (BUF _ OUT) Is included.

2. Further, a first input for receiving and processing a first input signal (INPUT) (IN _ A) input to is coupled, a first signal processor (10), fixed delay time (T _D) delay stage to produce (20) and the input of the delay stage (20), fixed delay time by receiving a first input signal (iNPUT) (T _D) by a first input that is delayed (iN _ a) coupled to the output of the delay stage (20), coupled to the second output delivering a fixed delay time (T _D) by a first input signal obtained by delaying (iNPUT) as a second output signal (BUF _ OUT) And a second input (IN) for receiving and processing the second input signal.
_ B) a second signal processing device (30) having an input coupled thereto;
First signal processing device (10) and second signal processing device (30)
It receives the output signals from, then the first output (DEL _ OU
A third signal processor (40) for processing a first output signal (OUTPUT) for T), a first signal processor (10) and a second signal processor (30) and / or The delay time (t _DEL ) of the delay cell (100) is coupled to the third signal processing device (40) according to the applied control signal (CTRL).
2. The delay cell according to claim 1, including a control device (50) for controlling the delay cell.

3. A first signal processing device (10) comprising a current switch, a second signal processing device (30) comprising a current switch, a third signal processing device (40) comprising a total stage, and a control device (50). 2. The delay cell of claim 1, wherein the delay cell comprises a current switch.

4. Control signal (CTRL): delay cell (10
0) to set the fixed mode or the variable mode
Control signal (VARFIX_i) and the delay of the delay cell (100)
Between (t_DEL) To the shortest delay time (t_{DELmin _ i}) Or longest late
Delay time (t_{DELmax i}Second control signal for setting
(MINMAX_i) and the delay time (t) of the delay cell (100)_DEL)
Is the shortest delay time (t_{DELmin _ i}) And the longest delay time (t
_{DELmax i}A third control signal for setting to a value between
(COM), thereby allowing the fixed mode
And the second control signal (MINMAX_i) by the delay time
(T_DEL) To the shortest delay time (t_{DELmin _ i}) Or longest delay
Time (t_{DELmax i}) Can be set to
In the mode, the third control signal (COM) causes a delay.
Delay time (t_DEL) To the shortest delay time (t_{DELmin _ i}) And the longest
Delay time (t_{DELmax i}) Can be set to a value between
3. The delay cell according to paragraph 1 or 2.

5. A first control circuit (210) for the control device (200) receiving a first control signal (VARFIX);
A second control circuit (220) for receiving a second control signal (MINMAX), and a third control circuit (230) for receiving a third control signal (COM). By
A first control circuit (210) configured to output a first control signal (VARFIX);
When the fixed mode is set through the second control circuit (220), the second control circuit (220) is activated, the third control circuit (230) is stopped, and the second control circuit (220) Control signal (M
INMAX), the first signal processing device (10) is started, and the third signal processing device (3
0) to stop the, whereby the first input (a first input signal at IN _ A) (INPUT) is first output (DEL _ OUT)
And the second control circuit (220)
When the longest delay time is set via the control signal (MINMAX), the first signal processing device (10) is stopped and the third signal processing device (30) is activated, whereby the second input the second input signal at the (iN _ B) is, the first output (DEL _
OUT) and the first control circuit (210)
When set to the variable mode via the first control signal (VARFIX), the second control circuit (10) controls the first signal processing device (10) and the second signal processing device (30). 5. The delay cell according to claim 4, wherein the delay cell is stopped and the third control circuit is activated.

6. A delay cell according to claim 5, wherein the first control circuit (210) comprises a current switch, the second control circuit (220) comprises a current switch, and the third control circuit (230) comprises a current switch.

7. A cascade (110, 120) of a plurality of delay cells (100.i): a first delay cell (100.1)
But a to pump its first input at (IN _ A1) receiving a first input signal (INPUT), a first output signal at the first output (DEL _ OUT _ 1) and (OUTPUT), the second output of the last delay cell (100.n) (BUF _ OUT _ n) is excluded and that is coupled to the second input (iN _ Bn), the first delay cell (100.1) and the first input of each delay cell (100.i) (iN _ Ai) is coupled to the second output of the preceding delay cell (100.i-1) (BUF _ OUT _ i-1) , The first output (DE) of each delay cell (100.i) except the first delay cell (100.1).
L _ OUT _ i) is coupled to a second input of the preceding delay cell (100.i-1) (IN _ Bi-1), 1 1 or 2 wherein the cascade described.

8. A first delay cell (100.1) receives the first input signal (INPUT) at its first input (IN _ A1), the first output (DEL _ OUT _ 1) at a first output and to pump signal (oUTPUT), and the second output of the last delay cell (100.n) (BUF _ OUT _ n) is coupled to the second input (iN _ Bn), the One delay cell (10
The first input of each delay cell, except for 0.1) (100.i) (IN _ A
i) is a second output of the preceding delay cell (100.i-1) (BUF _ OU
T_i -1) and the first delay cell (100.1)
The first output of each delay cell with the exception of (100.i) (DEL _ OUT _ i)
There, the second input of the preceding delay cell (100.i-1) (IN _ Bi-1)
And as a result, the delay time of only one particular delay cell (100.l) is
Is set by the control signal (VARFIX _ l) the variable mode, and be adjusted by the third control signal (COM), each of the other delay cell (100.i) is, first of its respective 1
Control signals and being set to a fixed mode by (VARFIX _ i), a delay cell that follows the specific delay cell (100.l) (100.l + 1) , the respective second control signal ( MIN
If it and is set to the shortest delay time _{(t DELmin _ l + 1)} , and each delay cell (k <l preceding the specific delay cell (100.l) by MAX _ l + 1), 100 . k) is set that the respective second control signal (MINMAX _ k) maximum delay time by (t _{DELmax _ k),} cascade according Section 4.

9. Item 9. The variable digital delay line or the cascade of variable digital delay lines according to any one of Items 1 to 8, wherein the first input signal (INPUT) and the first output signal (OUTPUT) are difference signals.

10. An oscillator circuit, comprising: a variable digital delay line (100) according to paragraph 1 or 2 or a cascade of variable digital delay lines according to paragraph 7 or 8, and an inverter circuit, whereby a delay is provided. Oscillator circuit characterized in that a first output signal (OUTPUT) of a line or cascade is coupled via an inverter circuit and returned to a first input signal of a delay line or cascade.

[0058]

The first input signal to be delayed (INPU
T) to receive the first input (IN A) and a first output (DEL) for delivering a first output signal (OUTPUT) delayed with respect to the first input signal. OUT), a variable digital delay cell (100) comprising a control signal (CTRL) for controlling the delay time of the delay cell. The delay cell further includes a second input (IN) that receives a second input signal that is delayed with respect to the first input signal. B) and a second output (BUF OUT) for delivering a second output signal that is delayed with respect to the first input signal by a fixed delay time.

Although the delay cells according to the present invention can be driven as a single device, they can also cascade an "unlimited" number of delay cells without increasing the basic delay as compared to a single delay cell. It is possible.

[Brief description of the drawings]

FIG. 1 is a structural diagram for an embodiment of a variable digital delay cell known in the art.

FIG. 2 is a structural diagram for an embodiment of a variable digital delay cell known in the art.

FIG. 3 is a structural diagram for an embodiment of a variable digital delay cell known in the art.

Is a signal diagram in Figure 4 Typical ratios in the circuit of Figure 3 relating to I _A pair I _B.

FIG. 5 is a diagram showing an example of a cascade of two delay cells in the art.

FIG. 6 is a structural diagram of a variable delay cell 100 according to the present invention.

FIG. 7 is a structural diagram of a variable delay cell 100 according to the present invention.

FIG. 8 shows a cascade of two delay cells according to FIG. 7;

9 shows an embodiment for the cascade of FIG. 8;

10 shows a cascade 1 of a plurality of delay cells 100 according to FIG.
FIG.

FIG. 11 is a diagram showing an embodiment of the delay cell of FIG. 7 in differential logic.

FIG. 12 is a diagram illustrating a more detailed embodiment of the delay cell of FIG. 11;

FIG. 13 shows a combination of FIG. 12 and FIG.
FIG. 3 illustrates a cascade of two delay cells.

FIG. 14 is a diagram showing a configuration of a plurality of delay cells of FIG.

[Explanation of symbols]

 IN_A first input IN_B second input DEL_OUT first output BUF_OUT second output 10 first signal processing device 20 delay stage 30 second signal processing device 40 third signal processing device 100 delay cell 100.1 first Delay cell 100.2 second delay cell 110 cascade 120 cascade 200 controller 210 first control circuit 220 second control circuit 230 third control circuit 260 control bus

Claims (1)

[Claims] 1. A variable delay cell (100): a first input for receiving a first input signal to be delayed (INPUT) and (IN _ A), the delay time of the delay cell (100) (t _DEL) only, a first output for delivering a first output signal that is delayed relative to the first input signal (oUTPUT) (DEL _ OUT) , the delay time of the delay cell (100) (t _DEL ) and a control signal (CTRL) for controlling a second input signal delayed with respect to the first input signal (INPUT). Second
And input (IN _ B), a fixed delay time (T _D) by a second output for delivering a second output signal that is delayed relative to the first input signal (INPUT) (BUF _ OUT) Is included.