JPH1131739A - Wafer cassette of semiconductor wafer package container - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid the contact between adjacent semiconductor wafers even if the semiconductor wafers are rattling in support grooves, by a method wherein the wall thickness of the teeth in a semiconductor wafer contact edge in a front domain is made within a specific range. SOLUTION: A standard wafer cassette is provided with the teeth 8, 10 comprising the support grooves 7, 9 for supporting in parallel multiple semiconductor wafers with at a specific interval in front and rear domains. Next, when the wafer cassette is turned sideways, the protrusive strips 8a having the sections thereof taking almost mesa shape are extended along the front end edges to be the contact edge parts of the semiconductor wafers on the groove sides in the support groove 7 on the opposite side to the wafer mounting surface. At this time, the protrusive size of the protrusive strips 8a is to be made so that the wall thickness T of the teeth 8 containing the protrusive strips 8a may be as follows, i.e., T>Lt+Rt. The Lt and Rt are the protrusion in the bottom side and the top side on the front end of the semiconductor wafer WL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wafer cassette accommodated in a semiconductor wafer packaging container and supporting a plurality of semiconductor wafers in parallel at a predetermined interval, and more particularly, to a wafer cassette in which semiconductor wafers are accommodated. When the wafer cassette is in the vertically placed state, even if the semiconductor wafer is tilted in the support teeth, the adjacent wafers do not come into contact with each other to be damaged so that the semiconductor wafers are not contacted in the wafer cassette. The present invention relates to a wafer cassette capable of preventing the above.

[0002]

2. Description of the Related Art A semiconductor wafer packaging container is usually composed of a wafer cassette for accommodating a plurality of semiconductor wafers, a container body for accommodating and holding the wafer cassette, a wafer pressing member for elastically gripping a peripheral edge of the wafer, and the like. I have. As a general material for the wafer cassette and the outer box body, polypropylene is used, and the lid is made of polypropylene or polycarbonate. Further, polyethylene or thermoplastic elastomer is used for the wafer pressing member.

[0003] The semiconductor wafer is manufactured by slicing a single crystal such as silicon thinly. The semiconductor wafer is highly brittle and has a great influence on physical properties due to contamination. Every effort must be made in the process to prevent damage and contamination. That is, at the time of storing the semiconductor wafer in the packaging container, contamination or damage due to collision of the semiconductor wafer with the wafer cassette must be avoided. In addition to preventing damage to the wafer, it is necessary to avoid contamination due to particles generated by friction with the wafer pressing member in the container. Therefore, it is strictly required to ensure the fixation of the wafer when the container is housed and to avoid the surface contact with the wafer cassette and the wafer pressing member and the friction thereof.

For example, Japanese Utility Model Laid-Open Publication No. Hei 6-26263 discloses a small wafer cassette for semiconductor wafers.
The wafer cassette has a shape of an open box with a part of the bottom cut away, and the bottom side of the left and right side walls is curved in an arc along the peripheral shape of the semiconductor wafer. Teeth extend along the arc on the inner surface of the left and right side wall portions, and a support groove for accommodating and supporting the semiconductor wafer is formed between the teeth. The wafer cassette disclosed in this publication suppresses dust generation when semiconductor wafers are inserted into and removed from the cassette, and in order to accurately support the wafers in the cassette, the thickness of the teeth is reduced from the cassette opening to the bottom. The width of the support groove at the bottom of the cassette is gradually reduced toward the bottom. Alternatively, when the teeth are formed to have a uniform thickness, a raised portion is formed on the semiconductor wafer mounting surface of the teeth, and the groove width is reduced at the end of the support concave groove on the bottom side.

However, the configuration disclosed in the above publication is applied to a small semiconductor wafer having a maximum diameter of at most 8 inches. This small-sized semiconductor wafer relies exclusively on manual operations, particularly for accommodating a wafer in a wafer cassette and taking out a wafer from the cassette, and the required minimum requirements were satisfied even with the configurations disclosed in the above-mentioned publications. However, various problems have arisen with the enlargement of the wafer diameter and the automation of handling, and standardization for these problems has been studied. Specifically, the practical use of a semiconductor wafer having a maximum diameter of 12 inches (300 mm) has been decided. Furthermore, it is expected that
Standardization of wafer handling specifications etc. is performed in various fields dealing with semiconductor wafers such as wafer manufacturers, transportation-related fields, device manufacturers, etc., in order to accommodate semiconductor wafers with a diameter of 2 inches or more, in order to increase the size of semiconductor wafers. That is inevitable.

[0006] Standardization in the basic part of the wafer packaging container described above is already an international standard, SEMI.
(Semiconductor Equipment and Material Internationala
l). The basic philosophy of the standardization is to appropriately cope with full automation in various processing steps accompanying the enlargement of semiconductor wafers. In other words, the processes in various processes, such as cleaning, printing, cutting, etc., that were previously dependent on humans, such as cleaning, printing, cutting, etc., have been standardized, and all the handling of semiconductor wafers in each process is left to robots to achieve complete automation. I'm trying. As a result, there is a need to adapt the wafer packaging container to the automation. Incidentally, the current SEMI standard is based on the fact that all semiconductor wafers are handled in a horizontal posture in various processing steps of a device other than during transportation to a device manufacturer.

Incidentally, packaging containers for large wafers have been developed in the past. This large-sized semiconductor wafer packaging container is roughly classified into two types, a vertical type and a horizontal type. That is, the vertical type wafer packaging container is
A wafer cassette accommodating and supporting semiconductor wafers is housed in a container body in a vertical posture, and in a later processing step, the wafer cassette is converted to a horizontal posture to extract semiconductor wafers. The wafer cassette accommodating and supporting the semiconductor wafer is housed in the container body in a horizontal posture, the wafer cassette is taken out of the container body in the horizontal posture, the wafer is extracted, and the wafer cassette is in a vertical posture during transportation.

In the SEMI standard at the present time, the specifications of the wafer cassette are standardized and the basic structure of the horizontal type semiconductor wafer packaging container for operating the semiconductor wafer in a horizontal posture is standardized. . However, it is fully conceivable that a vertical type semiconductor wafer packaging container and a wafer cassette that transport semiconductor wafers in a vertical position and operate the wafer cassette in a vertical position will be standardized in the future. Therefore, the present invention is being studied including the possibility of application not only to the horizontal type wafer cassette in accordance with the current SEMI standard but also to the vertical type wafer cassette for the future.

In both vertical and horizontal types of semiconductor wafer packaging containers, a plurality of semiconductor wafers are placed in support grooves of the semiconductor wafer formed in parallel on the inner surfaces of the front and rear side domains of the wafer cassette. Contained and supported. In addition, in this specification, the front refers to a side on which semiconductor wafers are inserted into a wafer cassette, and the rear refers to a back side opposite to the insertion side.

In this manner, with the wafer cassette housed in the container body, the container body is closed by the engaging member. At this time, a wafer pressing member provided with a plurality of concave grooves having the same form as the support concave groove is attached to the center of the back surface of the container main body, and when the container main body is closed by the engaging member, the wafer is pressed. The opposite peripheral edges of the plurality of semiconductor wafers accommodated and supported in the support concave grooves of the cassette are accommodated in the respective concave grooves of the wafer pressing member and simultaneously pressed by the same pressing members, so that the semiconductor wafers in the container are loose. Be firmly grasped so that there is no.

It should be noted here that the operation of inserting and removing the wafer cassette into and from the container body, and the operation of removing and inserting a large-diameter semiconductor wafer from the wafer cassette are performed exclusively by a robot. It is. Accordingly, the cassette gripping portion and the wafer gripping portion of this robot are also standardized. For example, when a semiconductor wafer is extracted from the wafer cassette, the gripping portion in the wafer cassette can be smoothly moved without damaging the wafer. The maximum movement range and the allowable range of grip force are standardized.

In response to this standardization, there are also restrictions on the formation regions of the front and rear side domains of the wafer cassette. According to the SEMI standard, as shown in FIG. 12, the distance x3 between the center line Y extending back and forth of the wafer cassette 31 and the inner end of the front side domain 34 is 125 mm or more, and the center line Y is The distance x9 from the outer end of the side domain 34 is 167 m
m, the distance y11 between the center line B extending to the left and right of the wafer cassette and the front end of the front side domain 34 is restricted to 85 mm or less, and the distance y4 to the rear end is restricted to 85 mm or less. ing. The rear side domain 35 has a distance x between the center line Y and its inner end.
1 is not less than 50 mm, the distance x2 from the outer end is not more than 75 mm, the distance y5 between the center line X extending to the left and right of the wafer cassette and the front end of the rear side domain 35 is not more than 120 mm, and the rear end is The distance y6 from the part is regulated to 152 mm or less.

[0013] Further, regarding the form of the above-mentioned supporting groove formed in the front and rear side domains,
Strictly specified in the EMI standard. According to this rule, the groove width w of the support concave groove should be at least 6 between the depth corresponding to the radius of the semiconductor wafer W of 300 mmφ.
mm width, which is about 10 times less than the thickness (0.775 mm) of a normal semiconductor wafer. Further, as shown in FIG. 13, the groove 37 has a side surface 37a formed in a plane parallel to the top and bottom domains. Further, the groove bottom surface is bisected at the center of the groove width, one groove bottom surface 37c is orthogonal to the groove side surface 37a, and the other groove bottom surface 37d is inclined with respect to the groove side surface 37a. In this way, half of the groove bottom is
7d, the semiconductor wafer is transported from a vertical position to a horizontal position for a later processing step, and when the wafer is mounted on the groove side surface 37a, the groove side surface is formed. This is for guiding the semiconductor wafer to the groove side surface 37a by the inclined bottom surface 37d so that the semiconductor wafer does not come into contact with the semiconductor wafer 37a.

[0014]

By the way, in the conventional semiconductor wafer packaging container, when the wafer cassette is inserted into and removed from the container main body with the semiconductor wafers accommodated in the wafer cassette, or when the wafer cassette is moved from the container main body. When the cassette is taken out and moved to a predetermined working position manually or by a robot, a large number of semiconductor wafers are supported only by the wafer cassette. In such a case, since the groove width of the support groove formed in the wafer cassette is almost less than 10 times the thickness of the semiconductor wafer as described above, when the wafer swings in the support groove, Lean down. At this time, the wafer tilted in the support groove comes into contact with the edge of the teeth constituting the support groove near the front end of the front side domain. At this time, if the thickness of the teeth is not set properly and the semiconductor wafers adjacent to each other with the teeth interposed therebetween are tilted in a direction approaching each other, the semiconductor wafers come into contact with each other and are damaged. Such inconveniences occur.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a specific object thereof is to accommodate a large number of semiconductor wafers in a wafer cassette in a vertical position and to a container body of a semiconductor wafer packaging container. Provided is a wafer cassette in which adjacent semiconductor wafers do not come into contact with each other even when semiconductor wafers are backlashed and tilted in a support groove when a wafer cassette is inserted or removed, or when the same cassette containing wafers is moved independently. It is in.

[0016]

SUMMARY OF THE INVENTION In order to achieve the above-mentioned object, the present invention is directed to a semiconductor wafer packaging container in which a number of semiconductor wafers are arranged at predetermined intervals in front and rear side domains. A standardized wafer cassette provided with teeth forming support grooves for parallel support by means of the above, wherein the thickness T of the teeth at the semiconductor wafer contact edge of the front side domain is:
The main configuration is a wafer cassette characterized by being set to a value that satisfies the equation of T> (Lt + Rt). In addition, Lt indicates the amount of the semiconductor wafer disposed on the top side of the one tooth falling to the bottom side at the front end, and Rt indicates the top side at the front end of the semiconductor wafer disposed on the bottom side of the one tooth. This indicates the amount of falling.

The semiconductor wafer is a front side domain 4
And are accommodated in supporting grooves 7, 9 formed between the teeth 8, 10 of the rear side domain 5. As described above, the groove width of the support grooves 7 and 9 is set to a value considerably larger than the thickness of the wafer according to the SEMI standard, so that the wafer is easily inclined in the support grooves 7 and 9. . The tilted semiconductor wafer is supported in contact with the front edge or the inner edge of the front side domain 4.

Here, a case where the semiconductor wafer contacts the front edge of the front side domain 4 will be described as an example. The semiconductor wafer which is accommodated in the support grooves 7 and 9 of the front and rear side domains 4 and 5 and tilts is shown in FIG.
Sometimes the front end F _L of the semiconductor wafer WL for tilting the semiconductor wafer WL and the top side of tilted bottom, F _R between approaches in each of the supporting grooves 7 and 9 adjacent as shown in. When the two adjacent semiconductor wafers WL and WR tilted in the directions approaching each other are tilted to the maximum, the height dimension y11 from the cassette center to the front edge of the front side domain is defined by the SEMI standard. Setting the maximum dimension (85 mm) and keeping the groove width constant can prevent the semiconductor wafer W from contacting. However, in general, the thickness of the teeth is reduced in operability and removal from the mold. to facilitate, being molded by gradually increasing the groove width is gradually decreased toward the tip from the base portion, it is a normal, they wafer WL, WR front end F _L of unavoidable contact between F _R.

In order to prevent the adjacent wafers from contacting each other, it is necessary to make the inclination angles of the wafers as small as possible so as to be close to vertical. For this purpose, by increasing the height dimension y11, the inclination angle of the wafer is reduced, and it is possible to avoid contact between adjacent wafers. However, in the current SEMI standard,
Since the height dimension y11 is strictly defined, it is impossible at present to increase the dimension y11.

The present inventors have intensively studied a wafer cassette structure in which adjacent wafers supported by the side domain do not contact each other while complying with the standardized standard. As a result, it has been found that there is a reasonable structure capable of supporting a large semiconductor wafer in a non-contact state without changing the height dimension y11 and the groove width between the teeth. That is, the problem can be solved by locally increasing the thickness T of the teeth 8 at least at the edge of the front side domain 4 which contacts the semiconductor wafer. That is,
If the thickness T is made larger than the sum of the respective fall amounts Lt and Rt of the adjacent semiconductor wafers WL and WR,
As shown by the phantom line in FIG. 1, the inclination angle of the semiconductor wafer WR is reduced, and the contact between the adjacent semiconductor wafers WL and WR is avoided. However, when determining the local thickness T, the required amount of fall Lt,
Rt is not determined uniformly, but is changed depending on the diameter R of the semiconductor wafer W, the width z11 of the support groove, and the support height M.

Hereinafter, a method of calculating Lt and Rt in the above equations will be described with reference to FIGS. Note that, here, the X axis and the Y axis adopt an axis that is a reference for each dimension in the SEMI standard. The semiconductor wafer W may contact the inner edge of the front side domain 4 as shown in FIG. 2 or may contact the front edge of the front side domain 4 as shown in FIG.

1. The coordinates (X _S , Y _S ) of the contact point S between the rear side domain 5 and the semiconductor wafer W are obtained. The contact point S because there always inside of the rear side domain 5, and x1 ≦ X _S ≦ x2. Further, the contact point S and Y in the SEMI standard
The distance from the point (0, y1) on the axis is set to r.
Use right-angled triangle having the hypotenuse of the two points, the Pythagorean ^{_{theorem, X S 2 + (y1 +}} Y S) 2 = r 2 Accordingly, the ^{_{Y S = y1 -√ (r 2}} -X S 2).

2. The coordinates of the center C of the semiconductor wafer W (0,
Y _C ). The distance between the wafer center C and the contact point S corresponds to the radius R of the semiconductor wafer W. In the present invention, it is assumed that the semiconductor wafer W is tilted in the wafer cassette. Therefore, assuming that the semiconductor wafer W is inclined at an angle θ with respect to the XY plane, the distance on the Y axis between the center C and the contact point S is (Y _S -Y _C ) / Cosθ. From the Pythagorean theorem, (Y _S -Y _C ) ² X _S ² + cos ² θ = R ^{2, and} thus Y _C = Y _S ^{+ cosθ · √ (R 2 -X} S 2) ······· Further, when the Z-coordinate of the contact point S and _{Z S, Y D -Y S cosθ} = √ {(Y D -Y S) 2 + Z _S ² ｝ ...

3. The coordinates (X _D , Y _D ) of the contact point D between the front side domain 4 and the semiconductor wafer W are obtained. The distance between the wafer center C and the contact point D corresponds to the radius R of the semiconductor wafer W. Here, the distance on the Y axis between the center C and the contact point D is (Y _D -Y _C ) / co.
sθ. From the Pythagorean theorem, (Y _D −Y _C ) ² X _D ² + cos ² θ = R ² is used by using a right-angled triangle having the center C and the contact point D as hypotenuses. Here, when the semiconductor wafer W contacts the inner edge of the front side domain 4 as shown in FIG. 2, X _D = x 3 may be substituted into the equation. Further, the contact point D is due to the front side domain within 4, a Y _D ≦ y11 ·······.

4. Find Y _D. (1) When the contact point D of the semiconductor wafer W with the front side domain 4 is the inner edge of the front side domain 4 as shown in FIG. 2, solving the above equations and the simultaneous equations yields two solutions. And the larger value is selected.

[0026] _{Y D = Y S + √ [} 2R 2 -x3 2 -X S 2 + 2√ {(R 2 -X S 2) (R 2 -x3 2)} - Z S 2] ····· If ... the value of Y _D obtained from equation of Y _D ≧ y11, since the contact point D is located on the front side domain within 4, Y
_D ≦ y11 (expression). Therefore, in this case, Y _D = y 11
(Constant). The value of Y _D obtained from expression Y _D <
For y11, as Y _D, using the calculated value obtained by the formula described above. (2) When the contact point D is the front edge of the front side domain 4 as shown in FIG. 3, Y _D = y 11.

5. A dimension M in the Y-axis direction between a contact point S of the semiconductor wafer W with the rear side domain 5 and a contact point D with the front side domain 4 is determined. M = Y _D -Y _S

6. A dimension L in the Y-axis direction between the contact point S and the front end of the semiconductor wafer W is determined. L = R cos θ + Y _C −Y _S

[0029] obtaining the tilting amounts Lt to the bottom side of the front end F _L of the semiconductor wafer WL arranged on the top side of 7.1 teeth. Point D _L and point F _L in FIG.
A right triangle to hypotenuse the line connecting, the right-angled triangle having the hypotenuse the line connecting the points D _L and the point S _L is similar figures. _{Thus, Lt: Z S (L)} = L L -M L: a M _L becomes, therefore _{Z S (L) · (L} L -M L) Lt = M L.

8. Request tilting amounts Rt to the top side of the front end F _R of the semiconductor wafer WR disposed on the bottom side of the first tooth. A right-angled triangle whose hypotenuse is a line connecting the points D _M and F _M in FIG. 1, a point D _M and a point S
A right-angled triangle with the line connecting _M as the hypotenuse is similar.
_{Therefore, Rt: Z S (R)} = L R -M R: a M _R, and the thus _{Z S (R) · (L} R -M R) Rt = M R.

When the semiconductor wafer W is accommodated in a wafer cassette satisfying the above expression T> (Lt + Rt), and the cassette is placed vertically, the width z11 of the support groove is set in accordance with the SEMI standard as described above. It is stipulated, and its dimensions are very large compared to the thickness of the semiconductor wafer. Therefore, when the wafer cassette is placed vertically, the semiconductor wafer accommodated in the supporting groove is easily tilted in the groove even by a slight impact. At this time, in the present invention, the thickness T of the wafer 8 at the front end of the teeth 8 in the front side domain 4 is T> (Lt +
Rt), the semiconductor wafers WL and W arranged on the top side and the bottom side with one tooth interposed therebetween.
Even when Rs are tilted in a direction to approach each other, the front ends of the wafers WL and WR do not come into contact with each other. Therefore, it is possible to completely prevent the semiconductor wafer from being damaged by the contact.

In order to satisfy the condition of T> (Lt + Rt) in the specification of the cassette conforming to the SEMI standard, in order to satisfy the condition of T> (Lt + Rt), the wafer contact edge portion of the front side domain opposite to the wafer mounting surface of each tooth. It is preferable that the tooth having a ridge has a thickness T.

In order to minimize contamination of the semiconductor wafer due to contact with the ridge, it is preferable that the ridge has a top surface that is in point contact with the semiconductor wafer.
Examples of the mode include a case where the cross section of the ridge is substantially trapezoidal, and a case where the cross section of the ridge is substantially semicircular.

[0034] Further, a projection may be provided at a wafer contact edge portion of the front side domain opposite to the wafer mounting surface of each tooth, and the thickness of the tooth including the projection may be T. It is preferable that the projection also has a top surface shape that makes point contact with the semiconductor wafer. For example, it is preferable that the projection has a columnar shape, or that the projection has a hemispherical shape.

Further, by forming the bottom of the supporting groove of the rear side domain into a substantially V-shaped cross section, the inclination angle of the semiconductor wafer can be raised in the vertical direction.

[0036]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments and specific examples of the present invention will be described below in detail with reference to Table 1 and the drawings. Table 1 shows that the radius R of the semiconductor wafer is 150 mm, and the height y11 of the front end of the front side domain is 8
The upper limit value of the thickness T at the contact edge of the tooth at which the front edge of the adjacent wafer comes into contact with the inner edge of the front side domain at the same time when the semiconductor wafer contacts the inner edge of the front side domain at 0 mm Falling amount L
The calculation results based on specific numerical values of t and Rt are shown. In addition,
The values of r and Z _S in FIG. 2 were changed among the specified values listed in the specific examples 1 and 2 in the table.

[0037]

[Table 1]

In the first specific example, the values of Y _D calculated by the formulas by substituting each numerical value are 82.44 mm and 82.3.
8 mm, which is larger than the value of y11. Therefore, Y
_{When D} = y11, that is, 80 mm, the values of M and L were obtained, and the values of Lt and Rt were calculated.
9 mm and Rt = 1.98 mm. Therefore, the thickness T of the teeth at the contact edge of the semiconductor wafer is set to 0.99+
If it is set to a value larger than 1.98 = 2.97 mm,
Contact between adjacent semiconductor wafers can be completely avoided.

Similarly, in Example 2, Y _D was set to 80 mm because the value of Y _D calculated by the formula by substituting each numerical value was larger than the value of y 11. As a result of calculation, L
t = 0.95 mm, Rt = 0.95 mm, and the thickness T of the teeth at the semiconductor wafer contact edge is 0.95+
If it is set to a value larger than 0.95 = 1.90mm,
Contact between adjacent semiconductor wafers can be completely avoided.

Next, a specific embodiment of the wafer cassette satisfying the condition of T> Lt + Rt will be described with reference to the illustrated embodiment. FIG. 4 is an exploded perspective view showing a wafer cassette of the semiconductor wafer packaging container according to the first embodiment of the present invention, and FIG. 5 is an enlarged perspective view of a support groove formed in the wafer cassette.

The wafer cassette 1 includes a top domain 2 serving as a top plate when the semiconductor wafer is placed in a horizontal posture, a bottom domain 3 serving as a bottom, and the top and bottom domains having a predetermined width. Left and right front side domains 4, connecting the two at the peripheral center
4 and the top and bottom domains 2, which form the bottom when the semiconductor wafer is placed vertically so that it is in a vertical position.
And a pair of left and right rear side domains 5 and 5 arranged side by side at an interval connecting the three. Accordingly, the top and bottom domains 2 and 3 are connected at a predetermined interval to the four side domains of the left and right front side domains 4 and 4 and the left and right rear side domains 5 and 5 in a posture in which they are placed horizontally. All of these side domains form an opening communicating inside and outside.

Each of the top domain 2 and the bottom domain 3 has a form conforming to the SEMI standard described above.
Except for the five portions, each of the side domains 4 and 5 has a substantially disk shape in which two notches 2a and 3a are formed on the front side, which is the insertion side of the semiconductor wafer. The notches 2a and 3a are strictly defined by the SEMI standard in order to ensure the passage of the detection light for detecting the attitude of the wafer cassette. For example, the intersection point O 'of the shoulder is shown in FIG. The distance between the center line X extending right and left passing through the center O of the top domain 2 and the center line Y extending before and after passing the center O of the top domain 2 must be within 112.5 mm. ing.

The opposing surfaces of the top domain 2 and the bottom domain 3 are substantially flat surfaces.
When the wafer cassette 1 is placed vertically, in order to ensure stability, left and right leg portions 6 are integrally formed on the rear edges of the top and bottom domains 2 and 3 opposite to the side where the semiconductor wafer is inserted. Have been.

On the other hand, the left and right side domains 4 and 5 are mirror-finished, and the inner surface thereof has an arc shape having a diameter substantially equal to the diameter of the semiconductor wafer to be accommodated. On the inner surface in the circumferential direction of the front side domain 4, a large number of plate-like teeth 8 having a predetermined thickness are extended at predetermined intervals in a direction parallel to the top and bottom domains 2 and 3. A support groove 7 for supporting the semiconductor wafers in parallel between the adjacent teeth 8 is formed.

The support groove 7 has a groove bottom at approximately the center of the groove width,
One is orthogonal bottom surface 7a orthogonal to the teeth 8
And the other is formed on an inclined bottom surface 7 b inclined with respect to the teeth 8. In addition, the inclined bottom surface 7
The groove side surface 7c continuous with b constitutes a wafer mounting surface when the wafer cassette 1 is placed horizontally. When the wafer cassette 1 is placed horizontally, the groove side surface 7d on the opposite side to the wafer mounting surface is extended by a ridge 8a having a substantially trapezoidal cross section along the front edge which is the contact edge of the semiconductor wafer W. Has been established. The groove side 7 opposite to the wafer mounting surface 7
d may not be parallel to the top and bottom domains 2 and 3 but may be slightly inclined.

The projecting dimension of the ridge 8a is determined by the thickness T of the tooth 8 including the ridge 8a at the front edge.
Is set to a value that satisfies T> Lt + Rt. here,
The Lt a quantity falling to the bottom side of the front end F _L of the semiconductor wafer WL arranged on the top side of one of the teeth 8, Rt is the semiconductor wafer WR disposed on the bottom side of said one tooth 8 a tilting amounts Rt to the top side of the front end F _R.

Further, on the inner surface of the rear side domain 5,
Numerous tapered plate-shaped teeth 10 are provided at predetermined intervals in a direction parallel to the top and bottom domains 2 and 3, and support recesses for supporting semiconductor wafers in parallel between the adjacent teeth 10 are provided. The groove 9 is formed. As shown in FIG. 6, the supporting concave groove 9 is located below when the semiconductor wafer W is placed horizontally, and the groove side surface 9a serving as the mounting surface of the semiconductor wafer is formed in parallel with the top and bottom domains 2 and 3. Have been. On the other hand, the groove side surface 9b opposite to the wafer mounting surface when the semiconductor wafer W is placed horizontally is inclined so as to increase the groove width as the depth of the concave groove 9 becomes shallower. The bottom surface of the concave groove 9 is formed into a first inclined bottom surface 9c in which a side continuous with the wafer mounting surface 9a is divided into two approximately at the center of the approximate groove width, and the wafer is formed following the first inclined bottom surface 9c. An orthogonal bottom surface 9d orthogonal to the mounting surface 9a is formed. Furthermore, the orthogonal bottom surface 9d and the groove side surface 9
b, a second inclined bottom surface 9e is formed.

The groove width z11 of each of the support groove 7 formed in the front side domain 4 and the support groove 9 formed in the rear side domain 5 is defined by the SEMI standard. The dimension is set to be slightly less than 10 times the thickness of the semiconductor wafer W. Therefore, when the wafer cassette 1 accommodating the semiconductor wafer W is placed vertically, the groove width z11 of the support grooves 7, 9 is set to be extremely large as compared with the thickness of the semiconductor wafer W. Is tilted in the support grooves 7, 9 even by a slight impact.

[0049] For example housed in the supporting groove 9, 9 adjacent the semiconductor wafer WL, when tilted in the direction of WR approach each other, they semiconductor wafer WL, front end F _R of WR, F _L is closest This is because the contact point S _R on the left side of FIG. 6, that is, the bottom side domain of the semiconductor wafer WR on the bottom side is the first inclined bottom surface 9.
There the boundary between the c and the perpendicular bottom surface 9d, a case where the contact point S _L in the bottom side domain of the top side of the semiconductor wafer WL is in the orthogonal bottom 9d and the boundary portion between the second inclined bottom surface 9e. That is, the semiconductor wafers WL, W
When the contact points S _R and S _L of the R with the respective rear side domains are farthest apart, the front ends F _R and F _L of the semiconductor wafers WL and WR are closest.

As shown in FIG. 3, the semiconductor wafer W tilted in the support grooves 7, 9 is
Contact with the front edge of the tooth 8 of the first. At this time, a ridge 8a is extended from the front edge so that the thickness T of the teeth 8 is reduced to the adjacent semiconductor wafers WL and W.
R of wafer front ends F _R and F in directions approaching each other.
_Since the inclinations Rt and Lt at _L are set to be larger than the sum of the inclinations Rt and Lt, the front ends F _R and F _L do not come into contact with each other to damage the wafers WL and WR.

Instead of the ridge 8a having a substantially trapezoidal cross section, a semicircular ridge 8b having a semicircular cross section can be used as shown in FIG. In this case, when the semiconductor wafer falls on the same semicircular ridge 8b and comes into contact with the same ridge 8b,
Since the semicircular ridge 8b has no angular portion, there is little danger of damage to the semiconductor wafer, and the semiconductor wafer only makes point contact with the semicircular ridge 8b. Contamination due to contact with water is also reduced.

The tilted semiconductor wafer is used for the teeth 8.
In the case of contact with the corner portion of the cylindrical shape, a cylindrical projection 8c as shown in FIG. 8 or a hemispherical projection 8 as shown in FIG.
d, and the thickness T of the teeth 8 in the same portion is
It can also be set to a value that satisfies the condition of T> Lt + Rt.

Further, as shown in FIG. 2, the contact edge of the semiconductor wafer is
In the case of the inner edge of the tooth 8, as shown in FIG.
e is extended. The contact point D in the front side domain 4 of the semiconductor wafer W can be calculated as described above. Therefore, the position of the contact point D may be calculated in advance, and the ridge 8e may be formed only near the contact point D.

Further, the support groove 9 formed in the rear side domain 5 can be a support groove 9 'shown in FIG. The support groove 9 ′ has a bottom surface that is divided into two approximately at the center of the groove width, and the first and second grooves are inclined to face each other.
It has a V-shaped cross section composed of inclined bottom surfaces 9f and 9g. Therefore, the semiconductor wafer W accommodated in the support groove 9 is supported at the boundary between the first and second inclined bottom surfaces 9f and 9g when the cassette 1 is placed vertically.

It is needless to say that the wafer cassette of the present invention does not deviate from the SEMI standard in any of the embodiments and modifications and conforms to the SEMI standard.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view schematically showing a part of a wafer cassette for explaining a formula of the present invention.

FIG. 2 is a front view schematically showing a part of the wafer cassette.

FIG. 3 is a front view schematically showing a part of another wafer cassette.

FIG. 4 is an overall perspective view of a wafer cassette according to an embodiment of the present invention.

FIG. 5 is an enlarged perspective view of a front side domain in the wafer cassette.

FIG. 6 is a partial sectional view of the wafer cassette.

FIG. 7 is an enlarged perspective view of a front side domain according to a first modified example of the present invention.

FIG. 8 is an enlarged perspective view of a front side domain according to a second modified example of the present invention.

FIG. 9 is an enlarged perspective view of a front side domain according to a third modified example of the present invention.

FIG. 10 is an enlarged perspective view of a front side domain according to a fourth modified example of the present invention.

FIG. 11 is a partial sectional view of a wafer cassette according to a fifth modification of the present invention.

FIG. 12 is a schematic front view of a wafer cassette for explaining the SEMI standard.

FIG. 13 is an explanatory diagram of a shape of a wafer supporting groove according to the SEMI standard.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Wafer cassette 2 Top domain 2a Notch 3 Bottom domain 3a Notch 4 Front side domain 5 Rear side domain 6 Leg 7 Support concave groove 7a Orthogonal bottom surface 7b Inclined bottom surface 7c Groove side surface (mounting surface of semiconductor wafer) 7d Groove side surface 8 Teeth 8a ridge 8b semicircular ridge 8c cylindrical projection 8d hemispheric projection 8e ridge 9,9 'support concave groove 9a groove side surface 9b groove side surface 9c first inclined bottom surface 9d orthogonal bottom surface 9e second inclined bottom surface 9f first inclined bottom surface 9g 2nd inclined bottom 10 teeth

 ──────────────────────────────────────────────────続 き Continued from the front page (72) Inventor Satoshi Fukuhara 1200 Manda, Hiratsuka-shi, Kanagawa Prefecture, Komatsu Ltd.

Claims (10)

[Claims] 1. A standardized wafer which is accommodated in a semiconductor wafer packaging container and has teeth forming support grooves for supporting a plurality of semiconductor wafers in parallel at predetermined intervals in front and rear side domains. A wafer cassette, wherein a thickness T of the teeth at a semiconductor wafer contact edge portion of the front side domain is set to a value satisfying the following expression. T> (Lt + Rt) where, Lt: the amount of fall (mm) of the front end of the semiconductor wafer disposed on the top side of the teeth at the front end to the bottom side of the semiconductor wafer disposed at the bottom side of the one tooth. The amount of fall to the top side at the front end (m
m). 2. A ridge is provided at a wafer contact edge of the front side domain opposite to a wafer mounting surface of each tooth, and the thickness of the tooth including the ridge is T.
The wafer cassette according to claim 1, wherein 3. The wafer cassette according to claim 2, wherein the ridge has a top surface shape that makes point contact with the semiconductor wafer. 4. The ridge has a substantially trapezoidal cross section.
The wafer cassette as described in the above. 5. The ridge is substantially semicircular in cross section.
The wafer cassette as described in the above. 6. A tooth is formed at a wafer contact edge of the front side domain opposite to a wafer mounting surface of each tooth, and the thickness of the tooth including the protrusion is T.
The wafer cassette according to claim 1, wherein 7. The wafer cassette according to claim 6, wherein the projection has a top surface shape that makes point contact with the semiconductor wafer. 8. The wafer cassette according to claim 7, wherein said projection has a cylindrical shape. 9. The wafer cassette according to claim 7, wherein the projection has a hemispherical shape. 10. The wafer cassette according to claim 1, wherein the support groove of the rear side domain has a bottom surface formed in a substantially V-shaped cross section.