JPH11312790A - Field effect transistor, semiconductor switch and semiconductor phase shifter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide devices such as a semiconductor switch, a semiconductor phase shifter and others, which are reduced in size and improved in characteristics. SOLUTION: When a pinch-off voltage is applied to a gate G of pinch-off a field effect transistor(FET), a capacitive impedance between a drain D and a source S becomes high (off-state), a resonant inductor line 20a regulated in line length and line width so as to parallel-resonate with the capacitance of the FET is provided, whereby the FET becomes nearly open in impedance from a viewpoint of the source S. Therefore, a path from an input terminal 1 to an output terminal 2 is shut off. Meanwhile, when a voltage of 0 V is applied to the gate G of the FET, a resistive impedance between the drain D and the source S becomes low (on-state), both the edges of the resonant inductor line 20a are excited in the same phase, so that a transmission line is loaded with a stub, whose tip is open and which is half as equivalently long as the resonant inductor line 20a. At this point, the stub functions as a reflection source to some extent, so that a transmission line deteriorates in reflection characteristics in transit, but signals inputted through the input terminal 1 are hardly attenuated and appear through the output terminal 2 to pass through the path.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field effect transistor (hereinafter, referred to as an FET), a semiconductor switch using the same as a switching element, and a semiconductor phase shifter.

[0002]

2. Description of the Related Art Semiconductor switches and semiconductor phase shifters are widely used in various devices such as a microwave band and a millimeter wave band. These semiconductor devices can be configured using switching elements such as FETs. The device configured in this way is applied to the fields of mobile communication, in-vehicle communication, satellite communication, and the like.

Conventional example 1. FIG. 15 is a configuration diagram showing a conventional semiconductor switch, which has an equivalent circuit configuration called a single-pole double-throw switch (SPDT switch). In the figure,
1 is an input terminal, 21 and 22 are output terminals, 3 and 4 are resonance inductor lines, and Q1 and Q2 are FETs. The configuration of this figure is described in “X-band monolithic SPDT switch composed of a pair of source electrode shared FETs”, Iyama et al., Proc. 3-2
09 is disclosed.

[0004] The SPDT switch shown in FIG.
It has a function of switching a signal output terminal by passing / blocking a signal path between the input terminal 1 and the output terminal 21 or 22. The passage / cutoff of the signal path is realized by two FETs Q1 and Q2 in which two resonance inductor lines 3 and 4 are loaded in a loop between a drain electrode (D) and a source electrode (S). The above FE
A bias is externally applied to each of TQ1 and Q2, but a bias circuit and the like for that purpose are not shown here.

Next, the electrode structure of the FETs Q1 and Q2 will be described. FIG. 16 shows the FE in Conventional Example 1.
FIG. 3 is a plan view showing a configuration around TQ1 and Q2. In the figure, 5 is a drain electrode finger, 6 is a source electrode finger, 7 is a gate electrode finger, 8 is a gate connection wiring, 9
Is an air bridge. The electrode structures of the FETs Q1 and Q2 include a drain electrode finger 5 and a source electrode finger 6.
Are formed in the shape of a finger cross, and the drain electrode fingers 5
Between the gate electrode fingers 7 and the source electrode fingers 6
Are arranged. The gate electrode fingers 7 are mutually connected by a gate connection wiring 8 and are drawn out. Further, in order to avoid competition and interference with the gate connection wiring 8, the source electrode finger 6 is led out through the air bridge 9.

Next, this semiconductor switch, ie, SPD
The operation of the T switch will be described. First, FET Q1
A pinch-off voltage is applied to the gate (G) of the FET Q2.
FIG. 1 shows an equivalent circuit when 0 V is applied to the gate (G) of FIG.
FIG. In this state, the drain (D) of the FET Q1
And the source (S) are capacitive high impedance (OFF
State) between the drain (D) and the source (S) of the FET Q2.
It has become. By providing the resonance inductor line 3 so as to resonate in parallel with the capacitance exhibited by the FET Q1, the impedance when the FET Q1 side is viewed from the transmission line branch portion is substantially open. As a result, the path from the input terminal 1 to the output terminal 21 is cut off.

On the other hand, both ends of the resonance inductor line 4
Since they are connected via a low resistance, both ends are excited in substantially the same phase. As a result, two open-ended stubs each having a length approximately half the entire length of the resonance inductor line are equivalently loaded on the transmission line in parallel. Although this stub serves as a reflection source, the reflection characteristics in the passing state deteriorate, but the signal incident from the input terminal 1 passes through the output terminal 22 with almost no attenuation.

FIG. 18 schematically shows the state of the switches when the FETs Q1 and Q2 are driven in this manner. F
The series-loaded unit switch SW1 composed of the ETQ1 and the resonance inductor line 3 is turned off, and the FET Q
The unit switch SW2 of the series loading composed of the resonance inductor line 4 and the resonance inductor line 4 is in the passing state, and the semiconductor switch as a whole is switched to the output terminal 22 side.

Next, the applied bias is reversed to make the FET
When 0 V is applied to the gate (G) of Q1 and a pinch-off voltage is applied to the gate (G) of FET Q2, each FE
As a result of the reversal of the operations of TQ1 and Q2, the semiconductor switch as a whole is switched to the output terminal 21 side. In this way, a switch having a function of switching the output destination of the incident signal to two ways (that is, outputting the incident signal to one of the two paths) is realized.

Conventional example 2. By applying a semiconductor switch, a device having a further different function is realized. FIG. 19 shows a metal pattern structure of a semiconductor phase shifter called a switched line type phase shifter constituted by using SPDT switches, which is referred to as “X band 5-bit monolithic GaAsF”.
ET phase shifter ", Iyama et al., 1984
National Radio Division Competition, pp. No. 1-143.

The phase shifter shown in FIG. 1 comprises an input line 10, an output line 11, two SPDT switches 16 and 17, a reference transmission line 18, and a delay transmission line 19. The SPDT switch 16 on the input side connects the input line 10 to the reference transmission line 18 or the delay transmission line 1.
9 is a means for selectively connecting to any one of. on the other hand,
The output-side SPDT switch 17 is a means for selectively connecting the output line 11 to either the reference transmission line 18 or the delay transmission line 19. The delay transmission line 19 has a longer line length than the reference transmission line 18, and
When the switches 16 and 17 are both switched to the reference transmission line 18 side, the propagation delay in the phase shifter is greater when the switches are switched to the delay transmission line 19 side.

The above SPDT switches 16 and 17
Are connected to the FET Q in the same manner as the unit switches SW1 and SW2 constituting the SPDT switch described above.
3 to Q6 and the resonance inductor lines 12 to 15. That is, the structure in which the FET Q3 and the resonance inductor line 12 are connected in the same manner as in FIG.
16 and the structure in which the resonance inductor line 13 is connected in the same manner as in FIG. 16, the input side SPDT switch 16 is configured by commonly connecting the input line 10 via the drain.

Similarly, a structure in which the FET Q5 and the resonance inductor line 14 are connected in the same manner as in FIG.
The output SPDT switch 17 is configured by commonly connecting the structure in which the resonance inductor line 15 is connected to the output line 11 via the drain, as in FIG. Although a circuit for applying a bias to the four FETs is required, a circuit and the like for this purpose are not shown here.

Next, the operation of the conventional semiconductor phase shifter will be described. First, in a passing state where 0 V is applied to the gates (G) of the FETs Q3 and Q5 and a pinch-off voltage is applied to the gates (G) of the FETs Q4 and Q6, the drains (D) and the sources (S) of the FETs Q3 and Q5 There is a resistive low impedance (ON state) between them, and a capacitive high impedance (OFF state) between the drain (D) and the source (S) of the FETs Q4 and Q6. At a frequency at which the capacitances of the FETs Q4 and Q6 and the resonance inductor lines 13 and 15 resonate in parallel, the input line 10 and the delay transmission line 19
, And between the delay transmission line 19 and the output line 11. On the other hand, since the FETs Q3 and Q5 have low impedance, the signal incident from the input line 10 passes through the reference transmission line 18 and appears on the output line 11.

Next, the bias applied to each FET is reversed. In this case, on the contrary, the connection between the input line 10 and the reference transmission line 18 and the connection between the reference transmission line 18 and the output line 11 are interrupted. At this time,
Since the FETs Q4 and Q6 have low impedance, the signal incident from the input line 10 passes through the delay transmission line 19 and appears on the output line 11. Therefore, by changing the bias voltage applied to the four FETs, S
Switching the passing terminals of the PDT switches 16 and 17,
The delay phase is changed by switching the signal propagation path to operate as a phase shifter.

[0016]

The conventional field-effect transistor, semiconductor switch, and semiconductor phase shifter are constructed as described above. Since the inductor line has a bad effect as a stub, the reflection characteristics and the loss characteristics are reduced. There was a problem of deterioration.

Further, when a long inductor line is required due to a low use frequency or the like, the inductor line is provided so as to protrude outside the FET so as to draw an arc, thereby occupying the device pattern occupation area. However, there was a problem that the size became particularly large.

Furthermore, the resonance inductor line of the SPDT switch serves as a stub to deteriorate the reflection characteristics. In particular, since two SPDT switches are used, multiple reflections occur, and the deterioration of the reflection characteristics becomes remarkable. . Since the magnitude of the multiple reflection is different in principle between the case where the signal passes through the reference transmission line and the case where the signal passes through the delay transmission line, the reflection characteristic changes when the phase is switched.
For this reason, there has been a problem that the reflection loss greatly changes, and the loss fluctuation at the time of phase switching increases.

Further, when the reflection of the phase shifter is large,
When a plurality of phase shifters are connected to form a digital phase shifter having a phase shift amount of 360 degrees, the phase changes due to the influence of multiple reflections, and the phase shift amount characteristics of the digital phase shifter deteriorate. There were challenges.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and a field-effect transistor, a semiconductor switch, and a semiconductor for realizing reduction of reflection, improvement of loss characteristics, improvement of phase shift amount characteristics, or miniaturization. The purpose is to obtain a phase shifter.

[0021]

According to a first field effect transistor of the present invention, a part of an inductor line is formed by an air bridge, which is disposed so as to straddle a source electrode, and one end of the air line is connected to a drain. It is electrically connected to an inductor line provided extending from an electrode, and the other end is connected to a source electrode.

A second field-effect transistor according to the present invention is configured such that a part of an inductor line provided to extend from a drain electrode is constituted by an air bridge, and is arranged so as to straddle a gate line. It is.

The third field-effect transistor according to the present invention has a pattern in which the source electrode portion is cut inside.

The fourth field-effect transistor according to the present invention is constructed by combining a plurality of gate, source and drain electrode fingers.

In a fifth field-effect transistor according to the present invention, an air bridge constituting an inductor line, which is disposed so as to straddle the source electrode, is connected to the source electrode via a projecting pattern provided on the source electrode. Things.

In a sixth field effect transistor according to the present invention, a part of the inductor line is constituted by an air bridge,
This is arranged so as to straddle the source electrode, one end of which is electrically connected to a line extending from the drain electrode and the other end is connected to the source electrode finger.

A seventh field-effect transistor according to the present invention has at least two air bridges constituting an inductor line, and one of the air bridges arranged so as to straddle a source electrode. Are arranged so as to straddle the drain electrode, are connected to each other to form a spiral inductor line, and are arranged so as to surround the electrode finger of the field effect transistor.

An eighth field-effect transistor according to the present invention has a spiral inductor line arranged so as to surround a plurality of electrode fingers, and an electrode arranged so as to straddle the inductor line. A drain electrode or a source electrode is connected to the outside via an air bridge.

In a ninth field effect transistor according to the present invention, a channel structure is formed between an inductor line and a drain electrode finger or a source electrode finger of a FET, and a gate electrode finger is provided.

In a tenth field effect transistor according to the present invention, an air bridge forming a part of an inductor line is disposed so as to straddle a source electrode finger or a drain electrode finger. An island pattern is provided between the fingers via a gate electrode finger, and the island pattern and the air bridge are connected.

An eleventh field effect transistor according to the present invention has a plurality of strip conductors, and a channel is provided between an inductor line connected through an air bridge and a drain electrode finger or a source electrode finger of the field effect transistor. A gate electrode finger is provided while forming a structure, and a channel structure is formed between the strip conductors adjacent to each other in a spiral shape, and a gate electrode finger is provided.

A semiconductor switch according to the present invention includes three or more switch input / output lines provided for inputting / outputting a signal, and a plurality of field effect transistors which are opened / closed complementarily to each other. One of the source electrodes is commonly connected to one of the switch input / output lines, the other is individually connected to the other switch input / output lines, and at least one of the plurality of field-effect transistors is connected to the first to the above-mentioned first to fourth input / output lines. It has a feature of an eleventh field effect transistor.

A semiconductor phase shifter according to the present invention includes an input line for inputting a signal, a plurality of transmission lines having different line lengths, an output line for outputting a signal, and an input line. A first semiconductor switch which is selectively connected to the transmission line, and which is opened and closed in synchronization with the first semiconductor switch so that a signal input from the input line passes through one of the transmission lines and appears on the output line. A second semiconductor switch for switching connection to any one of the transmission lines, wherein a switch input / output line related to common connection among the switch input / output lines of the first and second semiconductor switches is connected to an input line or an output line. The other switch input / output lines of the first and second semiconductor switches are respectively connected to one of the transmission lines, and at least one of the first and second semiconductor switches is connected. On the other hand but which is a circuit configuration of the first semiconductor switch described above.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a plan view showing a structure of a field effect transistor (hereinafter, referred to as an FET) according to a first embodiment of the present invention. In the figure, 1 is an input terminal, 2 is an output terminal, 5 is a drain electrode finger, 6 is a source electrode finger, 7 is a gate electrode finger, 8 is a gate wiring, 9 is an air bridge, and 20a is a resonance inductor line (inductor line). ), 201 is a first strip conductor (strip conductor), 202 is a first air bridge (air bridge),
203 is a second strip conductor (strip conductor), 20
4 is the second air bridge (air bridge), 211 is the first
Connection pads.

In the FET shown in FIG. 1, a drain electrode finger 5 and a source electrode finger 6 are formed in a finger crossing manner in the same manner as the conventional FETs Q1 to Q6 shown in FIGS. A gate electrode finger 7 is arranged between the electrode finger 5 and the source electrode finger 6, and the gate electrode fingers 7 are connected to each other by a gate connection wiring 8 and are led out. Further, in order to avoid competition and interference with the gate connection wiring 8, the source electrode finger 6 is led out through the air bridge 9.

Here, the resonance inductor line 20a applied to the FET according to the first embodiment includes a first strip conductor 201, a first air bridge 202, a second strip conductor 203, and a The first strip conductor 201 is connected to a drain electrode (D). On the other hand, the second air bridge 204 is disposed so as to straddle the source electrode (S), and its end is
It is connected to the source electrode (S) via the first connection pad 211.

Next, the operation will be described. When a pinch-off voltage is applied to the gate (G) of the FET, a capacitive high impedance (OFF state) is established between the drain (D) and the source (S) so that the FET resonates in parallel with the capacitance exhibited by the FET. By providing the resonance inductor line 20a by adjusting the line length and line width of the source (S)
The impedance as viewed from the FET side is almost open. Therefore, the path from the input terminal 1 to the output terminal 2 is cut off.

On the other hand, when 0 V is applied to the gate (G) of the FET, the resistance between the drain (D) and the source (S) is low (ON state), and the resonance inductor line 20a Are excited almost in-phase,
Equivalently, an open-end stub having a half length of the entire length of the resonance inductor line 20a is loaded on the transmission line. At this time, although the stub serves as a reflection source to some extent, the reflection characteristics in the passing state deteriorate, but the signal incident from the input terminal 1 passes through the output terminal 2 with almost no attenuation.

As described above, according to the first embodiment, a part of the pattern of the resonance inductor line 20a extends three-dimensionally over the electrode outside the FET.
The pattern occupancy can be reduced as compared with the conventional loop-shaped device, and the effect of reducing the size of the device can be obtained.

Embodiment 2 FIG. 2 is a plan view showing a field effect transistor (FET) structure according to a second embodiment of the present invention. The difference from the FET structure of the first embodiment shown in FIG. 1 is that the resonance inductor line (inductor line) 20b is cascaded without using the first air bridge 202 and the second strip conductor 203. First strip conductor 201 and second air bridge 204
Other configurations and operations are the same as those of the first embodiment, and the same or corresponding components are denoted by the same reference numerals or reference symbols, and redundant description will be omitted.

As described above, according to the second embodiment, the structure is as simple as omitting the first air bridge. As a result, in addition to the advantages of the first embodiment, the manufacturing is facilitated. There is.

Embodiment 3 FIG. 3 is a plan view showing a field effect transistor (FET) structure according to Embodiment 3 of the present invention. The difference from the FET structure of the first embodiment shown in FIG. 1 is that the source electrode (S) is cut into the inside, and the second air bridge 204 of the resonance inductor line (inductor line) 20c is formed. The point is that the length can be shortened. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the third embodiment, the short air bridge compared to the long air bridge reduces the possibility of disconnection and the possibility of contact with the source electrode (S) in the middle of the air bridge. Therefore, the first embodiment
In addition to the advantages of the FET structure described above, there is an advantage that the fabrication is easy.

Embodiment 4 FIG. FIG. 4 is a plan view showing a field effect transistor (FET) structure according to a fourth embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the number of gate, source and drain electrode fingers constituting the FET is large. In the FET shown in FIG. 4, three drain electrode fingers 5 and three source electrode fingers 6 and five gate electrode fingers 7 are used. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the fourth embodiment, by changing the number of electrode fingers,
Time capacity and ON resistance can be changed.
The width of the entire FET can be changed. As a result, it is possible to arbitrarily select and optimize the cut-off frequency and the pass-through attenuation.
a) The effect of reducing the electrical reflection generated at the connection with the external line can be obtained.

Embodiment 5 FIG. FIG. 5 is a plan view showing a field effect transistor (FET) structure according to a fifth embodiment of the present invention. The difference from the FET structure of the first to fourth embodiments is that the second air bridge 204, which is arranged so as to straddle the source electrode, is provided on the source electrode. ) 2
It is characterized in that it is connected to the source electrode (S) via the gate 21. Thereby, the line length of the resonance inductor line (inductor line) 20d can be increased on the source electrode (S) side. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the fifth embodiment, since the protruding pattern source electrode 221 can be used as a part of the inductor line 20d, an effect that a larger inductance can be realized is obtained.

Embodiment 6 FIG. FIG. 6 is a plan view showing a field effect transistor (FET) structure according to Embodiment 6 of the present invention. The difference from the FET according to the first embodiment is that the resonance inductor line (inductor line) 2
0e are the first strip conductors 2 connected to each other
01, first air bridge 202, second strip conductor 2
In addition to the third strip conductor (strip conductor) 205 in addition to the third strip conductor 205 and the second air bridge 204, the third strip conductor 205 is connected to the source electrode finger 6. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the sixth embodiment, since the source electrode finger 6 connected to the third strip conductor 205 can be used as a part of the resonance inductor line 20e, a larger inductance can be realized. A possible effect is obtained.

Embodiment 7 FIG. FIG. 7 is a plan view showing a field effect transistor (FET) structure according to a seventh embodiment of the present invention. Compared to the FET according to the sixth embodiment, the resonance inductor line (inductor line) 20f
Are configured longer. That is, the resonance inductor line 20f includes the first strip conductor 201, the first air bridge 202, the second strip conductor 203, the second air bridge 204, the third strip conductor 205, and the third air bridge ( Air bridge) 20
6, a fourth strip conductor (strip conductor) 207, a fourth air bridge (air bridge) 208, and a fifth strip conductor (strip conductor) 209. The terminal of the fifth strip conductor 209 is a source electrode (S )It is connected to the. The resonance inductor line 20f is formed spirally by using an air bridge without contacting the electrode of the FET in the middle of the line, and is arranged so as to surround the electrode finger of the FET. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the seventh embodiment, since the resonance inductor line 20f can be arranged near the FET electrode without protruding from the FET, a larger inductance can be obtained without significantly increasing the area occupied by the pattern. Is achieved.

Embodiment 8 FIG. FIG. 8 is a plan view showing a field effect transistor (FET) structure according to an eighth embodiment of the present invention. The difference from the FET according to the seventh embodiment is that the resonance inductor line (inductor line) 2
0g, the second strip conductor 203, the second air bridge 2
04, the sixth strip conductor (strip conductor) 2010 is used instead of the dependent connection portion of the third strip conductor 205, and the sixth strip conductor 2010
The source electrode (S) is connected to the source electrode air bridge (electrode air bridge) while avoiding contact between the electrode and the source electrode (S).
This is a point connected to an external line via. Since the source electrode air bridge 23 is wide and short, it is easy to manufacture and hardly affected by mechanical effects such as vibration and impact. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the eighth embodiment, the reliability and the mass productivity can be improved without impairing the advantage of miniaturization as described in the FET configuration of the seventh embodiment. Is obtained.

Embodiment 9 FIG. FIG. 9 is a plan view showing a field effect transistor (FET) structure according to a ninth embodiment of the present invention. In the FET according to the eighth embodiment, the case where only the source electrode portion is changed to the air bridge is shown. However, the present invention is not limited to this. As shown in FIG. 9, the resonance inductor line (inductor line) 20h and the third A seventh strip conductor (strip conductor) 2011 is used in place of the subordinate connection portion of the strip conductor 205, the third air bridge 206, and the fourth strip conductor 207, and the contact between the seventh strip conductor 2011 and the drain electrode (D). Is that the drain electrode (D) is connected to an external line via a drain electrode air bridge (electrode air bridge) 24. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the ninth embodiment, when an FET is used as a switching device, equivalent functions can be obtained even if the drain electrode (D) and the source electrode (S) are exchanged as is well known. Therefore, even in this case, the FE according to Embodiment 8 described above can be obtained.
An effect equivalent to T is obtained.

Embodiment 10 FIG. FIG. 10 is a plan view showing a field effect transistor (FET) structure according to Embodiment 10 of the present invention. The configuration of the resonance inductor line 20a is the same as that of the FET according to the first configuration, but a channel structure is formed between the first strip conductor 201 forming the resonance inductor line 20a and the drain electrode finger 5 of the FET. And a gate electrode finger 71 is provided. The other configuration is the same as that of the first embodiment, and a duplicate description will be omitted.

Next, the operation will be described. First, when a pinch-off voltage is applied to the gate (G), the FET has a capacitive high impedance (OFF state) between the drain (D) and the source (S). At the same time, the impedance between the first strip conductor 201 and the drain electrode finger 5 of the FET also becomes high, and the first strip conductor 201 functions as an independent line element. Therefore, F
By providing the resonance inductor line 20a so as to resonate in parallel with the capacitance exhibited by the ET, the impedance seen from the FET becomes almost open, and a cutoff state is realized.

Next, the applied bias is reversed to make the FET
When 0 V is applied to the gate (G), the resistance between the drain (D) and the source (S) becomes a low impedance (ON state). In this case, since the channel immediately below the gate electrode finger 71 becomes conductive, the drain electrode finger 5, the source electrode finger 6, the gate electrode finger 71, and the first strip conductor 201 have the same potential. Therefore, the portion where the finger and the strip conductor are provided functions as a one-sided conductor. As a result, the FET functions as a microstrip transmission line as a whole, and a passing state is realized.

As described above, according to the tenth embodiment, when the FET is in the ON state when the applied bias is 0 V, a part of the resonance inductor line arranged along the electrode finger is connected to each electrode finger. As a result of the same potential,
The reflection resulting from the resonance inductor line can be reduced, and the effect of achieving good reflection characteristics while the device is small can be obtained.

Embodiment 11 FIG. FIG. 11 is a plan view showing a structure of a field effect transistor (FET) according to Embodiment 11 of the present invention. F according to the tenth embodiment.
The difference from the ET structure is that the source electrode finger extended conductor 25 connected to the source electrode finger 6 and the air bridge 9 is adjacent to the source electrode finger extended conductor 25 via the gate electrode finger 72 in the form of an island. The island-like conductor 26 of the pattern is provided at the lower part of the second air bridge 204. Further, the second air bridge 204
Are connected to the island-shaped conductor 26 via the second connection pads 271. The other configuration is the same as that of the first embodiment, and a duplicate description will be omitted.

Next, the operation will be described. First, when a pinch-off voltage is applied to the gate (G), between the drain (D) and the source (S) of the FET, between the first strip conductor 201 and the drain electrode finger 5 of the FET, and
Both the source electrode finger extended conductor 25 and the island-shaped conductor 26 have high impedance and function as independent elements.
As in the case of the ET, the cutoff state is realized.

Next, the applied bias is reversed, and the FET
When 0 V is applied to the gate (G), the resistance between the drain (D) and the source (S) is low (ON state), the electrode fingers, the first strip conductor 201, the source The potential between the electrode finger extended conductor 25 and the island-shaped conductor 26 is the same. Therefore, the portion where these fingers and conductors are provided functions as a one-sided conductor, and the FET functions as a microstrip line-like transmission path as a whole, and a passing state is realized.

As described above, according to the eleventh embodiment, in addition to the effect of the tenth embodiment, the air bridge portion can be set to the same potential, so that better reflection characteristics can be realized.

Embodiment 12 FIG. FIG. 12 is a plan view showing a structure of a field effect transistor (FET) according to Embodiment 12 of the present invention. F of the seventh embodiment shown in FIG.
In ET, the number of electrode fingers is increased, and the first strip conductors 201 and F are connected in the same manner as in the eleventh embodiment.
A channel structure is formed between the ET and the drain electrode finger 5, and a gate electrode finger 71 is provided.
Further, a channel structure is formed between the third strip conductor 205 and the source electrode finger 6 of the FET, and a gate electrode finger 73 is provided. A channel structure is formed between the first strip conductor 201 and the fourth strip conductor 207. And a gate electrode finger 74 is provided. Other configurations and operations are the same as those of the first embodiment, and thus redundant description will be omitted.

As described above, according to the twelfth embodiment, when 0 V is applied to the gate (G) of the FET, the resistance between the drain (D) and the source (S) is low (the ON state). In addition, since each electrode finger and each strip conductor can be made to have the same potential, even when the resonance inductor line (inductor line) 20i is formed in a spiral shape and long, reflection can be reduced, and good resonance can be achieved. The effect of realizing the passing state is obtained.

Embodiment 13 FIG. An SPDT switch, which is a kind of a semiconductor switch, can be formed using the FETs described in the first to twelfth embodiments. FIG. 13 shows an FE of the type shown in the eleventh embodiment.
FIG. 36 is a plan view showing a configuration of an SPDT switch according to a thirteenth embodiment of the present invention, which is configured using T. The FETs Q7 and Q8 are provided so that the source electrode (S) is electrically connected to the common input line 10.

Next, the operation will be described. FET Q7,
When the bias applied to one side of Q8 is equivalent to the pinch-off voltage, the FET itself realizes a cutoff function, and an open state is realized near the connection with the source electrode (S). Therefore, the signal propagating through the other FET in the passing state is output without being affected by the FET in the blocking state.

Here, the case where the two FETs are the FETs according to the first to twelfth embodiments of the present invention has been described. However, the present invention is not limited to this, and the FET according to the present invention is used for at least one FET. May be. Further, although FIG. 13 shows only an SPDT switch using two FETs, an SPNT (single-pole multi-throw switch) having three or more FETs and having three or more output lines may be used. Obviously, the same effect is obtained.

As described above, according to the thirteenth embodiment, a SPNT such as a small SPDT switch with low reflection can be realized using the FET structure shown in the first to twelfth embodiments. The effect is obtained.

Embodiment 14 FIG. FIG. 14 is a plan view showing a configuration of a semiconductor phase shifter according to Embodiment 14 of the present invention. In the fourteenth embodiment, a phase shifter based on the principle shown in FIG. 17 includes an SPDT switch (semiconductor switch) 28 composed of FETs Q9 and Q10,
SPDT switch (semiconductor switch) 29 comprising input 11 and Q12, input line 10, reference transmission line 18
1, the delay transmission line 191 and the output line 11. Each FET constituting the SPDT switch is provided such that the source electrode (S) is electrically connected to the common input line 10 or the common output line 11 as described in the description of the thirteenth embodiment. is there. Here, the FETs Q9 to Q12 are the same as those in the twelfth embodiment.
However, the FET configuration according to the other embodiments 1 to 11 may be adopted. Although a circuit for applying a bias to the four FETs is required, a circuit and the like for this purpose are not shown here.

According to this configuration, the resonance inductor line 20 conventionally provided in a loop shape outside the FET is provided.
Since i is provided in a spiral shape so as to surround the gate, source and drain electrode fingers of the FET, it is necessary to use a resonance at a relatively low frequency or to improve the isolation characteristics. Even when providing a long inductor line, the area occupied by the phase shifter pattern can be reduced. In particular, a plurality of F
Since the ET is used at the same time, this effect is further enhanced as compared with the case of a single switch.

Further, in the conventional configuration, the resonance inductor line of the SPDT switch becomes a stub and the reflection characteristics deteriorate, but according to the present invention, when the bias applied to the FET is 0 V, it operates as a resonance circuit. Since the electrode finger becomes a part of the conduction portion (drain-source transmission line) of the FET and the stub effect as a reflection source can be reduced, good reflection characteristics can be realized. As a result, two S
Multiple reflection is reduced between the PDT switches, and the effect of suppressing deterioration of the reflection characteristics is produced. Therefore, loss fluctuation at the time of phase switching can be reduced. In addition, since the reflection of the above-mentioned phase shifter is small, there is an advantage that when a plurality of phase shifters are connected to constitute a multi-bit digital phase shifter, good phase shift characteristics can be maintained.

In the fourteenth embodiment, a line switching type phase shifter having a configuration in which two lines are switched by an SPDT switch has been described.
It is apparent that the same effect can be obtained even with a configuration in which a plurality of lines are switched by the NT switch.

As described above, according to the fourteenth embodiment, a phase shifter that causes a phase delay by selecting and using a plurality of transmission lines having different line lengths by using a semiconductor switch such as an SPNT switch is: F that constitutes this
Resonance inductor line 20 constituting ETQ9-Q12
Since i is provided in a spiral shape so as to surround these electrode fingers, the entire semiconductor transfer can be performed even when the resonance inductor line is required to be used at a low frequency or to improve the isolation characteristics. The effect of reducing the pattern occupation area of the phaser can be obtained. In addition, since the electrode finger that operates as a resonance circuit becomes a part of the conductive portion of the FET and the stub effect serving as a reflection source can be reduced, multiple reflection between two semiconductor switches incorporating these is reduced. Therefore, even when these are connected in multiple stages, the effect of realizing a phase shifter with little deterioration of the phase shift amount characteristic is obtained.

[0075]

As described above, according to the present invention, the first
In the field-effect transistor, a part of the resonance inductor line is formed by an air bridge, which is arranged so as to straddle the source electrode, and one end of which is electrically connected to a line extending from the drain electrode. Since the other end is connected to the source electrode, a part of the resonance inductor line can be formed above the field effect transistor, so that the pattern occupation outside the field effect transistor can be reduced and the size can be reduced.

According to the present invention, the second field-effect transistor is configured such that a part of the line extended from the drain electrode is constituted by an air bridge, and is arranged so as to straddle the gate wiring. , There is an effect that the production becomes easy.

According to the present invention, the third field-effect transistor is configured so that the source electrode portion has a pattern shape cut inside, so that the length of the second air bridge forming the resonance inductor line is reduced. There is an effect that the length can be shortened and the production becomes easier.

According to the present invention, the fourth field-effect transistor is constructed by combining a plurality of gate, source and drain electrode fingers, respectively.
The capacity at the time of FF and the resistance at the time of ON can be changed, and further, the width of the entire field effect transistor can be changed. As a result, it is possible to arbitrarily select the cutoff frequency and the attenuation when passing, and furthermore, it is possible to reduce the electrical reflection generated at the connection with the external line.

According to the present invention, the fifth field-effect transistor is configured such that the air bridge constituting the resonance inductor line disposed so as to straddle the source electrode is connected to the source via the protruding pattern provided on the source electrode. Since it is connected to the electrode, this projecting pattern can also be used as a part of the inductor line. That is, since the air bridge forming a part of the resonance inductor line can be formed above the field effect transistor, the pattern occupation outside the field effect transistor can be reduced and the size can be reduced, and the connection line between the air bridge and the source electrode can be formed. Since the portion can also be used as a part of the inductor line, there is an effect that a larger inductance can be realized.

According to the present invention, in the sixth field effect transistor, the air bridge forming a part of the resonance inductor line is connected to the source electrode finger.
The source electrode finger can also be used as a part of the resonance inductor line. Thereby, there is an effect that a larger inductance can be realized.

According to the present invention, the seventh field-effect transistor has at least two air bridges forming a resonance inductor line, and further includes the air bridge arranged so as to straddle the source electrode. One is arranged so as to straddle the drain electrode, and these are interconnected to form a spiral resonance inductor line, which is arranged so as to surround the electrode finger of the FET. In addition to the advantages of the first and second field-effect transistors, the longer length of the resonance inductor line allows the realization of a larger inductance.

According to the present invention, the eighth field-effect transistor has the spiral inductor line disposed so as to surround the electrode finger thereof.
The structure in which the drain electrode or the source electrode is connected to the outside through the electrode air bridge arranged so as to straddle the inductor line allows the air bridge to be wide and short, so that the manufacturing is easy. In addition, mechanical effects such as vibration and impact can be reduced. Therefore, such a configuration does not impair the advantage of downsizing as described in the fourth configuration, and
This has the effect of increasing reliability and mass productivity.

According to the present invention, the ninth field effect transistor has a channel structure formed between the inductor line and the drain electrode finger or the source electrode finger thereof and the gate electrode finger is provided.
When the field effect transistor is ON when the applied bias is 0 V, a part of the resonance inductor line arranged along the electrode finger can be made to have the same potential as each electrode finger. As a result, the reflection caused by the resonance inductor line is reduced. Thus, there is an effect that good reflection characteristics can be realized.

According to the tenth field effect transistor, in the tenth field effect transistor, the air bridge forming a part of the resonance inductor line is arranged so as to straddle the source electrode finger or the drain electrode finger. An island pattern is provided between the electrode fingers or the drain electrode fingers via the gate electrode fingers, and the island pattern and the air bridge are connected. In addition to the effect, the air bridge portion can be set to the same potential, so that there is an effect that more excellent reflection characteristics can be realized.

According to the eleventh field effect transistor, the eleventh field effect transistor has a channel structure formed between the inductor line and the drain electrode finger or the source electrode finger thereof, the gate electrode finger provided thereon, and the adjacent inductor line. Because a channel structure is formed between the strip conductors and the gate electrode fingers are provided,
The same potential can be applied not only between the electrode fingers and the resonance inductor lines, but also between adjacent resonance inductor lines.
Thereby, there is an effect that reflection caused by the resonance inductor line can be reduced and good reflection characteristics can be realized.

According to the present invention, the semiconductor switch is the first type.
By using a plurality of eleventh field-effect transistors, an SPNT (single-pole multi-throw switch) such as an SPDT switch is realized. That is, while drains or sources of a plurality of field effect transistors are commonly connected to one of three or more switch input / output lines, electrodes (drain or source) not commonly connected are connected to the remaining switch input / output lines. It is configured to be individually connected to the track. Here, an SPNT switch is realized by opening and closing each field effect transistor in a complementary manner. At this time, at least one of the above-described first to first fields
Since one transistor configuration is used, the advantages of these configurations are realized. As a result, a small SP with low reflection
There is an effect that the NT switch becomes possible.

According to the present invention, the configuration of the first semiconductor switch is used as an SPNT switch, and a plurality of transmission paths having different line lengths are selected and used by the SPNT switch, thereby providing different propagation delays. Since the phase shifter that generates the phase shifter is realized, the advantages of the above-described semiconductor switch can be enjoyed. In addition, the effect that the phase shifter having small multi-reflection and small deterioration of the phase shift amount characteristic even when connected in multiple stages can be realized. There is.

[Brief description of the drawings]

FIG. 1 is a plan view showing a field effect transistor structure according to a first embodiment of the present invention.

FIG. 2 is a plan view showing a field effect transistor structure according to a second embodiment of the present invention.

FIG. 3 is a plan view showing a field effect transistor structure according to a third embodiment of the present invention.

FIG. 4 is a plan view showing a field effect transistor structure according to a fourth embodiment of the present invention.

FIG. 5 is a plan view showing a field effect transistor structure according to a fifth embodiment of the present invention.

FIG. 6 is a plan view showing a field effect transistor structure according to a sixth embodiment of the present invention.

FIG. 7 is a plan view showing a field effect transistor structure according to a seventh embodiment of the present invention.

FIG. 8 is a plan view showing a field effect transistor structure according to an eighth embodiment of the present invention.

FIG. 9 is a plan view showing a field effect transistor structure according to a ninth embodiment of the present invention.

FIG. 10 is a plan view showing a field effect transistor structure according to a tenth embodiment of the present invention.

FIG. 11 is a plan view showing a field effect transistor structure according to an eleventh embodiment of the present invention.

FIG. 12 is a plan view showing a structure of a field-effect transistor according to a twelfth embodiment of the present invention.

FIG. 13 is a plan view showing a semiconductor switch according to a thirteenth embodiment of the present invention.

FIG. 14 is a plan view showing a semiconductor phase shifter according to Embodiment 14 of the present invention.

FIG. 15 is a circuit diagram showing a configuration of a semiconductor switch according to Conventional Example 1.

FIG. 16 is a plan view showing a configuration around a field-effect transistor according to Conventional Example 1.

FIG. 17 is an equivalent circuit diagram showing one operation state according to Conventional Example 1.

FIG. 18 is a simplified equivalent circuit diagram showing one operation state according to Conventional Example 1.

FIG. 19 is a circuit diagram showing a configuration of a semiconductor phase shifter according to Conventional Example 2.

[Explanation of symbols]

1 input terminal, 2, 21, 22 output terminal, 3, 4, 1
2 to 15, 20a to 20i Inductor line for resonance (inductor line), 5 drain electrode finger, 6 source electrode finger, 7, 71 to 74 gate electrode finger, 8 gate wiring, 9 air bridge, 10 input line, 11 output line , 16, 17, 28, 29 SPD
T switch (semiconductor switch), 18, 181 Reference transmission line, 19, 191 Delay transmission line, 23 Source electrode air bridge (electrode air bridge), 24 Drain electrode air bridge (electrode air bridge), 25 Source electrode finger extension conductor , 26 island conductor (island pattern), 201 first strip conductor (strip conductor), 202 first air bridge (air bridge), 2
03 Second strip conductor (strip conductor), 204
2nd air bridge (air bridge), 205 3rd strip conductor (strip conductor), 206 3rd air bridge (air bridge), 207 4th strip conductor (strip conductor), 208 4th air bridge (air bridge), 209 Fifth strip conductor (strip conductor), 211 first connection pad, 221 projecting pattern source electrode (projecting pattern), 271 second connection pad, 2010 sixth strip conductor (strip conductor), 2011 seventh strip conductor (strip) Conductors), Q1-Q12 Field effect transistors.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01P 1/15 1/185 (72) Inventor Yoshihiro Tsukahara 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation ( 72) Inventor Eiji Taniguchi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo, Japan Mitsubishi Electric Corporation (72) Inventor Morishige Hieda 2-3-2, Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Corporation (72) 72) Inventor Kenji Suematsu 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Inside Mitsubishi Electric Corporation

Claims (13)

[Claims] 1. A drain electrode finger having a finger shape connected to the drain electrode and having a drain electrode, a source electrode and a gate electrode, and a drain electrode finger connected to the source electrode and having a finger shape. A source electrode finger arranged in a finger-crossing manner with the finger; and a gate wiring having a gate electrode finger connected to the gate electrode and disposed between the drain electrode finger and the source electrode finger. In a field-effect transistor having a drain electrode and an inductor line provided electrically connected between the source electrode, a part of the inductor line is formed by an air bridge, which straddles the source electrode. One end of which is electrically connected to the inductor line provided so as to extend from the drain electrode. A field-effect transistor, wherein the other end is electrically connected to the source electrode. 2. The method according to claim 1, wherein a part of the inductor line provided so as to extend from the drain electrode is constituted by an air bridge, and is arranged so as to straddle the gate wiring. Field effect transistor. 3. The field effect transistor according to claim 1, wherein the source electrode portion has a pattern shape cut inside. 4. The field effect transistor according to claim 1, wherein a plurality of gate, source and drain electrode fingers are respectively combined. 5. An air bridge constituting an inductor line, which is disposed so as to straddle a source electrode, is connected to the source electrode via a projecting pattern provided on the source electrode. Item 2. The field effect transistor according to Item 1. 6. A part of an inductor line is constituted by an air bridge, which is arranged so as to straddle a source electrode, and one end of which is electrically connected to a line extending from a drain electrode. 2. The field effect transistor according to claim 1, wherein the other end is connected to a source electrode finger. 7. A drain electrode finger which has a drain electrode, a source electrode and a gate electrode and is connected to the drain electrode and has a finger shape, and a drain electrode which is connected to the source electrode and has a finger shape. A source electrode finger arranged in a finger-crossing manner with the finger; and a gate wiring having a gate electrode finger connected to the gate electrode and disposed between the drain electrode finger and the source electrode finger. In a field-effect transistor having a drain electrode and an inductor line electrically connected between the source electrode, a part of the inductor line is constituted by a plurality of air bridges, and at least one of the air bridges Are arranged so as to straddle the source electrode, and at least one other straddles the drain electrode. Disposed Te Unishi, these are spiral inductor line connected are formed together, the plurality of drain field effect transistor being disposed so as to surround the source and gate electrode fingers. 8. A drain electrode finger having a finger shape connected to the drain electrode and having a drain electrode, a source electrode and a gate electrode, and a drain electrode finger connected to the source electrode and having a finger shape. A source electrode finger arranged in a finger crossing manner with the finger; and a gate wiring having a gate electrode finger connected to the gate electrode and disposed between the drain electrode finger and the source electrode finger. A field-effect transistor having a drain electrode and an inductor line electrically connected between the source electrode, wherein the field-effect transistor has a spiral inductor line arranged to surround the plurality of electrode fingers. And the drain through the electrode air bridge arranged so as to straddle this inductor line. Field effect transistor, characterized in that the poles or the source electrode is connected to an external. 9. The semiconductor device according to claim 1, wherein a channel structure is formed between the inductor line and a drain electrode finger or a source electrode finger of the field effect transistor, and a gate electrode finger is provided. The field-effect transistor according to claim 1. 10. An air bridge forming part of an inductor line is disposed so as to straddle a source electrode finger or a drain electrode finger, and a gate electrode finger is provided between the source electrode finger or the drain electrode finger. The field effect transistor according to any one of claims 1 to 9, wherein an island-shaped pattern is provided through the first and second air bridges, and the island-shaped pattern is connected to the air bridge. 11. A channel structure is formed between a plurality of strip conductors, which are connected via an air bridge, and a drain electrode finger or a source electrode finger of a field effect transistor, and a gate electrode finger is provided. 9. The field effect transistor according to claim 8, wherein a channel structure is formed between adjacent strip conductors wound spirally and a gate electrode finger is provided. 12. A semiconductor device comprising: at least three switch input / output lines for inputting / outputting a signal; and a plurality of field effect transistors which are opened / closed complementarily to each other, and a drain electrode and a source of the plurality of field effect transistors. One of the electrodes is commonly connected to one of the switch input / output lines, the other is individually connected to the other switch input / output lines, and at least one of the plurality of field effect transistors is connected to the switch. Item 12. A semiconductor switch having the configuration according to any one of Items 11 to 11. 13. An input line for inputting a signal, a plurality of transmission lines having different line lengths from each other, an output line for outputting a signal, and the input line is switched and connected to any one of the transmission lines. A first semiconductor switch, which is opened and closed in synchronization with the first semiconductor switch so that a signal input from an input line passes through any transmission line and appears on an output line, and the output line is connected to any transmission line. A second semiconductor switch for switching connection, wherein a switch input / output line related to a common connection among the switch input / output lines of the first and second semiconductor switches is connected to an input line or an output line; 13. The other switch input / output line of the semiconductor switch is connected to one of the transmission lines, and at least one of the first and second semiconductor switches is connected to the transmission line. A semiconductor phase shifter having the configuration described above.