JPH11312745A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make it possible to form not only a bipolar element but also an MOS element only by a bipolar process, by providing a capacitor hole in a field insulating film, and forming the gate film for the MOS element. SOLUTION: A bipolar element 40 is formed by utilizing a p-type silicon semiconductor substrate 1, an n<+> -type embedded layer 2, an n<-> -type epitaxial growing layer 3 and an n<-> -type isolation region 4 as the structure of e.g. a PMOS element 30P. However, the points different from the MOS element are the point where a p-type base region 20 is formed at the n<-> -type growing layer 3, and the point wherein an n<+> -type collector region 22 is formed on the surface of the growing layer 3 and an npn-type bipolar element 40 is formed. The surface of this bipolar element is uniformly convered with a field insulating film 8. Finally, metal layers 23, 24 and 25 are connected to regions 20, 21 and 22 through the windows formed in the field insulating layer 8.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device in which a bipolar element and a MOS element are formed on a common semiconductor substrate only by a bipolar process.

[0002]

2. Description of the Related Art One of the embedded LSI technologies having both an analog function and a digital function is a BiCMOS process. In this BiCMOS process, a bipolar element and a MOS element can be formed simultaneously on the same semiconductor substrate by adding a part of a MOS process to a normal bipolar process. In such an embedded LSI,
Bipolar elements are used for analog processing and high power drive, and MOS elements are used for switches and the like.

[0003] When a bipolar element and a MOS element are formed on the same substrate, what matters is the process parameters of both elements. Particularly important is the control of the threshold voltage VTH of the MOS element and the current amplification factor hfe of the bipolar element.

[0004]

In the conventional BiCMOS process, in order to control the VTH of a MOS device, a dedicated gate film forming step thinner than a field insulating film and a VTH control step by ion implantation are prepared.
Since these are steps that are not necessary for forming a bipolar element, the steps of the conventional BiCMOS process are more complicated than those of a simple bipolar process. This is a problem to be solved by the present invention.

It is an object of the present invention to provide a method of manufacturing a semiconductor device in which not only a bipolar element but also a MOS element can be formed only by a bipolar process.

[0006]

SUMMARY OF THE INVENTION An object of the present invention is to form a bipolar element and a MOS element in a common semiconductor substrate by a bipolar process, and to form a thick field insulating film on the surface of the semiconductor substrate. And forming a thin gate film for the MOS element by making a hole in the field insulating film to form a capacitor hole.

According to a preferred embodiment of the present invention, the thickness of the gate film is controlled according to a desired threshold voltage of the MOS device. In this case, the field insulating film may be a silicon oxide film or a silicon nitride film.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to embodiments shown in the drawings. FIG. 1 is a sectional view showing a PMOS element 30P in one embodiment of a semiconductor device formed by a manufacturing method according to the present invention. The semiconductor substrate 1 used is a p-type silicon material. An n ⁺ type buried layer is formed in the element region of the substrate 1. Further, an n ⁻ -type epitaxial growth layer 3 is continuously formed thick on the surface of the substrate 1. The element region of the growth layer 3 is separated by a p ⁺ -type isolation region 4. In this element region, a p-type source region 5 and a drain region 6 of a PMOS are formed in a base forming step of a bipolar process. Further, the growth layer 3 is set to a positive potential + BG
N ⁺ -type contact region 7 for holding is formed by a bipolar process.

On the entire surface of the growth layer 3, a thick field insulating film 8 is formed. This insulating film 8 is made of a silicon oxide film (SiO ₂ ) or a silicon nitride film (Si ₃ N ₄ ).
It is. The source region 5, the drain region 6, and the contact region 7 are formed by opening windows in the field insulating film 8, respectively.
It is connected to wiring metal layers 9, 10, 11 such as (aluminum). On the other hand, the Al gate electrode 12 is formed on the thin gate film 13. This gate film 13
This is not a portion formed in the MOS process but a portion in which the thick field insulating film 8 is thinned in the capacitor hole forming process. Generally, a threshold voltage VTH of a MOS element is expressed by the following equation.

[0010]

(Equation 1)

However, ΔB = (kT / q) · ln (ND
/ NI), T is the absolute temperature, k is the Boltzmann constant, q is the charge, ND is the donor density, nI is the free electron density of intrinsic silicon, εo is the permittivity of free space, εs is the relative permittivity of silicon, and Co is This is the insulation film capacity.

In a normal bipolar process, the growth layer 3
Is low, the donor density ND is small. Therefore, the threshold voltage VTH between the source region 5 and the drain region 6 is only about 10 volts. MO as it is
Since it is difficult to use as an S element, the insulating film capacitance Co is increased to further lower VTH. For this purpose, a thin gate film 13 is formed by making a hole in the field insulating film 8 as described above. In this way, the PM process can be performed without adding a special MOS process to the bipolar process.
The OS element 30P can be formed.

FIG. 2 shows an NMOS device 30N in another embodiment of a semiconductor device formed by the manufacturing method according to the present invention.
FIG. The p-type silicon semiconductor substrate 1, the n ⁺ -type buried layer 2, the n ^-- type epitaxial growth layer 3, the p ⁺ -type isolation region 4, and the metal layers 9 to 12 are the same as those in FIG. In order to form an NMOS element in the n ⁻ -type growth layer 3, a low concentration p-diffusion is required in a channel portion for VTH control. The p ^- type region (well) 14 is for this purpose and is preferably diffused by high-resistance ion implantation. The surface of this p ^- type region 13 has n ⁺
Form source region 15 and n ⁺ -type drain region 16 are formed. Further, a thick field insulating film 8 is formed uniformly, and a window is opened in this to connect the metal layers 9, 10, 11 to each other. Al
The thin gate film 13 below the gate electrode 12 is a portion in which the thick field insulating film 8 is thinned in a capacity punching step. In this way, NMO can be performed only by the bipolar process.
The S element 30N is completed.

FIG. 3 shows a MOS device such as the PMO of FIG.
FIG. 11 is a cross-sectional view showing a part of an LSI of the present invention in which an S element 30P and a bipolar element 40 are mounted together only by a bipolar process. The structure of the PMOS element 30P is as described with reference to FIG. The bipolar element 40 is also formed using the same p-type silicon semiconductor substrate 1, n ⁺ -type buried layer 2, n ^-- type epitaxial growth layer 3, and p ⁺ -type isolation region 4. The difference from the MOS device is that the n ^- type growth layer 3
A p-type base region 20 and an n ⁺ -type emitter region 21 on the surface thereof, and an n ⁺ -type collector region 22 on the surface of the growth layer 3 to form an npn-type bipolar element 40. It is a point to form. The surface of the bipolar element 40 is uniformly covered with the thick field insulating film 8. Finally, the metal layers 23, 24, and 25 are connected to the regions 20, 21, and 22 via the windows formed in the field insulating film 8, and the bipolar element 40 is completed.

[0015]

As described above, according to the method of manufacturing a semiconductor device according to the present invention, a bipolar element and a MOS element can be formed only by a bipolar process.
General BiCMOS because only dedicated process is not used
The manufacturing process is simplified compared to the process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a PMOS element in one embodiment of a semiconductor device formed by a manufacturing method according to the present invention.

FIG. 2 is a cross-sectional view showing an NMOS element in another embodiment of a semiconductor device formed by a manufacturing method according to the present invention.

FIG. 3 is a cross-sectional view showing a part of an LSI of the present invention in which a MOS element and a bipolar element are mixed only by a bipolar process.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate 2 Buried layer 3 Epitaxial growth layer 4 Isolation region 5 Source region 6 Drain region 7 Contact region 8 Thick field insulating film 9 Source electrode metal layer 10 Drain electrode metal layer 11 Power supply electrode metal layer 12 Gate electrode metal layer 13 Thin Gate film 14 Well 15 Source region 16 Drain region 20 Base region 21 Emitter region 22 Collector region 23 Base electrode metal layer 24 Emitter electrode metal layer 25 Collector electrode metal layer 30P PMOS element 30N NMOS element 40 Bipolar element

Claims (3)

[Claims] A step of forming a bipolar element and a MOS element in a common semiconductor substrate by a bipolar process; a step of forming a thick field insulating film on a surface of the semiconductor substrate; and forming a capacity hole in the field insulating film. Applying the MOS
Forming a thin gate film for an element. 2. The method according to claim 1, wherein the thickness of the gate film is controlled in accordance with a desired threshold voltage of the MOS device. 3. The method according to claim 1, wherein the field insulating film is a silicon oxide film or a silicon nitride film.