JPH11312744A - Nonvolatile memory of metal gate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form the nonvolatile memory cell of an array-shaped metal gate together with a transistor around an MOS, by forming a control gate comprising metal in the pattern insulated from a floating gate so as to cover the floating gate. SOLUTION: Floating gates are arranged in the line pattern. The floating gates 24 are mutually separated with field oxide regions 31 in the longitudinal direction and mutually separated by the lines of continuous embedded bit lines 25 in the lateral direction. A source/drain region for each memory is formed at the line part of the embedded bit line 25 neighboring each floating gate 24. Furthermore, the part of the metal line 23 covering the floating gate 24 forms the control gate of each memory. This metal line 23 is also called as a word line. These word lines are constituted of metal. Word-line strapping as in the case of the nonvolatile array of a polysilicon word line is not used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to nonvolatile semiconductor memory technology, and more particularly, to a structure of a nonvolatile memory cell having a metal layer as a control gate and a method of manufacturing the same.

[0002]

Conventional non-volatile semiconductor memory cell technology, that is, a memory cell technology using a polysilicon floating gate as a memory component, usually uses two or more polysilicon layers. FIG. 1 shows a cross-sectional view of a conventional double polysilicon layer ETOX nonvolatile memory cell. The first polysilicon layer 10 is generally called a floating gate and is used as a memory component. As shown in FIG. 1, the floating gate 10 has its upper surface wrapped in an ONO (oxide-nitride-oxide) bonded dielectric layer 11 and its lower surface is typically about 100 angstroms thick tunnel oxide dielectric. Wrapped in layer 12.

The second polysilicon layer 13 is used as a control gate of this memory cell. When many memory cells are arranged side by side in the direction of one row of the memory array, the second polysilicon layer 13 is a continuous line, and this line is generally called a word line. As shown in FIG. 1, n + region 14 and n + drain region 15
Is formed on a P-type substrate by arsenic ion implantation.

A metal layer 16 contacts source region 14 and drain region 15 and is separated from control gate 13 by a typically thick BPSG insulating layer 17. Importantly, source region 14 and drain region 15 are self-aligned to the ends of the double polysilicon stack. This feature allows ETOX cell scaling with minimal complexity. This self-aligned feature is achieved by forming a stack of control gates 13 and floating gates 10 followed by ion implantation for source / drain formation.

With the advancement of submicron technology and the rapid increase in memory capacity, and with the advancement of system-on-a-chip, various limitations have arisen and effective solutions have not yet been found.

One of those limitations is the RC delay of long word lines associated with large memory arrays. As described above, in the nonvolatile memory array, the second-layer polysilicon forms a word line. Since the resistance value and capacitance value related to the second-layer polysilicon are large, so-called word line RC is used.
A delay occurs. As the capacity of memory devices has increased rapidly, the size of memory arrays has grown significantly. In addition to this, continued advances in semiconductor memory technology have resulted in the production of long, narrow polysilicon word lines, ie, memory arrays with long RC delays. This RC delay, the delay that occurs in the critical high-speed path of the majority of memory devices, is the limiting factor in keeping the access time of a memory device to an acceptable value.

Various techniques have been employed to minimize the word line RC delay. In one approach, the word line is split into two, one half driven by a row decoder and the other half driven by a repeater. Each word line requires one repeater, and each repeater is composed of two serially connected inverters. Since these two inverters connected in series must be accommodated between word lines,
Even if the layout is performed with high efficiency, an extra device surface area is required for the required area of the repeater. Therefore,
While repeaters are effective in reducing word line RC delays, they consume additional device surface area.

In the second method, tungsten silicide is used. That is, tungsten silicide makes the resistance of the word line RC one-tenth that of polysilicon. However, with the rapid increase in memory capacity over the past decade, silicides are no longer an effective means of reducing RC delay.

A third approach, which is more effective in minimizing word line RC delay, is to strap the polysilicon word lines with a metal layer. Since the resistance of the metal is so low, strapping the polysilicon effectively shorts the polysilicon word line, thereby greatly reducing the resistance of the word line RC. However, in order to strap the polysilicon word line with a metal, it is necessary to provide a contact hole between the metal and the polysilicon. Since the word line spacing is usually the narrowest, the contact holes will increase the word line spacing, resulting in a large waste of device surface area. Also, metal straps extending across the thin polysilicon word lines are formed over the bumpy topography resulting from the double polysilicon stack. The remarkable decrease in the non-defective product rate in the mass production of the nonvolatile memory is caused by this. Therefore, the improvement of the operation speed also comes at the cost of increasing the silicon surface area and decreasing the yield rate in this method.

[0010] All of the above approaches have considerable disadvantages in achieving a reduction in word line RC delay.

[0011] Another disadvantageous limitation is the complexity resulting from the combination of different technologies. A general trend in the semiconductor industry is to incorporate more functions into one chip and replace many individual devices with one device. For such integration, it has become necessary to integrate different technologies such as SRAM, nonvolatile memory, and standard CMOS logic into one process. However, combining these disparate technologies into a single process has proven difficult and complex.

One example of the complexity that arises when combining heterogeneous technologies is the combination of SRAM using four-transistor memory cells and non-volatile memory into one process, a combination commonly used in microcontroller design. It is. Four-transistor SRAM cells require the use of high resistivity polysilicon as a load element. In contrast, non-volatile memory technology requires the use of low resistivity polysilicon to minimize operating speed impediments such as polysilicon interconnect delay, gate resistance, and word line resistance. That is, two incompatible requirements are required for the polysilicon layer. Some memory manufacturers have adopted a single polysilicon layer non-volatile cell approach to overcome this limitation. However, the size of a single polysilicon layer cell is typically three to four times larger than a conventional double polysilicon layer cell. Therefore, in situations where no effective solution is proposed, flash / SRA
The development of cost-effective products such as MIC devices is lagging.

[0013] In theory, the above two limitations are overcome by using metal instead of polysilicon as the control gate of the memory cell. That is, since the word line can be formed directly from metal and a contact hole for strapping the word line is unnecessary, the problem of RC delay can be solved without sacrificing the chip surface area. SRAM
Regarding the limitations caused by the integration of the technology and the non-volatile memory technology, the second layer polysilicon of high resistivity is dedicated to the load element of the four-transistor SRAM cell and the metal layer
The control gate and floating gate of the cell are each comprised of the first layer polysilicon to address the above conflicting property requirements for the second layer polysilicon.

Metal gate MOS transistors were common during the early days of IC fabrication technology, ie, when 5 micron wide lithographic metal gate technology was used. However, the use of metal as a gate electrode or control electrode of a MOS device has been abolished for many years. The main reason this approach was abandoned was its lack of scalability. Unlike conventional polysilicon gate technology, which is highly scalable, metal gate configurations are difficult to scale.

As mentioned above, the scalability of polysilicon gate technology depends on the self-alignment feature of its manufacturing process. That is, since the source / drain ion implantation step is performed after the deposition and patterning of the polysilicon gate, the end of the polysilicon control gate is formed at the source / drain for defining the transistor channel region.
The source /
The drain region is self-aligned to the polysilicon control gate. Therefore, to achieve this self-alignment, the control gate must be formed before the source / drain regions. However, metal gate MO
In S technology, the source / drain implant step cannot be performed after the deposition and patterning of the metal control gate, and thus cannot achieve self-alignment with the source / drain regions. In MOS technology, an annealing step at a temperature of 900 ° C. or more needs to be performed after the source / drain ion implantation step to activate arsenic and form a defect-free source / drain region. 900 ° C due to the high temperature of this annealing process
If it is not a heat-resistant material such as tungsten polycide that can withstand the above high temperature, it cannot be used as a control gate. Therefore, aluminum, which is widely used as a gate metal, is a low-melting-point material and can be deposited only after the above-described annealing step, so that self-alignment of the source / drain regions becomes impossible. The reason why the metal gate MOS technology is no longer used is as described above.

Accordingly, an object of the present invention is to provide a memory cell structure in which an array-like metal gate (MG) nonvolatile memory cell is formed together with a MOS peripheral transistor, and a method of manufacturing the same.

[0017]

According to the present invention, it is possible to provide a metal gate (MG) nonvolatile memory cell suitable for forming an array, and a method of forming the cell together with a MOS peripheral transistor.

The MG nonvolatile memory cell comprises a source region and a drain region formed in a silicon substrate and separated from each other by a channel region, and a floating region formed over the channel region and insulated from the channel region. A gate having at least one end aligned with a corresponding end of one of the source and drain regions and used to define the end; and a floating gate over the floating gate. A control gate made of metal formed insulated from the gate.

A method for manufacturing an MG nonvolatile memory cell according to the present invention comprises the steps of: forming a first insulator layer on a silicon substrate; forming a floating gate on the insulator layer; Forming a source region and a drain region in the substrate by self-aligning at least one of the source region and the drain region with a corresponding end of the floating gate; Forming a control gate including a metal on the second insulator layer; and forming a control gate including a metal on the second insulator layer.

One feature of the present invention is that the word line RC is significantly reduced without burdening the chip surface area because the word line is made of metal.

Another feature of the present invention is that the source / drain region of the memory cell can be self-aligned with the end of the floating gate.

The present invention achieves the above features using a simple process that facilitates integration of CMOS transistors and MG nonvolatile memory cells.

The above and other features and advantages of the present invention will become more apparent from the following description and accompanying drawings.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One cell configuration of a metal gate nonvolatile memory cell according to the present invention and a method of manufacturing the same will be described in detail below. This description is for the purpose of illustration and not limitation.

(A) Description of Cell Configuration of Metal Gate Non-Volatile Memory Cell in Contactless Array: FIGS. 2A and 2B illustrate a specific embodiment of the present invention. FIG. 2A shows a contactless array according to the present invention. FIG. 2B is FIG.
2A shows a cross section taken along line AA.

As shown in FIG. 2A, the floating gates 24 are arranged in rows. The floating gates 24 are vertically separated from each other by field oxide regions 31 and are horizontally separated from each other by columns of continuous buried bit lines 25. A source / drain region for each memory cell is formed in a column portion of the buried bit line 25 adjacent to each floating gate 24 (this is also shown in FIG. 2B).

In FIG. 2A, a continuous metal line 23 is shown laterally across the array to cover the floating gate 24. The portion of the metal line 23 covering the floating gate 24 forms the control gate of each memory cell. This metal line 23 is also called a word line. Note that these word lines are made of metal and do not use word line strapping as in the case of a conventional nonvolatile memory array using polysilicon word lines.

FIG. 2B also shows a lightly doped diffusion (LDD) oxide spacer 34 at the end of the control gate 24. These spacers smooth the topography of the array and improve the step coverage of the metal word lines.

The metal control gate 23 and the floating gate 24 are separated by a coupling dielectric 21. In one embodiment, the coupling dielectric 21 comprises an oxide-nitride-oxide-polysilicon (ONOP) composite layer. The ONOP composite layer has a thickness of 8 from the lower layer to the upper layer.
It includes an oxide layer in the range of 0 Å to 250 Å (a preferred thickness of 100 Å), a nitride layer (N) having a thickness of 100 Å, an oxide layer having a thickness of 50 Å, and a polysilicon layer (P).

In an alternative embodiment, coupling dielectric 21 comprises a composite oxide-polysilicon (OP) layer. This oxide ranges in thickness from 80 Angstroms to 250 Angstroms (the preferred thickness is 100 Angstroms).
To form the lowermost layer.

The oxide layers in both the ONOP composite layer and the OP composite layer are formed by high temperature oxide (HTO) or thermal oxidation growth. The polysilicon layer in these composite layers also acts as a buffer layer that protects the underlying layers from subsequent steps. The optimum value for the thickness of the polysilicon layer depends on whether polysilicon doped with impurities or undoped polysilicon is desired. If undoped is desired, a preferred thickness is 100 Å to 600 Å. If doping is desired, the value is 400 angstroms.

For doping the polysilicon layer, an impurity such as arsenic or phosphorus is used. The doped polysilicon is advantageously used at the periphery for interconnection, load resistance of a four-transistor SRAM cell, and the like. Four transistor SRA
When used in the M cell, an optimum value of the thickness is selected so that the polysilicon buffer layer has a desired load resistance characteristic.

FIG. 2B shows a tunnel oxide dielectric layer 22 that isolates the floating gate from the lower silicon substrate.
Are also shown.

One important difference from the conventional ETOX cell approach is that the annealing step in the formation of the metal gate memory cell, that is, the step of removing defects from the source / drain regions, is performed after the formation of the control gate as described below. This is done before formation. By altering the process sequence in this way, concerns associated with the low melting point of aluminum in the high temperature annealing process are eliminated.

Another important difference from the conventional ETOX cell approach is that the source / drain region is floating gate in contrast to the ETOX cell approach where the source / drain region is self-aligned to the control gate and floating gate stack. Is self-aligned to the end of the

The two differences described above allow metal to be used directly as the control gate of a memory cell, while maintaining the benefits of scalability based on a self-aligned source / drain formation process.

(B) Description of the steps of the manufacturing process of the metal gate nonvolatile memory cell: FIGS. 3A to 3M show one embodiment of the present invention. These figures show cross sections of memory devices and MOS peripheral transistors at various stages of the manufacturing process. The cross section of a MOS transistor is
Included in the figure to show that the metal gate memory process of the present invention can be easily incorporated into a standard MOS process. The dimensions in these drawings are not to scale, but are for illustration only.

Prior to the step of FIG. 3A, an island-shaped field oxide layer having a thickness of about 5000 angstroms, as indicated by region 31 in FIG. 2A, is grown on a silicon substrate. The field oxide 31 of FIG. 2A is not shown in FIGS. 3A to 3M. That is, these figures show cross sections taken along line AA in FIG. 2A at various stages of the manufacturing process.

FIG. 3A shows a P-type substrate 10 on which a thin tunnel oxide layer 11 having a thickness in the range of 65 Å to 100 Å has been grown. Subsequently, over the tunnel oxide layer 11, a thickness of 150
Deposit a first polysilicon layer or polycide layer 12 ranging from 0 Angstroms to 3000 Angstroms. Next, the polysilicon layer 12 is doped with phosphorus to be n-type.

The cross-sections shown in the figures below FIG. 3B show peripheral transistors in the peripheral region 40 along the side memory cells of the array region 50. In FIG. 3B, the floating gate 1
3 is partitioned by a photoresist masking step followed by a plasma etching step. The polysilicon portion 16 in FIG. 3B remains unpartitioned. As shown in FIG. 3B, the photoresist 30 used to partition the polysilicon is not removed from above the floating gate 13 and the polysilicon 16.

Next, as shown in FIG.
Arsenic ion implantation is performed to form the source / drain regions 15 of the memory cells in 0. In this step, the source region and the drain region are self-aligned with the end of the floating gate.

Since the floating gate 13 is covered with the photoresist 30 during the arsenic implantation process, the floating gate 13 is protected from potential damage during the source / drain implantation. As a result, it is possible to avoid deterioration of the memory cell holding characteristics, that is, the deterioration of the non-defective product rate or the deterioration of the characteristics that otherwise causes the loss of the pellets having sufficient functions.

Next, as shown in FIG. 3D, the photoresist 30 is removed, and a high-temperature annealing process at about 900 ° C. is performed to remove defects in the source / drain regions 15. The annealing of the source / drain region 15 is performed before the deposition and formation of the memory cell control gate.

As shown in FIG. 3E, the entire array region 50 is covered with the photoresist 27 and protected while protecting the peripheral region 40.
A photoresist masking step for partitioning the gate electrode 26 of the peripheral transistor in FIG.

Next, a photoresist 27 is applied to the gate electrode 2.
6 and the entire memory cell. A photoresist masking step is performed again to cover the memory cells with photoresist 28, and a peripheral area 40 is ion implanted to form lightly doped (LDD) regions 17 as shown in FIG. 3F.

As shown in FIG. 3G, the photoresist 28
Is removed from above the memory cell and an oxide spacer, preferably made of HTO, is deposited and then etched back to remove the edge of the peripheral transistor 26 and the floating gate 13.
An LDD oxide spacer 19 is formed at the end of. Although oxide spacers 19 are commonly used to form peripheral LDD transistors, it is advantageous in the present invention to use the oxide spacers in array region 50 to smooth the topography of the array. If the allography is smooth, the step coverage of the metal word line deposited in the subsequent process will be good.

Next, as shown in FIG. 3H, arsenic ion implantation is performed on the peripheral region 40 to form the source / drain region 20 of the peripheral transistor. During this ion implantation step, the array region 50 is covered with an array mask 29 to protect the floating gate 13 from ion implantation.

As shown in FIG. 3I, a coupling dielectric 21 is grown over the memory cells and peripheral transistors.
In one embodiment, the coupling dielectric 21 comprises an oxide-nitride-oxide-polysilicon (ONOP) composite layer. The ONOP composite layer has a thickness ranging from 80 Angstroms to 250 Angstroms (preferably 100 Angstroms) in order from bottom to top.
, A 100 Å thick nitride (N) layer, a 50 Å thick oxide layer, and a polysilicon (P) layer.

In an alternative embodiment, coupling dielectric 21 includes an oxide-polysilicon (OP) composite layer. The oxide layer has a thickness between 80 Å and 250 Å (a preferred thickness of 100 Å),
The lowermost layer of the OP composite layer is formed.

The oxide layers in both the ONOP composite layer and the OP composite layer are formed of high temperature oxide (HTO) or thermally oxidized growth layers. In addition, these ONOP composite layers and O
The polysilicon layer in the P composite layer acts as a buffer protecting the lower layer from subsequent processing. The optimum value for the thickness of the polysilicon layer depends on the decision whether to use doped or undoped polysilicon. Without undoping, the preferred thickness range is 100 Å to 600 Å. If doped, the preferred thickness is between 400 Å and 100 Å.

For doping the polysilicon layer, an impurity such as arsenic or phosphorus is used. The polysilicon layer so doped is a peripheral interconnect, a four transistor SR
It is advantageous to use it for the load resistance of an AM cell. In the case of a four-transistor SRAM cell, an optimum thickness is selected so that the buffer polysilicon exhibits desired load resistance characteristics.

In FIG. 3J, coupling dielectric composite layer 21 is removed from the peripheral transistors by a conventional photoresist masking and etching process. In FIG. 3K, BPSG
An insulating layer 22 is deposited and then subjected to a BPSG flow step to form a BPSG having a thickness of about 6000 Å over both the array region 50 and the peripheral region 40.

In FIG. 3L, the contact holes 23 are formed by using a contact mask. When forming the contact hole 23 in the peripheral region 40, the BPSG layer 22 is dug down to the silicon surface by etching. This facilitates subsequent steps for forming a contact with the source / drain region 20. In the array region 50, the entire memory array is opened as a large contact hole 23, and the BPSG layer 22 is etched down to the coupling dielectric layer 21 as shown in FIG. 3L. Due to the oxide-polysilicon selectivity of the dry plasma oxide etch, the lower layer is
O to protect against etching for G contact
It is necessary to select an appropriate thickness for the buffer polysilicon layer of the NOP composite layer or the OP composite layer. For example, if the oxide-polysilicon selectivity exceeds 30, sufficient protection can be achieved by increasing the buffer polysilicon thickness to 400 Å or more.

After forming the contact holes, a layer 24 of metal 1 is deposited over the memory cells and peripheral transistors. The deposited metal 1 layer 24 is partitioned using a photoresist masking step in the array region 50 as a control gate of the memory cell and in the peripheral region 40 as an interconnect line for a peripheral transistor. As described above, the oxide spacer 1 near the floating gate 13
9 provides for smooth step coverage of the metal word lines 24 as shown in FIG. 3M.

Next, a portion of the buffer polysilicon layer (not shown in FIG. 3M) remaining exposed between adjacent metal word lines is subjected to polysilicon plasma using the metal word line pattern as a mask. It is removed in an etching step. This step is necessary to prevent leakage between metal word lines through the buffer polysilicon. Also, by using the metal word line pattern as a mask in the etching of the buffer polysilicon, the self-alignment of the remaining buffer polysilicon to the metal word lines is ensured.

Next, a conventional process (not shown) can be performed to form a subsequent metal layer as required. Finally, a conventional passivation layer (not shown) is deposited over the silicon surface to protect the pellet from damage such as scratches.

FIGS. 4A to 4F show another embodiment of the present invention. The upper half of each of these figures shows a well-known non-volatile memory cell structure along with its corresponding program / erase / read logic table. The lower half of each of these figures shows a metal gate configuration corresponding to the known structure of the non-volatile memory cell of the present invention.

FIG. 4A shows an ETOX nonvolatile memory cell and its program / erase / read-out table (same mail).
U.S. Pat. No. 5,077, to Shafik Hadat et al.
No. 691) is shown with a corresponding metal gate configuration for a substantially grounded array structure without contacts. FIG. 4B shows a split gate memory cell and its program / erase / read table with its corresponding metal gate configuration. FIG. 4C shows a double polysilicon source side implanted memory cell and its program / erase / read table with corresponding metal gate configuration. FIG. 4D shows a triple polysilicon source side implanted memory cell and its program / erase / read table (U.S. Pat.
No. 4,465 and U.S. Pat.
No. 090) is shown with a corresponding metal gate configuration for a contactless substantially grounded array structure. FIG. 4E shows a triple well divided bit line NOR (DINOR) memory cell and its program / erase / read table (IEDM).
Tsuji et al., "DINOR Improving Erasure / Write Cycle Durability," published on pages 3.4.1 to 3.4.4 in 1994.
New Erasure Method for Flash Memory ”is shown with a metal gate configuration for a contactless, substantially grounded array structure. FIG. 4F shows a self-aligned dual bit line split gate flash memory cell (US Pat. No. 5,278,439, issued Jan. 11, 1994), which is hereby incorporated by reference. Shown with corresponding metal gate configurations and program / erase / read tables.

As is apparent from FIGS. 4A to 4F, the concept of the metal gate memory cell is simple, so this concept can be applied to any nonvolatile memory cell such as EPROM, flash EPROM, flash EEPROM, NOVRAM, and the like.

The above description is intended to be illustrative, not limiting. Also, the present invention is intended to embrace all such variations and modifications that fall within the scope of the appended claims.

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[Procedure amendment]

[Submission date] July 10, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Brief description of drawings

[Correction method] Added

[Correction contents]

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a conventional double polysilicon layer ETOX nonvolatile memory cell.

FIG. 2A is a plan view of an array without contacts according to the present invention.

FIG. 2B is a sectional view taken along line AA in FIG. 2A.

FIG. 3A is a memory device and MO for describing a manufacturing process of a metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3B is a memory device and MO for explaining a manufacturing process of the metal gate nonvolatile memory cell of the present invention;
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3C is a memory device and MO for describing a manufacturing process of the metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3D is a memory device and MO for describing a manufacturing process of the metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3E is a memory device and MO for explaining a manufacturing process of the metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3F is a memory device and MO for describing a manufacturing process of the metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3G is a memory device and MO for explaining a manufacturing process of the metal gate nonvolatile memory cell of the present invention;
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3H is a memory device and MO for describing a manufacturing process of the metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3I is a memory device and MO for describing a manufacturing process of a metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3J is a memory device and MO for explaining the manufacturing process of the metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3K is a memory device and MO for describing a manufacturing process of a metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3L is a memory device and MO for describing a manufacturing process of a metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 3M is a memory device and MO for describing a manufacturing process of a metal gate nonvolatile memory cell of the present invention.
FIG. 4 is a sectional view of an S peripheral transistor.

FIG. 4A is a cross-sectional view of a known nonvolatile memory cell structure, and a corresponding program / erase / read logic table;
And a sectional view of a second embodiment of the invention corresponding to the above known structure.

FIG. 4B is a cross-sectional view of a known nonvolatile memory cell structure, and a corresponding program / erase / read logic table;
And a sectional view of a third embodiment of the invention corresponding to the above known structure.

FIG. 4C is a cross-sectional view of a known non-volatile memory cell structure, with corresponding program / erase / read logic tables;
And a sectional view of a fourth embodiment of the invention corresponding to the above known structure.

FIG. 4D is a cross-sectional view of a known nonvolatile memory cell structure, and a corresponding program / erase / read logic table;
And a sectional view of a fifth embodiment of the present invention corresponding to the above known structure.

FIG. 4E is a cross-sectional view of a known non-volatile memory cell structure, with a corresponding program / erase / read logic table;
And a sectional view of a sixth embodiment of the present invention corresponding to the above known structure.

FIG. 4F is a cross-sectional view of a known nonvolatile memory cell structure, and a corresponding program / erase / read logic table;
And a sectional view of a seventh embodiment of the invention corresponding to the above known structure.

DESCRIPTION OF SYMBOLS 10 Polysilicon layer (floating gate) 11 Oxide-nitride-oxide (ONO) bonding dielectric layer 12, 22 Tunnel oxide dielectric layer 13 Polysilicon layer (control gate) 14 Source region 15 Drain region 16 Metal layer 17 BPSG insulating layer 21 Oxide-nitride-oxide-polysilicon (ON
OP) Composite layer 23 Continuous metal line (word line) 24 Floating gate 25 Continuous buried bit line (source / drain region) 30 Photoresist 40 Peripheral region 50 Array region

Claims (50)

[Claims] A source region and a drain region formed in a silicon substrate and separated from each other by a channel region; and a floating gate covering the channel region in an insulated state from the channel region. At least one of which is aligned with one corresponding end of the source region and the drain region and serves to define the corresponding end; and covers the floating gate insulated from the floating gate. A nonvolatile memory cell including a metal control gate. 2. The non-volatile memory cell according to claim 1, wherein said control gate is subjected to an annealing step to remove defects from said source region and said drain region. 3. The nonvolatile memory cell according to claim 1, wherein said floating gate is insulated from said channel region by a tunnel oxide dielectric layer. 4. The semiconductor device according to claim 1, wherein the control gate is formed of a composite oxide-nitride-oxide-polysilicon (ONOP) dielectric or an oxide-polysilicon (OP) composite dielectric in order from a lower layer to an upper layer. 2. The non-volatile memory cell according to claim 1, wherein the non-volatile memory cell is insulated from the floating gate. 5. The nonvolatile memory cell according to claim 4, wherein said oxide in said ONOP coupling dielectric and said OP coupling dielectric is a high temperature oxide (HTO) or a thermally oxidized oxide. 6. The non-volatile memory cell of claim 4, wherein said ONOP coupling dielectric and said polysilicon in said OP coupling dielectric are undoped and have a thickness in the range of 100 Å to 600 Å. 7. The non-volatile memory cell of claim 4, wherein said ONOP coupling dielectric and said polysilicon in said OP coupling dielectric are doped with impurities and have a thickness in the range of 400 Å to 1000 Å. 8. The nonvolatile memory cell according to claim 4, further comprising an oxide spacer provided adjacent to a side surface of said floating gate and extending over a part of each of said source region and said drain region. 9. The nonvolatile memory cell according to claim 1, wherein said metal comprises an alloy. 10. The nonvolatile memory cell according to claim 1, wherein said metal includes aluminum, tungsten or copper. 11. The non-volatile memory cell according to claim 1, wherein said floating gate comprises a polycrystalline silicon material, tungsten polycide, or tungsten silicide. 12. The nonvolatile memory cell according to claim 1, wherein said nonvolatile memory cell comprises an EPROM cell, a flash EPROM cell or an EEPROM cell. 13. The floating gate extends across the entire channel region and the floating gate end is aligned with a corresponding end of the source and drain regions and serves to define the corresponding end. Item 2. The nonvolatile memory cell according to Item 1. 14. The non-volatile memory cell of claim 13, wherein said memory cell is adapted for use in a contactless substantially grounded array structure. 15. The nonvolatile memory cell of claim 1, wherein said floating gate extends across a first portion of said channel region and said control gate extends across a remaining portion of said channel region. 16. A first portion of the floating gate extends across a first portion of the channel region, a remaining portion of the floating gate extends across a portion of the drain region, and wherein the metal layer is 2. The non-volatile memory cell of claim 1, wherein said non-volatile memory cell extends across a remaining portion of said channel region. 17. The non-volatile memory cell of claim 1, further comprising a select gate, wherein said floating gate and said control gate extend across a first portion of said channel region, and wherein said select gate is said control gate. A portion of the gate and a remainder of the channel region and a portion of the source region extending insulated therefrom, wherein the floating gate and the control gate are made of a polysilicon material or tungsten polycide or tungsten silicide And the select gate includes a metal. 18. The non-volatile memory cell according to claim 1, further comprising a first well in said substrate and a second well in said substrate, wherein said floating gate covers the entire channel region. Extending transversely, the source and drain regions are in the first well, the first well is in the second well, and the source and drain regions are of one conductivity type. Wherein the first well has a conductivity type opposite to the one conductivity type, and the second well has a conductivity type opposite to the first well. 19. The non-volatile memory cell of claim 18, adapted for use in a contactless substantially grounded array structure. 20. A dual bit flash EEPROM.
A semiconductor substrate having a surface region of one conductivity type; a first drain region formed on the surface region and having a second conductivity type opposite to the one conductivity type; A drain region, a floating gate / control gate of a first stacked configuration, and a floating gate / control gate of a second stacked configuration provided at a distance from each other in the surface region between the first drain region and the second drain region. A floating gate / control gate; a select gate provided in the surface region between the floating gate / control gate in the first and second stacked configurations; and a first bit in contact with the first drain region. A second bit line that is in contact with the second drain region; and a second bit line that is in contact with the select gate and is substantially in contact with the first bit line and the second bit line. A dual-bit flash EEPROM cell including a vertically oriented word line, wherein the word line and the select gate are comprised of metal. 21. A non-volatile memory cell array formed in a silicon substrate, said plurality of non-volatile memory cells being formed on said silicon substrate in a state insulated from said substrate, and extending in a first direction across said array. A plurality of floating gates arranged along a line, and a plurality of continuous buried bit lines provided in the substrate between the lines of the floating gate, wherein a portion adjacent to the floating gate is a portion of the memory cell. At least one end of the source region and the drain region, that is, at least one end of the end of the floating gate is aligned, and the corresponding end is defined by using the one end. A plurality of continuous buried bit lines forming a source region and a drain region; A plurality of metal control lines extending in a state insulated from the switching gate, extending in a direction different from the first direction, and forming a control gate of the memory cell immediately above each of the cells. And a non-volatile memory cell array including a metal control line. 22. The non-volatile memory cell according to claim 21, wherein said control gate is subjected to an annealing step to remove defects from said source region and said drain region. 23. The nonvolatile memory cell of claim 21, wherein said floating gate is insulated from said channel region by a tunnel oxide dielectric layer. 24. The semiconductor device according to claim 24, wherein the control line is formed of a composite oxide-nitride-oxide-polysilicon (ONOP) dielectric or a composite oxide-polysilicon (OP) dielectric in the order of lower layer to upper layer. 22. The nonvolatile memory cell according to claim 21, which is insulated from the floating gate. 25. The non-volatile memory cell according to claim 24, wherein said oxide in said ONOP coupling dielectric and said OP coupling dielectric is a high temperature oxide (HTO) or a thermally oxidized oxide. 26. The non-volatile memory cell according to claim 24, further comprising an oxide spacer provided adjacent to a side surface of said plurality of floating gates and extending over a part of each of said source region and said drain region. 27. The non-volatile memory cell according to claim 21, wherein said metal includes aluminum, tungsten or copper. 28. A method of manufacturing a nonvolatile memory cell, comprising: (A) forming a first insulating material layer on a silicon substrate; and (B) forming a first insulating material layer on the silicon substrate. Forming a floating gate; and (C) aligning a source region and a drain region in the silicon substrate, wherein at least one of the ends of the floating gate is aligned with one corresponding end of the source region and the drain region. (D) forming a second insulating material layer on the floating gate; and (E) forming a metal control gate on the second insulating material layer. And a process comprising: 29. The method of claim 28, further comprising the step of: (F) annealing after step (C) and before step (D). 30. The method according to claim 29, wherein the first insulating material layer includes a tunnel oxide. 31. An oxide-nitride-oxide-polysilicon (O) layer in which the second insulating material layer is arranged from a lower layer to an upper layer.
NOP) coupled dielectric or oxide-polysilicon (O
30. The method of claim 29, comprising a composite layer of P) coupling dielectric. 32. The method according to claim 31, wherein the oxide in the ONOP coupling dielectric and the OP coupling dielectric is a high temperature oxide (HTO) or a thermally oxidized oxide. 33. The non-volatile memory cell fabrication of claim 31, wherein said ONOP coupling dielectric and said polysilicon in said OP coupling dielectric are undoped and have a thickness in the range of 100 Angstroms to 600 Angstroms. Method. 34. The non-volatile memory cell fabrication of claim 31, wherein said ONOP coupling dielectric and said polysilicon in said OP coupling dielectric are doped with impurities and have a thickness in the range of 400 Angstroms to 1000 Angstroms. Method. 35. A photoresist masking process when forming the floating gate in the step (B), and the floating gate is covered with a photoresist upon completion of the step (B). 30. The method according to claim 29, wherein the method is used so that the resist is removed. 36. The method of claim 31, wherein (G) forming an oxide spacer proximate to a side of the floating gate and extending over a portion of each of the source and drain regions. A method for manufacturing a nonvolatile memory cell, further comprising a step of forming before step (D) after step (D). 37. The method according to claim 29, wherein the metal includes an alloy. 38. The method according to claim 29, wherein the metal includes aluminum, tungsten or copper. 39. The method according to claim 29, wherein the floating gate comprises a polycrystalline silicon material, tungsten polycide, or tungsten silicide. 40. The method according to claim 29, wherein said nonvolatile memory cell comprises an EPROM cell, a flash EPROM cell or an EEPROM cell. 41. A method of manufacturing a nonvolatile memory cell in which a nonvolatile memory cell is formed in an array with at least one MOS peripheral transistor, comprising: (A) an insulating material layer on a silicon substrate including an array region and a peripheral region. (B) forming a layer of polycrystalline silicon material in the array region and the peripheral region, a plurality of polycrystalline silicon materials in the array region being arranged along a plurality of lines in a first direction. (C) forming a buried bit line continuous in the silicon substrate between the lines of the floating gate in the array region, A portion adjacent to the floating gate forms a source region and a drain region of the memory cell; Forming at least one end with corresponding ends of the source region and the drain region; (D) performing annealing; and (E) performing the annealing in the peripheral region. Forming at least one gate electrode of the at least one MOS peripheral transistor from crystalline silicon material; and (F) forming a source region and a drain region of the at least one MOS peripheral transistor in the peripheral region. (G) forming a second insulating material layer on the array region; (H) forming a contact hole in the peripheral region; and (I) forming a contact hole in the array region and the peripheral region. A plurality of control lines arranged on the floating gate in a direction different from the first direction in the array region; As defined by state Oite the contact with the source region and drain region of at least one MOS peripheral transistor, the nonvolatile memory cell manufacturing method comprising the steps of forming. 42. The method of claim 42, wherein: (J) a plurality of islands of field oxide on said array region of said silicon substrate, said plurality of islands of said floating gate in said first direction. A method of manufacturing a non-volatile memory cell, further comprising forming a plurality of islands of field oxide separated from each other along a line. 43. A photoresist masking process when partitioning said polycrystalline silicon material in said step (B), and said floating gate and said polycrystalline silicon material in said peripheral region at the completion of step (B). 42. The non-volatile memory of claim 41, wherein both are covered with photoresist and used to remove said photoresist from above both said floating gate and said polysilicon material in said peripheral region immediately prior to step (C). Method for manufacturing volatile memory cell. 44. The method of claim 42, wherein the steps are:
(F) is lightly doped diffusion (LDD) in the substrate in the state of (K) being close to the gate electrode and aligned with the end of the gate electrode.
Forming a region, (L) on a part of the LDD region and a part of the source region and the drain region in the array region in the vicinity of the side surface of the gate electrode and the side surface of the floating gate. (M) forming the source region and the drain region aligned with the oxide spacer in the substrate in proximity to the gate electrode. Memory cell manufacturing method. 45. The method according to claim 41, wherein the first insulating material layer contains a tunnel oxide. 46. An oxide-nitride-oxide-polysilicon (O) layer in which the second insulating material layer is arranged from a lower layer to an upper layer.
NOP) coupled dielectric or oxide-polysilicon (O
The method of claim 44, comprising P) a composite layer of coupling dielectric. 47. The method according to claim 46, wherein said oxide in said ONOP coupling dielectric and said OP coupling dielectric is a high temperature oxide (HTO) or a thermally oxidized oxide. 48. The method of claim 46, wherein (N) removing said polysilicon layer portion of said ONOP coupling dielectric or a region of said OP coupling dielectric between said control lines. A method for manufacturing a nonvolatile memory, further comprising the step of removing after the step. 49. A mask is used to partition said metal layer in said step (I), said mask being used for removing said polysilicon layer in said step (N) and remaining after said step (N). 49. The method according to claim 48, wherein the metal layer and the polycrystalline silicon layer in the ONOP composite layer are aligned with each other. 50. The method according to claim 42, wherein said metal includes aluminum, tungsten or copper.