JPH11311865A - Highly accurate resist patterning method on substrate having difference in level - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reliability by eliminating a CD(critical dimension) control error. SOLUTION: As a highly accurate resist patterning method on a substrate having a difference in a level, the difference in the level of a base is flattened by forming flattening film 21 on the substrate 1 having the difference in the level, and reflection preventive film 22 is formed on it so as to be flat, and the highly accurate patterning of a resist 23 is executed on it. Thus, the appearance of a standing wave effect is stopped, and the CD control error caused by the standing wave effect is eliminated. In the case that the flattening film 21 consists of hydrogen silosesquioxane, it is similarly removed by alkali developer as the resist or the like. Thus, a selection ratio for SiO2 film, polycrystal silicon and SiN film is set to be large, and the CD control error of a base pattern caused by over-etching at the time of removing the flattening film is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for patterning a resist with high accuracy on a substrate having a step.

[0002]

2. Description of the Related Art Generally, an integrated circuit generally operates normally when a large number of fine semiconductor elements are integrated on a substrate and each semiconductor element operates normally. Here, in each semiconductor element, for example, when the dimensions of the gate electrode and the like change, the operation such as the threshold voltage also changes. For this reason, each semiconductor element is required to be formed according to design dimensions. Forming control according to this design dimension is critical
It is called critical dimension (CD) control.

[0003] Incidentally, this type of integrated circuit employs a lithography technique having steps of, for example, applying a resist on a layer on a substrate surface, patterning the resist by exposure and development, etching a layer exposed by patterning, and removing the resist. And an etching technique.

[0004] Therefore, the above-mentioned CD control requires higher precision of a lithography technique represented by resist patterning. For example, using a short wavelength exposure apparatus such as a KrF excimer laser having a wavelength of
It is also required to develop a highly accurate resist patterning method for forming a resist layer having a width of nm according to design dimensions.

However, during exposure, a standing wave whose light intensity spatially fluctuates due to light interference of each reflected light from a medium having a different refractive index. This standing wave has the effect of periodically changing the resist line width like a wavefront along the reflected optical axis. The standing wave effect has a greater adverse effect on finer semiconductor elements that require higher precision. Therefore, a flattening technology using an anti-reflection coating (hereinafter, referred to as ARC) film or CMP (chemical mechanical polishing) is used. Preferably, it is suppressed.

FIG. 5 is a sectional view showing a part of a conventional active area (hereinafter, referred to as AA) lithography process. 5, a plurality of deep trenches (hereinafter, referred to as DT) 3 are formed in a semiconductor layer 2 on a substrate 1, and a polycrystalline silicon 5 is provided in each DT 3 via a color oxide film 4. 2 is buried to a height of 50 nm below the surface. The semiconductor layer 2 on the surface between the respective DT3 via the SiO ₂ film 6 of 8nm thickness 100 to 15
A SiN film 7 having a thickness of 0 nm is formed. That is, the substrate 1 has the surface of the polycrystalline silicon 5 in each DT 3,
Each DT 3 has a step having a height difference of about 150 nm from the surface of the SiN film 7.

Here, an ARC film 8 for preventing the above-mentioned standing wave effect is formed on the entire surface of the substrate 1, and a resist layer 9 is formed on the ARC film 8. However, the ARC film 8 formed on the step has an uneven thickness distribution.

Similarly, the resist layer 9 formed on the ARC film 8 so as to bury the step is formed in the concave region B above the DT3.
And the convex region A above the SiN film 7 are approximately 150 n
m different thicknesses.

Such an uneven distribution of the resist thickness is as follows.
Since the best focus position and the best dose condition differ between the two regions A and B, the standing wave effect
There is a problem that a CD control error occurs.

[0010] Further, the uneven distribution of the ARC thickness is caused by the ARC
In order to make it difficult to etch the film 8 using RIE or the like, over-etching for complete etching is required. However, over-etching causes a reduction in the thickness of the resist, and the over-etching causes an increase in the reduction in the thickness of the resist, which tends to cause a CD control error.

The above-mentioned problems are not peculiar to the AA lithography process, and are difficult to achieve on a substrate having a step.
This is common to resist patterning using C. For example, FIG. 6 is a sectional view showing a part of a conventional gate conductor (hereinafter, referred to as GC) lithography process. In FIG. 6, each DT3 similar to that in FIG. 5 has a shallow trench formed by burying the oxide layer 10 after the region between the DT3s is removed shallowly by etching including the side half of each DT3. An isolation (shallow trench isolation; hereinafter, referred to as STI) region is provided.

Here, the substrate 1 has a surface of about 50 nm between the surface of the STI region and the surface of the other region outside the DT3.
Has a height difference of An oxide film 11 for a gate oxide film, a polycrystalline silicon wiring layer 12,
The WSi wiring layer 13 and the SiN layer 14 are sequentially formed. An ARC film 15 and a resist layer 16 are sequentially formed on the SiN layer 14. However, the resist layer 16 is
Corresponding to the step described above, a concave region C above the STI region;
The thickness of the convex region D above the region outside each DT is different from that of the convex region D by about 50 nm.

Similarly, the uneven distribution of the resist thickness causes a CD control error due to the standing wave effect. Further, the ARC film 15 has a problem that it needs to be over-etched, which is non-uniformly distributed as described above, and is likely to cause a CD control error.

[0014]

As described above,
The patterning of the resist on the substrate having a step has a problem that the step makes the thickness distribution of both the ARC film and the resist layer non-uniform, causing a CD control error and lowering the reliability.

The present invention has been made in view of the above circumstances, and has as its object to provide a high-precision resist patterning method on a substrate having steps, which can eliminate CD control errors and improve reliability. .

[0016]

In order to achieve the above object, a first aspect of the present invention is a high-precision resist patterning method on a substrate having a step, the method comprising: (planarization) Process of forming film and anti-reflection to prevent reflection of light for exposure on planarization film
(anti-reflection coating; ARC) A step of forming a film, a step of applying a photoresist on the ARC film, and patterning the photoresist by exposure and development to form an AR.
Forming a photoresist pattern so as to partially expose the C film, etching the exposed ARC film, and then etching a region reaching a middle depth of the substrate via the planarization film; Removing the photoresist and the ARC film after the etching and removing the flattening film.

Further, a second invention is a method for patterning a resist with high precision on a substrate having a step, wherein a step of forming a wiring layer on the substrate, a step of forming an insulating layer on the wiring layer, A step of forming a flattening film for flattening the surface on the insulating layer; a step of forming an antireflection film for preventing reflection of light for exposure on the flattening film; and A step of applying a photoresist, a step of patterning the photoresist by exposure and development to partially expose an anti-reflection film, and a step of extending the exposed anti-reflection film to a wiring layer via a planarizing film and an insulating layer. The method includes a step of etching the region, a step of removing the photoresist and the antireflection film after the etching, and a step of removing the flattening film.

Therefore, in the first and second aspects of the present invention, the substrate having the local step is flattened by the flattening film so that the step is flattened. Since the ARC film and the resist layer are sequentially formed on the flattening film, both the ARC film and the resist layer can be formed to have a uniform thickness. Here, since the resist layer can be formed to have a uniform thickness, the influence of the standing wave effect can be eliminated, and the CD control error can be eliminated to improve the reliability. In addition, since the ARC film can be formed uniformly,
The over-etching time for completely removing the RC film can be reduced. Further, for removing the flattening film, an alkali solution or the like that can have a large etching selectivity with respect to the underlying oxide film, silicon nitride film, and polycrystalline silicon film can be used, so that only the flattening film can be selectively removed .

The present invention is also effective in a fine manufacturing process in which the step is, for example, 150 nm or less or 50 nm or less. The flattening film located immediately below the ARC film has the following characteristics (1) to (4) in addition to the above-described effects when the hydrogen silsesquioxane is used as a material. (1) A flat surface is easily obtained by coating. That is, it is easy to obtain a flat surface by a coating method applied to a resist film such as spin coating. After application and baking of this film, the planarization film changes to properties similar to a SiO ₂ film. The DT step is completely embedded in the planarization film in the case of AA and GC lithography. (2) The thickness control of the wafer is good. For example, the variation in the film thickness in the wafer is less than 20% of the applied film thickness. For example, in the case of applying 100 nm, there is a thickness variation of 15 nm in the wafer. (3) The flattening film has dry etching (RIE) characteristics similar to the SiO ₂ film. After the ARC dry etching and the AA dry etching by RIE, for example, the thickness distribution of the flattening film along the depth direction of the trench is good. Then, the over-etching time of the ARC film can be reduced due to the uniform ARC film thickness. That is, a CD control error caused by over-etching can be reduced. This is useful for forming a fine semiconductor element as designed according to a highly accurate resist pattern distribution after etching the ARC film. (4) The film can be easily removed by an etching solution such as a developer.

To remove the planarization film after the process,
When the flattening film is made of hydrogen silsesquioxane, an alkali solution similar to a resist developer is effective. The same system as the resist developer can be used to remove the planarization film.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. (First Embodiment) A high-precision resist patterning method according to a first embodiment of the present invention will be described. First, a planarization film and an ARC film commonly used in each embodiment will be described.

As the material for the flattening film, hydrogen silosesquioxane is preferably used from the viewpoints of surface flatness, dry etching characteristics and ease of removal. Hydrogen silsesquioxane is also commercially available from Dow Corning under the trade name flowable oxide (FOX) and is therefore also referred to as FOX.

The optical characteristics of this FOX film are very similar to those of a quartz substrate made of SiO ₂ , and the thickness variation (± 3σ) of less than 1% is similar to that of SOG (spin-on-glass). However, unlike SOG, the FOX film has a property of being dissolved by an alkaline solution such as a developer used for resist patterning. That is, at the time of removal,
Since a large selection ratio can be obtained with respect to the SiO ₂ film, the poly-Si film, and the SiN film, no CD control error occurs in the pattern formed on the base due to over-etching. The alkaline liquid preferably has a pH of, for example, 8 to 13. Specifically, TMAH (tetramethylammonium hydroxide) (CH ₃ ) ₄ NOH or choline (trimethyldioxyethyl ammonium hydroxide) (CH ₃ ) is used. ₃ N (CH ₂ CH ₂ OH) can be used.

Typical properties of the FOX membrane are shown below (this was described in the Dow Corning brochure). Solid content range Up to 40% Coating thickness range Up to 1000 nm Thickness variation (± 3σ) Less than 1% Small amount of metal impurities (in solution) Less than 10 ppb Humidity absorption Less than 1% Mechanical stress range -1 × 10 ⁸ -1 × 10 ⁹ dynes / cm ² Refractive index 1.40 to 1.45 Dielectric constant at 1 MHz 3.3 to 4.2 Note that the refractive index and the dielectric constant at 1 MHz are converted (convex).
rsion) controlled by conditions.

Such a FOX film is, for example, about 3000
A spin speed of between -5000 rev / min is applied by the preferred spin coating and is about 150-4
1 minute at about 150 ° C. at a temperature between 50 ° C., 1 minute at 250 ° C.
Bake at 450 ° C. for 60 minutes for 60 minutes. FOX
The preferred thickness of the film is between about 50-800 nm.

On the other hand, the material of the ARC film includes, for example, a polymer, and this kind of polymer is produced, for example, as TSP-4 type by Tokyo Ohka Kogyo Co., Ltd. of Japan.
Examples of other materials for the ARC film are perfluoroalkyl polyethers supplied by Montefloss.
polyether; PFAE), polysiloxane (SH410) supplied by Toray Industries, Inc., polyethylvinylether (PEVE) produced by Scientific Polymer Products, Inc., and supplied by Kuraray Co., Ltd. Polyvinyl alcohol (polyvinylalc
ohol; PVA) can be used respectively.

The PFAE can be removed by Freon TF supplied by Mitsui / DuPont Fluoro Chemical Company. The polysiloxane is removable in xylene. PEVE and PVA are each soluble in water.

Each ARC film is, for example, about 3000 to 500
A spin rate of between 0 revolutions / minute is applied by the preferred spin coating and formed by baking at a temperature between about 80-200 ° C. for about 1 minute. The preferred thickness of the ARC film is between about 30-80 nm.

Next, a high-precision resist patterning method using the above-described FOX film and ARC film will be described. 1 and 2 are cross-sectional views of AA lithography for explaining the high-accuracy resist patterning method. It should be noted that like reference numerals in the accompanying drawings indicate equivalent parts in many figures.

As shown in FIG. 1A, a plurality of DTs 3 are formed in a semiconductor layer 2 on a substrate 1, and polycrystalline silicon 5 for a gate is formed in each DT 3 via a color oxide film 4. It is buried to a height of 50 nm below the surface of the layer 2. 8n on the surface of the semiconductor layer 2 between each DT3
A 100-150 nm-thick SiN film 7 as a CMP stopper is formed via an m-thick SiO ₂ thin film 6. That is, the substrate 1 has a step having a height difference of about 150 nm between the surface of the polycrystalline silicon 5 in each DT 3 and the surface of the SiN film 7 between each DT 3.

Here, unlike the conventional case, the FOX film 21 is formed on the entire surface of the substrate 1 so as to bury the step and flatten it. The FOX film 21 has a thickness of about 2 on DT3.
It is formed by spin coating so as to have a thickness of 00 nm and a thickness of about 50 nm on the SiN film 7. Thereafter, in order to dry the FOX film 21, 150 ° C. (1
(Minute) + 200 ° C. (1 minute) + 350 ° C. (1 minute), the entire substrate 1 is baked.

Next, as shown in FIG. 1B, an ARC film 22 is formed on the entire surface of the FOX film 21. ARC film 22
A resist layer 23 is selectively formed thereon by coating, drying, exposing, and developing so as to expose a half upper region including surfaces of the DTs 3 facing each other. In addition,
The FOX film 21 has a property of dissolving in an alkali developing solution for resist patterning, but does not dissolve here because it is covered with the ARC film 22.

Next, as shown in FIG. 2A, the ARC film 22 exposed between the resist layers 23 is formed by RIE (reacti
ve ion etching). Then, FOX
The film 21 and the region between DT3 including the side half of each DT3 are:
By non-selective RIE, it is etched and removed shallowly. Thus, the STI region 24 is formed.

Next, as shown in FIG. 2B, after the resist layer 23 and the ARC film 22 are removed by, for example, O ₂ ashing or the like, the FOX film 21 is removed by the above-described alkali developing solution for resist patterning. Is dissolved and removed. That is, the FOX film 21 is selectively removed from the substrate 1 with respect to other patterns of the base.

As described above, according to the first embodiment,
Substrate 1 having a local step is formed of FOX as a planarizing film.
By forming the film 21, the step is flattened and the FO is formed.
The surface of the X film 21 becomes flat. A on the FOX film 21
Since the RC film 22 and the resist layer 23 are sequentially formed,
Both the RC film 22 and the resist layer 23 can be formed with a uniform thickness. Here, since the resist layer 23 can be formed to have a uniform thickness, the influence of the standing wave effect can be eliminated, the CD control error of the resist pattern due to the standing wave effect can be eliminated, and the controllability of the pattern dimension can be improved. The reliability of element characteristics can be improved.

Further, since the ARC film 22 can be formed uniformly, the over-etching time for completely removing the ARC film 22 can be reduced. Therefore, it is possible to prevent the resist film from being reduced due to the over-etching of the ARC film 22, and to eliminate the CD control error due to the reduced resist film.

Further, the FOX film 21 has a characteristic of a thickness variation (± 3σ) of less than 1% and is easily and reliably applied evenly and evenly to a stepped base by using spin coating. be able to.

Further, since the FOX film 21 has a dry etching characteristic similar to SiO ₂ , it is possible to perform RIE simultaneously with the underlying SiO ₂ film or the like with high accuracy corresponding to a highly accurate resist pattern. C at dry etching
D control errors can be eliminated.

Further, since the FOX film 21 is dissolved by the alkaline developer, the SiO ₂ film 6 and the polycrystalline silicon 5
And a high selectivity with respect to the SiN film 7, and a base, SiO ₂ film,
CD control errors in the Si ₃ N ₄ film, the polycrystalline silicon film and the like can be eliminated.

The FOX film 21 is formed by using an alkaline solution.
Can be selectively removed from the substrate 1, which can be realized by a simple process. Similarly, since the same system as the resist development can be used for removing the FOX film 21, the existing equipment can be effectively used. (Second Embodiment) FIGS. 3 and 4 are sectional views of GC lithography for explaining a high-accuracy resist patterning method according to a second embodiment of the present invention.

As shown in FIG. 3A, the oxide layer 10 is embedded in each DT3 after the region between the DT3s is removed shallowly by etching including the side half of each DT3. Thus, an STI region 24 is provided. The substrate 1 has a step having a height difference of about 50 nm between the surface of the STI region 24 and the surface of the other region outside the DT3. On each region, an oxide film 11 for a gate oxide film,
Polycrystalline silicon wiring layer 12, WSi wiring layer 13, and Si
N layers 14 are sequentially formed. The SiN layer 14 has a step difference of about 50 nm between the concave region above the STI region 24 and the region outside each DT3 corresponding to the above-mentioned step.

Here, unlike the conventional case, the FOX film 31 is formed on the entire surface of the SiN layer 14 so as to bury the step and flatten it. The FOX film 31 is formed by spin coating so that the concave region has a thickness of about 100 nm and the convex region has a thickness of about 50 nm. Thereafter, in order to dry the FOX film 31, the entire substrate 1 is baked, for example, under the above-described baking conditions.

Next, as shown in FIG. 3B, an ARC film 32 is formed on the entire surface of the FOX film 31. ARC film 32
On top, a resist layer 33 is selectively formed by application, drying, exposure, and development so as to expose an upper region between the DTs 3 and the like.

Next, as shown in FIG. 4A, the ARC film 32 exposed between the respective resist layers 33 is formed by RIE.
Removed. Thereafter, the FOX film 31 and the Si immediately below the FOX film 31 are formed.
The N layer 14 is removed by RIE. As a result, a SiN cap layer 14a having a predetermined pattern shape is formed.

Next, as shown in FIG. 4B, after the resist layer 33 and the ARC film 32 are removed by O ₂ ashing or the like, the FOX film 31 is removed by the above-described alkali developing solution.
Is melted and separated from the substrate 1 and removed. Thereafter, the WSi wiring layer 13 and the polysilicon wiring layer 12 are etched using the SiN cap layer 14a as a mask.

As described above, according to the second embodiment,
An FOX film 31 is formed on the substrate 1 having a step to flatten the underlying step, and an ARC film 32 is formed flat thereon,
Since a step of patterning the resist layer 33 with high accuracy is included thereon, the same effect as in the first embodiment can be obtained. (Other Embodiments) The above-described first and second embodiments use the RI
Although the case where the alkali developing solution is used in the step of removing the FOX films 21 and 31 after E has been described, the present invention is not limited to this, and a modification may be made such that a dilute HF solution is used instead of the alkali developing solution. Even with such a modification, the present invention can be implemented in the same manner and a similar effect can be obtained.

The steps of the substrate 1 and the FOX films 21 and 31
Needless to say, the thicknesses of the ARC films 22 and 32, the materials of the ARC films 22 and 32, the spin coating rotation speed, the baking conditions, and the like can be appropriately changed.

In the second embodiment, after the FOX film 31 is removed, the base is etched using the SiN cap layer 14a as a mask. However, the base may be etched with the FOX film 31 remaining. . In addition, the present invention can be implemented with various modifications without departing from the scope of the invention.

[0049]

As described above, according to the present invention, C
It is possible to provide a highly accurate resist patterning method on a substrate having a step, which can eliminate D control errors and improve reliability.

[Brief description of the drawings]

FIG. 1 is a process sectional view of AA lithography for describing a high-precision resist patterning method according to a first embodiment of the present invention.

FIG. 2 is a process sectional view of AA lithography in the embodiment.

FIG. 3 is a process sectional view of GC lithography for describing a high-accuracy resist patterning method according to a second embodiment of the present invention.

FIG. 4 is a process cross-sectional view of GC lithography in the embodiment.

FIG. 5 is a sectional view showing a part of a conventional AA lithography process.

FIG. 6 is a sectional view showing a part of a conventional GC lithography process.

[Explanation of symbols]

1 ... substrate 2 ... semiconductor layer 3 ... DT 4 ... collar oxide 5 ... polycrystalline silicon 6 ... SiO ₂ film 7 ... SiN film 10 ... oxide layer 11 ... oxide film 12 ... polycrystalline silicon wiring layer 13 ... WSi wiring layer 14 SiN layer 14a SiN cap layer 21, 31 FOX film 22, 32 ARC film 23, 33 Resist layer 24 STI region

Claims (8)

[Claims] 1. A high-precision resist patterning method on a substrate having a step, comprising: forming a planarization film for planarizing a surface on the substrate; Forming an anti-reflection film for preventing reflection of light; applying a photoresist on the anti-reflection film; patterning the photoresist by exposure and development to partially form the anti-reflection film Exposing, etching a region extending from the exposed anti-reflection film to an intermediate depth of the substrate via the planarizing film, and after the etching, removing the photoresist and the anti-reflection film. A highly accurate resist patterning method on a substrate having a step, comprising: a step of removing; and a step of selectively removing the flattening film with respect to a base film. 2. The method according to claim 1, wherein the step is 150 nm or less. 3. A high-precision resist patterning method on a substrate having a step, wherein: a step of forming a wiring layer on the substrate; a step of forming an insulating layer on the wiring layer; Forming a flattening film for flattening the surface, forming an antireflection film on the flattening film to prevent reflection of light for exposure, and forming a photo on the antireflection film. Applying a resist, patterning the photoresist by exposure and development to partially expose the antireflection film, and etching the planarizing film and the insulating layer from the exposed antireflection film. Removing the photoresist and the antireflection film after the etching; selectively removing the planarizing film; and etching the wiring layer using the insulating layer as a mask. Precision resist patterning process on a substrate having a step, characterized in that it contains the step of packaging. 4. The method according to claim 3, wherein the step is 50 nm or less. 5. The stepped substrate according to claim 1, wherein a material of the flattening film is hydrogen silosesquioxane. High precision resist patterning method. 6. The method according to claim 5, wherein the flattening film is formed by spin coating. 7. The method according to claim 5, wherein in the removing step, the flattening film is dissolved with an alkaline solution.
7. A method for patterning a resist with high precision on a substrate having a step according to claim 6. 8. The method according to claim 5, wherein the etching step is reactive ion etching.