JPH11308872A - Power supply - Google Patents

Abstract

PROBLEM TO BE SOLVED: To sufficiently raise the carrier frequency of a PWM signal, by multiplying the PWM signal obtained through pulse width calculation to a complex pulse for each period, and then outputting it to each switching element. SOLUTION: DSP 8 performs the pulse width calculation of PWM signal due to the feedback control and momentary value control of an output current of a power supply, but it also outputs the data obtained by dividing the data of pulse width into 1/N as the final result of calculation. Therefore, when the pulse output number data N is set to 4 (N=4), the frequency data Δt/4 is latched to a latch circuit 17 of the frequency control circuit 13, while the pulse output number data N=4 is latched to a latch circuit 31 of the operation intermitting means 30. Since the pulse width data ΔW/4 is outputted to the pulse width control circuit 12 for every constant period Δt, the carrier frequency in the constant period Δt of the PWM signal becomes four times. As a result, each switching element can be controlled with a higher frequency obtained by multiplying the carrier frequency of PWM signal by N times.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply device for controlling output by pulse width control (hereinafter referred to as PWM control).

[0002]

2. Description of the Related Art In general, in a power supply device using PWM control, as shown in FIG. 5, a time axis t is equally divided into small sections Δt, and a time integration ∫v _L of a voltage v _L of each small section Δt. (t) dt
Is controlled to change the pulse width of each minute section Δt such that (t) = ∫v _L (t) dt.

[0003] As a conventional power supply device for performing such PWM control, a power supply device for system interconnection in a photovoltaic power generation system will be described as an example.

FIG. 6 is a block diagram showing the whole of the power supply device for system interconnection.

The power supply device shown in FIG. 6 is a so-called high-frequency transformer insulation system, which converts the DC output of a solar cell into high-frequency AC, insulates it with a high-frequency transformer, and then temporarily converts it into DC. Then, it is converted again to the commercial frequency alternating current.

More specifically, in FIG. 6, reference numeral 1 denotes a high-frequency inverter, which is composed of four switching elements (here, transistors) Q1 to Q4,
ON / OFF control is performed by a signal. Reference numeral 2 denotes a high-frequency transformer, which has a function of insulating a boost and an input / output. Reference numeral 3 denotes a full-wave rectifier circuit in which four diodes are bridge-connected, and performs full-wave rectification of the high-frequency AC obtained by the high-frequency inverter 1.

Reference numeral 4 denotes a DC filter that cuts high-frequency components and converts the commercial system waveform into a full-wave rectified waveform. Reference numeral 5 denotes a low-frequency inverter, which is composed of four switching elements (transistors in this case), and is connected to a commercial system by converting a voltage waveform generated in the preceding stage into an alternating current of a commercial frequency (50/60 Hz). And output. Reference numeral 6 denotes an AC filter that removes high-frequency components and has a function of an interconnection reactor.

Reference numeral 7 'denotes a control unit which controls the switching operation of the high frequency inverter 1 and the low frequency inverter 5.

FIG. 7 is a block diagram showing a specific configuration of the control unit 7 'provided in the power supply device shown in FIG.

In FIG. 7, reference numeral 8 'denotes a digital signal processor (hereinafter referred to as DSP); 9', a pulse generation circuit; 10, a microcomputer; and 11, an A / D converter.

The DSP 8 'calculates the pulse width of the PWM signal (in this case, the period during which the switching elements Q1 to Q4 of the high-frequency inverter 1 are turned on) by feedback control and instantaneous value control of the output current of the device, and calculates the pulse width. The pulse width data is output to the pulse generation circuit 9 'every fixed period Δt (see FIG. 5).

In this case, the feedback of the output current of the DSP 8 and the method of calculating the pulse width of the PWM signal by the instantaneous value control are well-known techniques, and the description thereof will be omitted.

On the other hand, the pulse generation circuit 9 'generates and outputs a PWM signal to the high-frequency inverter 1 based on the pulse width data from the DSP 8'. Also, microcomputer 1
0 is a low-frequency inverter 5 that is turned back in synchronization with the commercial system
Control and various protection. Further, the AD converter 11 detects a signal necessary for control and performs digital conversion.

The pulse generation circuit 9 'includes a pulse width control unit 10 and a PWM signal output unit 20.

The pulse width control unit 10 determines the period of the pulse width of the PWM signal for turning on each of the elements Q1 to Q4 of the high-frequency inverter 1, and latches the pulse width data supplied from the DSP 8 '. 14 and
It is composed of a timer 15 which starts counting time by a latch signal from the DSP 8 ', and a comparator 16 which compares the output of the latch circuit 14 with the output of the timer 15.

The PWM signal output section 20 generates a PWM signal having a pulse width determined by the pulse width control section 12, and includes three flip-flops 21, 22,
23 and a selector 24. The two flip-flops 21 and 22 on the upper stage are for generating a PWM signal, and the one flip-flop 23 on the lower stage is a switching signal for the selector 24 to alternately select the flip-flops 21 and 22. Is to be output.

Next, P in the control unit 7 'shown in FIG.
The operation of generating the WM signal will be described.

The control unit 7 'of the power supply device for system interconnection
Performs the current control for controlling the output current. This current control detects the output current of the AC filter 6 and
From the digitally converted value by the D converter 11, the DSP
At 8 ', feedback control for calculating the pulse width of the PWM signal is performed by software.

That is, the DSP 8 'calculates the pulse width of the PWM signal at each instant based on the value of the output current, and outputs the pulse width data to the pulse generation circuit 9' at regular intervals Δt (see FIG. 5). . Here, the frequency (= 1 / Δt) at which the DSP 8 ′ outputs pulse width data corresponds to the basic carrier frequency of the PWM signal, and this carrier frequency changes even if the pulse width of the PWM signal changes. There is no.

When the DSP 8 'outputs pulse width data to the pulse width control unit 12 of the pulse generation circuit 9',
At the same time, a latch signal is output.

As a result, the pulse width data is latched in the latch circuit 14 of the pulse width control unit 12, and at the same time, the timer 15 starts counting the time using the latch signal as a trigger.

Further, in the PWM signal output unit 20,
Assuming that the upper flip-flop 21 has been selected by the selector 24 in advance, the upper flip-flop 21 is set by the latch signal, and the output Q of the upper flip-flop 21 becomes high level.

The output Q of the flip-flop 21 is
Becomes high level, the flip-flop 23
Is reset, the selector 24 switches to select the flip-flop 22 on the lower side.

The pulse width data latched by the latch circuit 14 is compared with the time data measured by the timer 15 by the comparator 16, and if the two values match, the previously set flip-flop is set. 21 is reset. Therefore, this flip-flop 21
Thus, a PWM signal having an ON time corresponding to the pulse width data given from the DSP 8 is output to the switching elements Q1 and Q4 of the high frequency inverter 1.

When the time period Δt has elapsed, the DSP
8 'again outputs the pulse width data and the latch signal to the pulse width control unit 12 of the pulse generation circuit 9' again.

Therefore, at this time, a PWM signal having an ON width time corresponding to pulse width data is output from the flip-flop 22 on the lower side of the PWM signal output section 20 to the switching elements Q2 and Q3 of the high frequency inverter 1. You.

In this manner, each of the switching elements Q1 to Q4 of the high-frequency inverter 1 is switched while changing the pulse width in time series at a frequency corresponding to the carrier frequency of the PWM signal.

[0028]

However, the configuration of the control section 7 'shown in FIG. 7 has the following problems.

To reduce the size of the entire power supply, the switching elements Q1 to Q4 of the high-frequency inverter 1 are turned on.
It is sufficient that the high-frequency transformer 2 can be further miniaturized by increasing the OFF frequency, but for that purpose, it is necessary to increase the carrier frequency of the PWM signal.

Here, when all the pulse width calculations of the PWM signal are performed by software, the required calculation result is obtained and the PWM
There is a limit on the software processing speed before a signal is output, and it is not possible to set a higher carrier frequency.

In order to increase the carrier frequency,
When all the pulse width calculations of the PWM signal are realized by hardware, the circuit scale becomes larger than the current state, and it is not possible to sufficiently reduce the size of the device.

The present invention has been made to solve such a problem, and the PWM signal added to the high-frequency inverter can be added to the conventional circuit configuration by only slightly changing the software and adding hardware. It is an object to reduce the size of the entire device by enabling the carrier frequency to be sufficiently increased.

[0033]

According to the present invention, in order to solve the above-mentioned problems, a pulse width calculation is performed for each period corresponding to a carrier frequency of a PWM signal, and a PWM signal having a pulse width based on the calculation result is obtained. Is generated, and the switching device is turned ON / OFF by the PWM signal in the following manner.

That is, in the invention according to claim 1, a frequency conversion means for multiplying a PWM signal obtained by the pulse width calculation into a plurality of pulses for each one cycle, and outputting the multiplied PWM signal to each of the switching elements. It has.

According to the second aspect of the present invention, in the first aspect,
Wherein the frequency of the signal multiplied by the frequency conversion means is set to be an integral multiple of the carrier frequency of the PWM signal.

According to the third aspect of the present invention, in the power supply device according to the first or second aspect, when the carrier frequency of the PWM signal changes during the output period of the multiplied signal and the period is extended. Comprises an operation suspending means for turning off all of the switching elements during a period after the output of the multiplied signal until the result of calculating the pulse width of the next PWM signal is obtained.

According to this configuration, even if the pulse width calculation of the PWM signal based on the software is relatively slow, it is possible to generate a PWM signal having a high carrier frequency, thereby realizing the miniaturization of the power supply device. it can.

[0038]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The overall configuration of a power supply device for system interconnection according to this embodiment is basically the same as that shown in FIG. 7, but the configuration of a control unit 7 is different from that of a conventional one. Are different. Therefore, here, the contents of the control unit 7 will be described in detail with reference to FIG.

FIG. 1 is a block diagram showing a specific configuration of a control unit 7 provided in a power supply device for system interconnection according to this embodiment, and a portion corresponding to the prior art shown in FIG. Assign a sign.

In FIG. 1, reference numeral 7 denotes an entire control unit.
8 is a DSP, 9 is a pulse generation circuit, 10 is a microcomputer, 1
1 is an A / D converter. Note that the configurations of the microcomputer 10 and the AD converter 11 are the same as those of the prior art shown in FIG. 7, and therefore, detailed description is omitted here.

The DSP 8 performs feedback control of the output current of the power supply unit and P
The pulse width calculation of the WM signal is performed. In this case, data obtained by further dividing the data of the pulse width ΔW obtained by the conventional calculation into N equal parts (that is, data of ΔW / N) is output as the final calculation result. That is, ΔW / N is output as pulse width data. However, this pulse width data ΔW
/ N is output to the pulse generation circuit 9 at regular intervals Δt corresponding to the carrier frequency, as in the related art. Therefore, as the pulse width calculation processing of the DSP 8, it is only necessary to add a 1 / N division processing flow to the conventional configuration.

Further, the DSP 8 sets the fixed period Δt to 1 /
The value of N is output to the pulse generation circuit 9 as frequency data, and the value of N is output as pulse output frequency data within a fixed period Δt.

The pulse generation circuit 9 generates a PWM signal for the high-frequency inverter 1 based on the data ΔW / N, Δt / N, and N provided from the DSP 8, and includes a pulse width control unit 12, a frequency control unit 13, It includes a PWM signal output unit 20, an OR gate 27, and an operation interruption unit 30.

The basic contents of the pulse width control section 12 and the PWM signal output section 20 constituting the pulse generation circuit 9 are the same as those of the prior art shown in FIG.

That is, the pulse width control unit 12
A latch circuit 14 for latching the pulse width data ΔW / N given from the counter 8, a timer 15 for starting time counting by a latch signal from the DSP 8, and a comparator 16 for comparing the output of the latch circuit 14 with the output of the timer 15 Become. The PWM signal output unit 20 includes three flip-flops 21, 22, 23 and a selector 24.

The frequency control unit 13 divides a fixed period Δt corresponding to a conventional carrier frequency into N equal parts (= Δt / N).
A latch circuit 17 for latching the frequency data Δt / N provided from the DSP 8, a timer 18 for starting clocking by a latch signal from the DSP 8, and comparing the output of the latch circuit 17 with the output of the timer 18. And a comparator 19.

The DSP 8 and the frequency control unit 13 constitute a frequency conversion means in the claims.

On the other hand, when the base frequency of the PWM signal is changed and the period is extended, the operation interrupting means 30 operates the high-frequency inverter 1 during the period until the next PWM signal pulse width calculation result is obtained. Each switching element Q
1 to Q4 are all turned off, and the DSP
A latch circuit 31 for latching the pulse output number data N given from the counter 8; and a counter 32 for counting the coincidence signal output from the comparator 16 of the pulse width control unit 12.
A comparator 33 that compares the output of the latch circuit 31 with the output of the counter 32;
Is set by the latch signal output to the flip-flop 3 and reset by the output of the comparator 33
4 and two AND gates 25 and 26 for interrupting the PWM signal output from the PWM signal output unit 20 by the reset output of the flip-flop 34.

Next, the pulse control operation in the control unit 7 of the power supply device having the above configuration will be described with reference to the timing charts shown in FIGS. Here, a case where the pulse output frequency data N = 4 is described.

The DSP 8 previously stores the frequency data Δt / in the latch circuit 17 of the frequency control unit 13 of the pulse generation circuit 9.
N (where N = 4) and the pulse output frequency data N (where N = 4) is stored in the latch circuit 31 of the operation suspending means 30.
Are output together with the latch signal.

Therefore, the frequency data Δt / 4 is stored in the latch circuit 17 of the frequency control unit 13 by the operation suspending means 30.
Latch circuit 31 latches pulse output frequency data N = 4.

Further, the DSP 8 divides the data of the pulse width ΔW obtained by the pulse width calculation of the PWM signal by the feedback control and the instantaneous value control of the output current of the power supply device into N (= 4) equal parts to obtain the final pulse width. The pulse width data ΔW / 4 is output to the pulse width control unit 12 of the pulse generation circuit 9 at regular intervals Δt as data ΔW / 4. In the example of FIG. 2, the pulse width data Δ at each of the times t ₀ , t ₈ ,.
W / 4 is output.

The DSP 8 outputs a latch signal at the same time as outputting the pulse width data ΔW / 4 to the pulse width control unit 12, so that the pulse width data ΔW / 4 is latched, and at the same time, the above-mentioned latch signal is transmitted via the OR gate 27 to each of the timers 15 of the pulse width control unit 12 and the frequency control unit 13.
18, this is used as a trigger for both timers 15,
18 starts timing at the same time (for example, the time shown in FIG. 2).
t ₀ ).

Further, in the PWM signal output unit 20,
Assuming that the upper flip-flop 21 has been selected by the selector 24 in advance, the upper flip-flop 21 is set by the latch signal, and the output Q of the upper flip-flop 21 becomes high level.

The output Q of the flip-flop 21
Becomes high level, the flip-flop 23
Is reset, the selector 24 switches to select the flip-flop 22 on the lower side.

The pulse width data ΔW / 4 latched by the latch circuit 14 of the pulse width control unit 12 is compared with the time measured by the timer 15 by the comparator 16. Is reset (for example, at time t _{1 in} FIG. 2). Therefore, the flip-flop 21 outputs a PWM signal having an ON time corresponding to the pulse width data ΔW / 4 given from the DSP 8 to the switching elements Q1 and Q4 of the high-frequency inverter 1.

On the other hand, in the frequency control unit 13, the frequency data Δt / 4 latched by the latch circuit 17 and the time measured by the timer 18 are compared by the comparator 19, and if the two values match, the comparator 19 Outputs a match signal.

Here, since .DELTA.W <.DELTA.t, the comparator 19 outputs a coincidence signal after the comparator 16 of the pulse width controller 12 outputs a coincidence signal (for example, FIG. 2). time t _2).

The coincidence signal from the comparator 19 is
Since the timers 15 and 18 of the pulse width control unit 12 and the frequency control unit 13 are added via the OR gate 27, both the timers 15 and 18 are cleared at the same time, and the timer starts again. Further, the coincidence signal is output to the PWM signal output unit 20.
Is applied to the other flip-flop 22 via the selector 24 of FIG. 2, the flip-flop 22 is set, and the output Q thereof becomes high level (time t _{2 in} FIG. ₂ ).

When the time measured by the timer 15 of the pulse width control unit 12 after the flip-flop 22 is set coincides with the pulse width data ΔW / 4 latched in the latch circuit 14, the comparator 16 Output a match signal from the flip-flop 22.
Is reset (for example, time t _{3 in} FIG. 2).

Therefore, from this flip-flop 22, a PWM signal having an ON time corresponding to the pulse width data ΔW / 4 given from DSP 8 is output to switching elements Q2 and Q3 of high frequency inverter 1.

When the period of Δt / 4 has elapsed, the comparator 19 of the frequency control unit 13 outputs a coincidence signal again, the two timers 15 and 18 are cleared at the same time, and time measurement is started again (FIG. 2). time t ₄ of).

The above operation is repeated until the next latch signal of the pulse width data ΔW / 4 is input from the DSP _{8 (} until time t _{8 in} FIG. 2).

As described above, the pulse width data output from the DSP 8 is 1/1 of the pulse width calculation result of the conventional PWM signal.
It is N times (here, 1/4 times), and therefore, the carrier frequency of the PWM signal within each fixed period At is N times (here, 4 times) the conventional frequency.

When the carrier frequency, which is the basis of the PWM signal, changes and the period is extended (when the period is longer than the period Δt in FIG. 3 by α), the DSP 8 sends the pulse width to the pulse width controller 12. The timing of the latch signal output therefrom is also changed from time ta to time tb in FIG. At this time, after outputting the PWM signal N times (here, four times),
Until the next latch signal is output from the DSP 8, the switching elements Q1 to Q4
Are all in the off state, and the PWM for more than the set number of times
It is necessary to prevent signals from being output. For this purpose, in this embodiment, an operation interruption means 30 is provided.

Next, the operation of the operation suspending means 30 will be described in more detail.

As described above, the DSP 8 outputs the pulse output frequency data N to the latch circuit 31 of the operation suspending means 30.
= 4 is latched in advance.

When a latch signal of pulse width data is output from the DSP 8 to the pulse width control unit 12,
(For example, t ₀ , t ₈ ,... In FIG. 2)
4 is set and the AND gates 25 and 26 are opened.

Each time a coincidence signal is output from the comparator 16 of the pulse width control unit 12, the counter 32
Sequentially counts the coincidence signals, and the count value is supplied to the comparator 33. The comparator 33 calculates the pulse output count data N of the latch circuit 31 and the counter 32
And outputs a match signal when they match (in this example, when N = 4). Since the flip-flop 34 is reset by the coincidence signal, the AND gates 25 and 26 are closed.

Therefore, four PWMs within the period Δt
After the signal is output, the DSP 8 outputs the pulse width control unit 1
Until the next pulse width data latch signal is output to the switching element 2, the switching elements Q1 to Q4 of the high-frequency inverter 1 are all in the off state and are on standby.

As shown in FIG. 4, when the carrier frequency at which the DSP 8 outputs pulse width data changes, the period becomes shorter (when the period becomes longer than the period Δt in FIG. 4 by β). In FIG. 4, the timing of the latch signal output from the DSP 8 to the pulse width control
The time is changed from ta to time tc. At this time, even if the PWM signal is not output N times (here, four times), the DSP 8
Is restarted by outputting the updated pulse width data and the latch signal from, and is immediately reflected in the PWM control.

As described above, according to this embodiment, even if the pulse width calculation of the PWM signal based on the software is relatively slow, by dividing the pulse width data from the calculation result of the PWM signal, the carrier of the PWM signal can be obtained. Each switching element can be controlled at a high frequency obtained by multiplying the frequency by N, and the power supply device can be downsized.

In this embodiment, the case where N = 4 is set as the pulse output count data is described. However, the present invention is not limited to this. If N is an integer of 2 or more, the operation of the DSP 8 is simplified, but it may be a positive real number.

Further, in this embodiment, a case has been described in which the present invention is applied to a power supply apparatus of a high-frequency transformer insulation type for system interconnection, but the present invention is not limited to this. The present invention is also applicable to a power supply device such as a DC converter.

[0075]

According to the present invention, the following effects can be obtained.

(1) According to the first aspect of the present invention, the pulse width calculation of the PWM signal based on the software is relatively slow only by slightly changing the software and adding hardware to the conventional circuit configuration. In addition, the pulse width data is divided from the operation result of the PWM signal, and each switching element can be controlled at a high frequency obtained by multiplying the carrier frequency of the PWM signal by N, so that the power supply device can be downsized. .

(2) According to the second aspect of the present invention, the frequency of the signal multiplied by the frequency conversion means is set to be an integral multiple of the basic carrier frequency of the PWM signal. It gets even easier.

(3) According to the third aspect of the invention, when the carrier frequency, which is the basis of the PWM signal, is changed and the cycle is extended, all the switching elements are kept in the OFF state, and only the required number of times are set. Since it does not perform switching operation,
Output fluctuations of the power supply device can be suppressed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a specific configuration of a control unit included in a power supply device for system interconnection according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining a pulse control operation in a control unit in FIG. 1;

FIG. 3 is a timing chart for explaining a control operation of an operation interrupting unit when a period is extended due to a change in a carrier frequency which is a basis of a PWM signal;

FIG. 4 is a timing chart for explaining a control operation of an operation interrupting unit when a period is shortened due to a change in a basic carrier frequency of a PWM signal;

FIG. 5 is a waveform diagram of a PWM control operation.

FIG. 6 is a configuration diagram showing the entire power supply device for system interconnection;

FIG. 7 is a block diagram showing a specific configuration of a conventional control unit provided in the power supply device of FIG. 6;

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... High frequency inverter, 2 ... Transformer, 3 ... Full-wave rectifier circuit, 4 ... DC filter, 5 ... Low frequency inverter, 6 ... A
C filter, 7 control unit, 8 DSP, 9 pulse generation circuit, 10 microcomputer, 11 AD converter, 12 ...
Pulse width control unit, 13: frequency control unit, 20: PWM signal output unit, 30: operation interruption means.

Claims (3)

[Claims] 1. A power supply for performing a pulse width calculation for each period corresponding to a carrier frequency of a PWM signal, generating a PWM signal having a pulse width based on the calculation result, and turning on / off a switching element by the PWM signal. In the apparatus, the PWM signal obtained by the pulse width calculation is converted to the 1
A power supply device comprising frequency conversion means for multiplying a plurality of pulses in each cycle and outputting the multiplied PWM signal to each of the switching elements. 2. The power supply device according to claim 1, wherein the frequency of the signal multiplied by said frequency conversion means is PW
A power supply device set to be an integral multiple of a carrier frequency of an M signal. 3. The power supply device according to claim 1, wherein the carrier frequency of the PWM signal changes during the output period of the multiplied signal and the period of the multiplied signal is extended. A power supply device comprising: an operation interrupting unit that turns off all of the switching elements during a period from when the output is performed until a result of calculating the pulse width of the next PWM signal is obtained.