JPH11308282A - Jitter correction circuit for field path transmission signal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To recover jitter characteristics for a deteriorated transmission signal and to enable signal transmission for a long distance by obtaining a jitter from a difference between a time between level change point detection pulses for an input transmission signal of a field path and its ideal value, correcting the jitter and outputting it. SOLUTION: An inputted transmission signal is sampled by a clock Fclk 1, a change point (the point where H becomes L or L becomes H) of a level of the sampled input signal is detected, and a pulse signal is inputted. Then, a time Tdc from the previous level change point detection pulse to a level change point detection pulse this time is obtained by counting the clock Fclk 1. A jitter is obtained from the Tdc (that is, the time when H or L continues) and a standard of the transmission signal and a delay time for correcting it between input and output is obtained. Then, jitter correction is performed by delaying the sampled input signal by using a clock Fclk 2 only for the delay time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for correcting jitter of a fieldbus transmission signal.

[0002]

2. Description of the Related Art Conventionally, there is a start-stop synchronization method as a general digital transmission signal jitter correction method. In this method, jitter is absorbed by sampling a transmission signal using a reference clock signal Fclk having the same frequency as the bit frequency of the transmission signal or a frequency having a fixed ratio. 4 and 5 show an example of the start-stop synchronization method and a time chart.

[0003]

By the way, the standard of the field bus (H1) is defined as follows. (1) Transmission rate: 31.25 kbit / s ± 0.2% (by Manchester code) (2) Maximum frame length: 276 bytes (3) Maximum reception jitter: ± 14.0% nominal bit time (4) Maximum transmission jitter : ± 2.0% nominal bit time (5) Delay time: less than 2 nominal bit time

Therefore, the above-mentioned start-stop synchronization method cannot be used in the field bus. Because the transmission signal is a Manchester code, a clock having a frequency twice as high as the input transmission rate is used to sample the transmission signal. That is, although an internal clock having a frequency of 62.5 kHz is used, even if the frequency of the internal clock is accurate, an allowable error in the transmission rate of the input transmission signal is ± 0.2%.

Therefore, as shown on the left side of FIG.
Even if the phase of the clock is optimized at the start of the input transmission signal, the allowable error is accumulated with the lapse of time, and the phase relationship between the input transmission signal and the clock is shifted.
Finally, as shown on the right side of FIG. For example, in the case of data transmission of the maximum frame length, when the time lag between the transmission signal and the clock is the maximum allowable error ± 0.2%, 276 × 8 × (± 0.2 / 100) =
This results in ± 4 bit jitter. Therefore, an object of the present invention is to provide a jitter correction circuit that complies with the standard of the field bus (H1).

[0006]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, a first aspect of the present invention provides a clock circuit for generating a first clock signal used for sampling an input signal, and a circuit for correcting the input signal. Circuit for generating a second clock signal to be used when outputting the data, a sampling circuit for sampling the transmission signal of the field bus with the first clock signal, and a detection circuit for detecting a level change point of the sampled transmission signal And the interval between the detected level change point and the next detected level change point is the first
Measuring means for measuring using the number of pulses of the clock signal, calculating means for comparing the measured level change point interval with the transmission signal standard to calculate the jitter at the level change point, and measuring the jitter from the obtained jitter value. Calculating means for calculating the delay amount of the output signal for correcting the delay time, and an output circuit for delaying the transmission signal sampled using the obtained delay amount by the delay amount based on the second clock signal and outputting the delayed transmission signal. It is characterized by having.

That is, in the present invention, an input transmission signal is first sampled by a clock Fclk1 (for example, 1 MHz). The level change point (H) of the sampled input signal
→ L or L → H) and outputs a pulse signal. The time (Tdc) from the previous level change point detection pulse to the current level change point detection pulse is represented by clock Fclk1.
Is determined by counting. Jitter (Tjit) is obtained from Tdc (that is, the time during which H or L continues) and the standard of the transmission signal, and a delay time between input and output (Tdly) for correcting the jitter is obtained. The sampled input signal is clocked by the clock Fclk2 for the delay time (Tdly).
(For example, 4 MHz), the jitter is corrected by outputting the delay.

According to a second aspect of the present invention, in the first aspect, the measured level change point interval is compared with a time corresponding to 1 bit or 1/2 bit of the transmission signal, and the difference is compared with the jitter of the level change point. Calculation means for calculating the delay amount, and calculating means for subtracting the obtained jitter value from the previously calculated delay amount to obtain the value as the current delay amount. The obtained delay amount is within a preset delay time range. And a correcting means for determining whether or not the delay is outside the range, and correcting the increase or decrease of the delay amount in units of the pulse width of the second clock signal when out of the range.

That is, in the present invention, the transmission signal of the field bus (H1) standard is assumed, and the time (Tdc) between the level change point detection pulses and its ideal value (32 bits corresponding to 1 bit) are assumed.
The jitter (Tjit) is obtained from the difference from the value of μs or 16 μs corresponding to 1/2 bit). The delay time between input and output (Tdly) for jitter correction is changed to a value obtained by subtracting the jitter from the previous delay time (Tdly) value. Here the jitter (Tji
In the polarity of t), the leading direction is considered as-and the lagging direction is considered as +. Therefore, the delay time (Tdly) increases in the leading direction of the jitter and decreases in the delaying direction of the jitter.

However, if the delay time (Tdly) is out of the predetermined delay time range (for example, 10 μs to 20 μs), the time is further increased or decreased by one cycle of the clock Fclk2 (for example, 4 MHz). For example, when Tdly <10 μs, 0.25 μs is added to the delay time (Tdly). Tdl
When y> 20 μs, the delay time (Tdly) is reduced to 0.25 μs.
Subtract s. This is the input transmission rate tolerance (±
0.2%) to limit the variable range of the delay time (Tdly). Field bus (H1)
Jitter correction of a transmission signal conforming to the standard becomes possible.

According to a third aspect of the present invention, in the first or the second aspect of the present invention, the transmission signal sampled by the sampling circuit is continuously at the H or L level for a preset number of times or more from the level change point. And a filter circuit for transmitting the signal change to the next stage in the case where the signal is changed. That is, according to the present invention, even if there is noise (short-time pulse) in the input signal, erroneous sampling of the noise can be prevented by the sampling means having the filter function.

According to a fourth aspect of the present invention, in the first or second or third aspect of the present invention, a pair of signal line connection terminals connected in the middle of the signal line through which the field bus transmission signal is transmitted; A pair of circuit connection terminals connected to an input terminal and an output terminal of the jitter correction circuit; and a switching circuit that connects between the pair of signal line connection terminals and the pair of circuit connection terminals so as to be alternately switchable. A direction detection circuit for detecting a transmission direction of a signal in the signal line, and operating the switching circuit each time the direction detection circuit detects a reversal of the signal transmission direction, so that the signal is always transmitted in the signal line. Switching circuit driving means for inputting a signal from an input terminal of the jitter correction circuit and transmitting the signal from an output terminal to a signal line. That is, in the present invention, the addition of the signal switching means enables the jitter correction for the half-duplex bidirectional transmission signal.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows the configuration of the embodiment of the present invention.
FIG. 2 shows a time chart of each part corresponding to this. The input signal sampling unit 1 samples the input transmission signal with a clock Fclk1 (1 MHz) output from a cook generation circuit (not shown). The level change point detector 2 detects the level change point (H → L) of the sampled input signal.
Or a point at which L → H is detected) and a pulse signal is output.

The inter-level change point time measuring section 3 obtains the time (Tdc) from the previous level change point detection pulse to the current level change point detection pulse by counting the clock Fclk1. The jitter calculation / input / output delay amount calculation unit 4 calculates the jitter (Tjit) from the time Tdc (time during which H or L continues) and the standard of the transmission signal, and calculates a delay time between input and output to correct the jitter (Tjit). Tdly).
The initial delay time at the start of the input signal is 15 μs, and the delay time is updated each time jitter is detected. Variable delay unit 5
Then, the sampled input signal is delayed by the delay time (Tdly) obtained as described above using a clock Fclk2 (4 MHz) output from a cook generation circuit (not shown) and output.

Next, a specific operation example in the case where a transmission signal of the field bus (H1) standard is assumed will be described. The jitter calculation / input / output delay amount calculation unit 4 calculates the jitter (Tjit) from the difference between the time (Tdc) between the level change point detection pulses and its ideal value. This ideal value is always 32 μs (1b
Since it is either 16 μs (corresponding to bit bit) or 16 μs (corresponding to bit bit), the jitter (Tjit) is obtained by comparing with it.

The delay time between input and output (Tdly) for jitter correction is changed to a value obtained by subtracting the jitter from the previous delay time (Tdly) value. Where jitter (Tjit)
Is assumed to be-in the leading direction and + in the lagging direction. Therefore, the delay time (Tdly) increases in the leading direction of the jitter and decreases in the delay direction. Also,
The maximum jitter of the input signal is ± 7 μs (± 2
1.8% nominal bit time), maximum error of transmission rate = ±
Considering 0.39%, the variable range of the delay time (Tdly) is 15 ± 10 μs, ie, 5 μ
s to 25 μs.

If the delay time (Tdly) is out of the predetermined delay time range (10 μs to 20 μs), the time is further increased or decreased by one cycle of the clock Fclk2 (4 MHz). That is, when Tdly <10 μs, 0.25 μs is added to the delay time (Tdly). Tdly> 20μs
In the case of (2), 0.25 μs is subtracted from the delay time (Tdly). As a result, even when the transmission rate of the input signal has the maximum allowable error (± 0.39%), the output transmission signal has a jitter of one cycle of the clock Fclk2 (jitter at Fclk2 = 4 MHz is 0.78% bit time). ), And the delay time between input and output falls within the range of 5 μs to 25 μs.

As described above, the jitter correction of the transmission signal conforming to the field bus (H1) standard becomes possible. The operation when the input signal sampling section 1 has a filter function is as follows. As a result of sampling with the clock Fclk1, when the signal is determined to be “H” or “L” continuously for a predetermined number of times, the result is output as a sampling signal. Thereby, even if there is noise (short-time pulse) in the input signal, it is possible to prevent the noise from being erroneously sampled.

FIG. 3 shows an embodiment of the invention according to claim 4 in which a signal switching section is added. Here, a signal switching unit 7 is connected in the middle of the signal line 6 through which the fieldbus transmission signal is transmitted, and the jitter correction circuit 8 shown in FIG. 1 is connected via the signal switching unit 7. 7 of signal switching unit 7
Reference numerals 1 and 72 are signal line connection terminals, 73 is a circuit connection terminal connected to the input terminal of the jitter correction circuit 8, and 74 is a circuit connection terminal connected to the output terminal of the jitter correction circuit 8.

The operation of the signal switching section 7 is as follows. As shown by the solid line in FIG. 3, when the input signal 1 is transmitted from the left to the right on the signal line 6, the connection terminal 71 and the connection terminal 73 are provided in the signal switching unit 7.
Are connected and the connection terminal 72 and the connection terminal 74 are connected, so that the input signal 1 is input to the jitter correction circuit 8 and the output signal of the jitter correction circuit 8 is transmitted to the signal line 6 as the output signal 1. Is done.

On the other hand, when the input signal 2 is transmitted from the right to the left on the signal line 6 as shown by the broken line, the connection terminals 71 and 74 are connected and the connection terminals 72 and By connecting the connection terminal 73,
The signal switching section 7 is switched so that the input signal 2 is input to the jitter correction circuit 8 and the output signal of the jitter correction circuit 8 is transmitted as the output signal 2 to the signal line 6. Although the signal transmission direction on the signal line 6 is not shown,
A signal transmission direction detection circuit provided in the signal switching section 7 detects the signal transmission direction, and the connection between the terminals is switched according to the direction. This makes it possible to perform jitter correction even on a half-duplex bidirectional transmission signal.

[0022]

As described above, according to the first and second aspects of the present invention, the jitter of the input transmission signal of the field bus is corrected and output, so that the jitter correction circuit of the present invention is transmitted. By inserting the transmission signal in the middle of the path, the jitter characteristic of the deteriorated transmission signal can be recovered. As a result, signal transmission over a longer distance can be performed as compared with the related art. According to the third aspect of the present invention, the jitter correction circuit is provided with a filter function, so that jitter can be corrected even when the input signal has noise (short-time pulse). Furthermore, according to the fourth aspect of the present invention, the signal switching unit is provided in the jitter correction circuit, so that the jitter can be corrected for the half-duplex bidirectional transmission signal.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a time chart showing the operation of each unit in FIG.

FIG. 3 is a diagram showing an embodiment of the invention of claim 4;

FIG. 4 is a diagram showing a conventional example.

FIG. 5 is a time chart showing the operation of the conventional example.

[Explanation of symbols]

 Reference Signs List 1 input signal sampling unit 2 level change point detection unit 3 level change point time measurement unit 4 jitter calculation / input / output delay amount calculation unit 5 variable delay unit 6 signal line 7 signal switching unit 8 jitter correction circuit 71, 72 signal line connection Terminal 73, 74 Circuit connection terminal

Claims (4)

[Claims] A clock circuit that generates a first clock signal used when sampling an input signal; a clock circuit that generates a second clock signal used when correcting and outputting an input signal; A sampling circuit for sampling the transmission signal of the above with a first clock signal, a detection circuit for detecting a level change point of the sampled transmission signal, and a level change point between the detected level change point and the next detected level change point Measuring means for measuring the interval using the number of pulses of the first clock signal; calculating means for comparing the measured level change point interval with the transmission signal standard to calculate the jitter at the level change point; Calculating means for calculating the amount of delay of the output signal for correcting the jitter from the value of, and transmitting the transmission signal sampled using the obtained amount of delay. Jitter correction circuit Fieldbus transmission signal, characterized in that it includes an output circuit by the delay amount based on the second clock signal is delayed outputs, a. 2. The jitter correction circuit for a field bus transmission signal according to claim 1, wherein the measured level change point interval is compared with a time corresponding to 1 bit or 1/2 bit of the transmission signal, and the difference is compared with the level change. Calculating means for calculating the point jitter; calculating means for subtracting the obtained jitter value from the previously calculated delay amount to obtain the value as the current delay amount; and delaying the obtained delay amount in advance. Correction means for determining whether or not the time is within a time range, and when the time is out of the time range, correcting means for increasing or decreasing the delay amount in units of a pulse width of the second clock signal. Jitter correction circuit. 3. The jitter correction circuit for a fieldbus transmission signal according to claim 1, wherein the transmission signal sampled by the sampling circuit is continuously H or L at least a preset number of times from a level change point. A jitter correction circuit for a fieldbus transmission signal, comprising: a filter circuit for sending a signal change to a next stage when the level is a level. 4. The method according to claim 1, 2 or 3.
In the above described jitter correction circuit for a fieldbus transmission signal, a pair of signal line connection terminals connected in the middle of a signal line through which the fieldbus transmission signal is transmitted; and an input terminal and an output terminal of the jitter correction circuit. A pair of circuit connection terminals, a switching circuit that connects between the pair of signal line connection terminals and the pair of circuit connection terminals so as to be alternately switchable, and detects a transmission direction of a signal in the signal line. A direction detection circuit, and each time the direction detection circuit detects the reversal of the signal transmission direction, the switching circuit is operated, and a signal transmitted through the signal line is always input from the input end of the jitter correction circuit and output. A switching circuit driving means for transmitting the signal from the end into the signal line; and a jitter correction circuit for a fieldbus transmission signal.