JP2011077751A - Data processing apparatus, and data processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce error of a timing from signal reception to signal transmission. <P>SOLUTION: In a data processing system where a plurality of data processing nodes are connected to a communication channel in a given topology, the data processing apparatus at a data processing node has a communication function of reproducing a received clock signal based on a received signal, reproducing the received data from the received signal in a received data reproduction unit (122) in synchronism with the received clock signal thus reproduced, generating the transmission data for the received data thus reproduced in a transmission data generation unit (123), and generating a transmission signal from the transmission data in a transmission unit (125) and then transmitting the transmission signal to the communication channel in synchronism with a transmission clock signal. Furthermore, the data processing node has a detection unit (124) which detects the error time when the processing time is short for the permitted time until the transmission signal is transmitted from the transmission unit after a signal is received at the received data reproduction unit. The transmission unit starts transmission of the transmission data after an elapse of the error time detected in the detection unit. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a data processing apparatus and a data processing system.

  Ethernet CAT (Ethernet for Control Automation) is a standard for controlling systems by communicating control data with high-precision timing using the physical layer and data link layer standards of IEEE 802.3, commonly called Ethernet (registered trademark). Technology) standards.

  For example, 100BASE-TX, which is one communication standard of Ethernet (registered trademark), divides the physical layer function as PHY (Physical Layer Entities) and the data link layer function as MAC (Media Access Control), and divides the connection into MII (Media Access Control). Media Independent Interface).

  The 100BASE-TX PHY uses the 25 MHz transmission clock signal sent from the MAC via the MII, the transmission frame data sent sequentially every 4 bits in synchronization with the clock, and its valid signal. A 125 MHz transmission clock signal obtained by multiplying the 25 MHz transmission clock signal by 5 is generated, and a 5 bit code signal is sequentially generated by 4B / 5B (4 Bit / 5 Bit) pattern conversion, and the generated code signal 5 is generated. Bits are serialized serially and sequentially applied to the transmission path of the communication medium at 125 MHz for each bit.

  In addition, a 125 MHz reception clock signal used for transmission by the data link partner is recovered from a signal received from the reception path of the communication medium applied by the data link partner, and the 125 MHz reception recovery clock signal is divided by a factor of five. Generates a rounded 25 MHz reception clock signal, and successively reproduces a reproduction signal at 125 MHz for each bit from the received signal, serially deserializes the reproduction signal to sequentially generate a 5-bit code signal, and a 4B / 5B pattern 4 bits of received frame data is sequentially generated for every 5 bits of the code signal by inverse conversion, and a 25 MHz reception clock signal is generated in MAC via MII, and reception frame data and its valid signal are sequentially generated every 4 bits in synchronization with the clock. Are sent sequentially.

  The MAC or higher part of the communication processing device generates a 25 MHz clock signal different from the 25 MHz reception clock signal sent from the PHY, and sends it to the PHY via the MII as a 25 MHz transmission clock signal. Also, the received frame data 4 bits sequentially transmitted from the PHY via the MII and its valid signal are replaced with the 25 MHz transmission clock signal or another clock signal in the apparatus for processing.

  Such a system compatible with the Ethernet CAT standard using Ethernet (registered trademark) connects devices in a bus type, tree type or star type network topology. One of the devices in the system first transmits control data as a master. Then, another device as a slave extracts data from the control data, adds it, corrects it, and transfers it cyclically between the devices. Finally, the master receives the control data.

  In order to realize a real-time and high-precision control system, each device is required to perform the above-described processing at high speed and with low jitter. For example, in the EtherCAT standard, the jitter between two devices is defined as an absolute value within 40 nanoseconds (range within ± 20 nanoseconds).

IEEE Computer Society "IEEE Std 802.3 (TM) -2008", Carrier sense multiple access with Collision Detection (CSMA / CD) Access Method and Physics 28 http: // www. ethercat. org / en / technology.html "EtherCAT-Technical Induction and Overview" (as of June 23, 2009)

  In order to realize a more accurate control system in an industrial network using communication based on the EtherCAT standard, each communication processing device needs to perform communication processing with low jitter. In short, it is necessary to be able to transmit a cyclically transferred signal with low jitter, that is, with a small timing error. The timing error includes a phase difference between a 125 MHz clock signal reproduced from the received signal and a 125 MHz clock signal to be transmitted, an error in the reproduction start timing of the received data with respect to the reproduced 25 MHz received clock signal, and a 25 MHz transmission clock. This is due to an error in transmission data generation start timing with respect to the signal.

  Further, in order to expand the number of devices connected to the system, each device is required to perform processing at higher speed and with lower jitter. Otherwise, even if the number of devices connected to the system is expanded, the control system as a whole cannot guarantee certain real-time performance and accuracy. For example, in an apparatus using 100BASE-TX, the jitter becomes a maximum of 40 nanoseconds by switching the frame data between the 25 MHz reception clock signal and the 25 MHz transmission clock signal, and the signal is cyclically transferred and returned to the master apparatus. In some cases, jitter of individual devices is accumulated, and there is a possibility that real-time performance and accuracy cannot be guaranteed in a large system.

  An object of the present invention is to provide a data processing apparatus including a communication processing circuit that can reduce a timing error from signal reception to signal transmission.

  Another object of the present invention is to reduce the accumulation of jitter in a data processing system that circulates a plurality of data processing nodes and transfers signals, and to guarantee real-time performance and accuracy of the data processing system.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  That is, in a data processing system in which a plurality of data processing nodes are connected to a communication path with a predetermined topology, the data processing device of the data processing node regenerates the received clock signal based on the received signal, and the regenerated received clock signal In synchronization with the received data, the received data reproducing unit reproduces the received data from the received signal, the transmission data for the reproduced received data is generated by the transmission data generating unit, the transmitting unit generates the transmission signal from the transmitted data, and the transmission clock A communication function is provided for transmitting to a communication path in synchronization with a signal. The data processing node further includes a detection unit that detects an error time when the processing time is short with respect to a time allowed from reception of the signal by the reception data reproduction unit to transmission of the transmission signal by the transmission unit. . The transmission unit waits for the error time by the detection unit to start transmission of transmission data.

  Thus, theoretically, the jitter at the communication node is suppressed to the phase difference between the reception clock signal and the transmission clock signal.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, the accumulation of jitter in the data processing system can be reduced, and the real-time property and accuracy of the data processing system can be improved.

FIG. 1 is a block diagram illustrating an example of a data processing apparatus. FIG. 2 is a timing chart illustrating the timing of transfer processing when the processing necessary for transfer can be completed in the best time by the communication processing circuit. FIG. 3 is a timing chart illustrating the timing of the transfer process when the process necessary for transfer is completed in the worst time by the communication processing circuit. FIG. 4 is a flowchart showing the procedure of the communication processing operation performed by the communication processing circuit. FIG. 5 is a block diagram illustrating a data processing system using the data processing apparatus of FIG.

1. First, an outline of a typical embodiment will be described. Reference numerals in the drawings referred to in parentheses in the outline description of the representative embodiments merely exemplify what are included in the concept of the components to which the reference numerals are attached.

  [1] A data processing device (101) according to a typical embodiment includes a communication processing circuit (120) and a data processing circuit (110). The communication processing circuit includes a clock recovery unit (121) that recovers a reception clock signal (CKR) from a reception signal, and reception data (SIGR) that is received from a reception signal (SIGR) in synchronization with the reception clock signal that is recovered by the clock recovery unit. DATR) is generated by a reception data reproduction unit (122), a transmission data generation unit (123) that generates transmission data (DATT) for the reception data reproduced by the reception data reproduction unit, and a transmission data generation unit. A transmission unit (125) that generates a transmission signal (SIGT) from the transmitted data and transmits the signal to the outside in synchronization with the transmission clock signal (CKT), and a transmission signal from the reception of the signal by the reception data reproduction unit And a detection unit (124) for detecting an error time when the processing time is short with respect to the time allowed until the transmission of. The transmission unit starts transmission of a transmission signal after an error time has elapsed by the detection unit.

  Thus, theoretically, the jitter at the communication node is suppressed to the phase difference between the reception clock signal and the transmission clock signal. Therefore, each data processing apparatus can reduce the timing error from signal reception to signal transmission.

  Here, “when the processing time is shorter than the time allowed from the reception of the signal by the reception data reproducing unit to the transmission of the transmission signal by the transmission unit” is specifically as follows. That is, with respect to the processing time allowed from the reception of the signal by the reception data reproducing unit to the transmission of the transmission signal by the transmitting unit (that is, the worst processing time), the transmission signal from the reception of the signal by the reception data reproducing unit When the processing time actually spent (estimated) before the transmission of is short.

  The processing time that is actually spent (estimated) may be different for each frame data received from the received data reproducing unit. Therefore, the worst processing time is defined in advance and this information is stored in a storage unit, etc., and the estimated processing time that will be actually spent for each frame data received from the received data reproduction unit is estimated. Is shorter than the worst processing time, it waits for the error time (= worst processing time-estimated processing time) to transmit.

  [2] In the data processing device according to item 1, for example, the clock recovery unit generates a divided clock signal (CKRd) having a frequency of 1 / n with respect to the received clock signal together with the received clock signal (CKR). To do. The received data reproduction unit reproduces a bit unit signal in synchronization with the reproduced reception clock signal, and decodes the reproduced bit signal in a plurality of bit units in synchronization with the divided clock signal. To play the received data. The transmission data generation unit generates transmission data in synchronization with an internal clock signal (CKTd) having the same frequency as that of the divided clock signal. The transmission unit encodes the transmission data and generates the transmission signal that is bit-synchronized with a transmission clock signal obtained by multiplying the frequency of the internal clock signal (CKT) by n.

  [3] In the data processing device according to item 2, for example, the detection unit is a target based on the number of clock cycles of the received clock signal from when the received data reproducing unit receives the received signal until the valid received data is reproduced. A first error cycle number (ERN1) with respect to the cycle number is detected, and a second error cycle number (ERN2) of the phase delay of the internal clock signal with respect to the divided clock signal with reference to the clock cycle of the received clock signal And the time corresponding to the sum of the first error cycle number and the second error cycle number is defined as the error time.

  [4] In the data processing apparatus according to item 3, the reception data generation unit supplies the reproduction data to the transmission data generation unit and, if necessary, to the data processing circuit. The transmission data generation unit generates transmission data by performing data extraction, data addition, or data correction on the reproduction data in accordance with an instruction from the data processing circuit.

  [5] In the data processing device according to item 4, for example, the data processing circuit includes a central processing unit (111) for executing an instruction, a memory (112) accessed by the central processing unit, and a peripheral circuit controlled by the central processing unit. (113) and a clock pulse generator (115) for generating the internal clock signal. The central processing unit operates in synchronization with the internal clock signal.

  [6] A data processing system according to a typical embodiment is a data processing system in which a plurality of data processing nodes (401, 411 to 416, 421, 422) are connected to a communication path with a predetermined topology, Each of the plurality of data processing nodes includes a data processing device. The data processing apparatus includes a communication processing circuit connected to the communication path and a data processing circuit connected to the communication circuit. The communication processing circuit regenerates a received clock signal based on a received signal received from a communication path, and regenerates received data from the received signal in synchronization with the received clock signal regenerated by the clock regenerating unit. A reception data reproduction unit, a transmission data generation unit for generating transmission data for the reception data reproduced by the reception data reproduction unit, and a transmission clock signal by generating a transmission signal from the transmission data generated by the transmission data generation unit And a transmission unit that transmits to the communication path in synchronization with each other. And a detector that detects an error time when the processing time is short relative to a time allowed from reception of the signal by the reception data reproduction unit to transmission of the transmission signal by the transmitter. Waits for the elapse of the error time by the detection unit and starts transmitting the transmission signal.

  Thus, theoretically, the jitter at the communication node is suppressed to the phase difference between the reception clock signal and the transmission clock signal. Therefore, each data processing apparatus can reduce the timing error from signal reception to signal transmission. Therefore, it is possible to reduce the accumulation of jitter in a data processing system that circulates a plurality of data processing nodes and transfers signals, and to guarantee the real-time property and accuracy of the data processing system.

  [7] In the data processing system according to item 6, for example, the plurality of data processing nodes include a master device (401), relay devices (421, 422), and slave devices (411 to 416) arranged at a base point of a communication path. The output from the master device is cyclically transferred to the relay device and the slave device and returned to the master device.

  As a result, in a data processing system that performs communication so that a signal from the master device circulates through a plurality of relay devices and slave devices and returns to the master device, accumulation of jitter that occurs during the circulation can be reduced. Real-time performance and accuracy can be guaranteed.

  [8] In the data processing system according to item 7, for example, the allowable time is set equally among all the data processing apparatuses.

  [9] In the data processing system according to item 8, for example, the clock recovery unit recovers the reception clock signal and generates a divided clock signal having a frequency of 1 / n with respect to the reception clock signal. The received data reproduction unit reproduces a bit unit signal in synchronization with the reproduced reception clock signal, and decodes and receives the bit signal reproduced in synchronization with the generated divided clock signal. Play the data. The transmission data generation unit generates transmission data in synchronization with an internal clock signal having the same frequency as that of the divided clock signal. The transmission unit encodes the transmission data and generates the transmission signal that is bit-synchronized with a transmission clock signal obtained by multiplying the frequency of the internal clock signal by n.

  [10] In the data processing system according to item 9, the detection unit has a target cycle based on the number of clock cycles of the received clock signal from when the received data reproducing unit receives the received signal until the valid received data is reproduced. And detecting a second error cycle number of a phase lag of the internal clock signal with respect to the divided clock signal with reference to a clock cycle of the received clock signal. The time corresponding to the sum of the number of error cycles and the second number of error cycles is defined as the error time.

  [11] In the data processing system according to item 10, the reception data generation unit supplies reproduction data to the transmission data generation unit and, if necessary, to the data processing circuit. The transmission data generation unit generates transmission data by performing data extraction, data addition, or data correction on the reproduction data in accordance with an instruction from the data processing circuit.

  [12] In the data processing system according to item 11, the data processing circuit includes a central processing unit that executes instructions, a memory that is accessed by the central processing unit, a peripheral circuit that is controlled by the central processing unit, and the internal clock signal. It has a clock pulse generator to generate. The central processing unit operates in synchronization with the internal clock signal.

2. Details of Embodiment FIG. 1 shows an example of a data processing apparatus. The data processing apparatus exemplified in the figure is not particularly limited, but is a microcomputer which is formed on a single semiconductor substrate such as single crystal silicon by a complementary MOS integrated circuit manufacturing technique and a required system can be on-chip. Configured as The data processing apparatus 101 shown in the figure is roughly divided into a data processing circuit 110 and a communication processing circuit 120 that receives the control.

  The data processing circuit 110 is, for example, a central processing unit (CPU) 111 that fetches an instruction and executes a program, and a memory 112 that is accessed by a CPU 111 or the like and used as a temporary storage area for data or a storage area for a program executed by the CPU 111. , A peripheral circuit 113 under the control of the CPU 111, a clock pulse generator (CPG) 115 for generating a synchronous clock signal, and the like, which share an internal bus 114 and are interfaced. The CPG 115 receives a system clock signal CKS used for an operation reference clock signal of the CPU 111, an internal clock signal CKTd used for data processing of the communication processing circuit 120, a transmission clock signal CKT used for transmission operation of the communication processing circuit 120, and the like. Generate.

  The communication processing circuit 120 is not particularly limited, but is a circuit that conforms to 100BASE-TX and can be interconnected with an external device conforming to 100BASE-TX. In the actual communication standard, there are control code signals such as a preamble and a delimiter before and after the communication frame signal. However, since this is not the essence of the description of the present invention, the description thereof is omitted in this specification together with the drawings. In addition, although some processing delay occurs depending on the implementation of data exchange between asynchronous clocks, this is not the essence of the description of the present invention, and the description thereof is also omitted.

  The communication processing circuit 120 includes a reception clock recovery unit 121, a reception data recovery unit 122, a transmission data generation unit 123, a phase difference information detection unit 124, and a phase difference adjustment transmission unit 125.

  The communication processing circuit 120 is converted into a 5-bit code signal for every 4 bits of transmission frame data by 4B / 5B (4 Bit / 5 Bit) pattern conversion, serialized serially, and supplied to the transmission path of the network 102 at 125 MHz for each bit. The signal is received as a reception signal SIGR.

  The reception clock reproduction unit 121 reproduces the reception clock signal CKR included in the reception signal SIGR received from the outside, and generates a divided clock signal CKRd having a frequency of 1 / n, for example, 1/5 with respect to the reception clock signal CKR. Generate. The reception clock signal CKR is set to 125 MHz, and the divided clock signal CKRd is set to 25 MHz.

  The reception data reproducing unit 122 reproduces a bit-unit signal in synchronization with the reception clock signal CKR with respect to the reception signal SIGR, and outputs the bit signal reproduced in synchronization with the divided clock signal CKRd to four bits. Received data is reproduced by decoding into bits (4 bit / 5 bit pattern inverse transform).

  The reproduced reception data DATR is supplied to the internal bus 114 as necessary, is processed by the CPU 111, and is passed to the transmission data generation unit 123 at the subsequent stage. The transmission data generating unit 123 generates transmission data DATT for the reception data DATR in synchronization with the internal clock signal CKTd having the same frequency as the frequency-divided clock signal CKRd. That is, the transmission data generation unit 123 generates transmission data DATT by performing data extraction, data addition, or data correction on the reception data DATR in accordance with instructions from the CPU 111. The CPU 111 may perform part of the generation of data to be added and the generation of correction data. Alternatively, the transmission data generation unit 123 may generate the transmission data DATT by extracting data, adding data, or modifying the data to the reception data DATR without receiving an instruction from the CPU 111. The data DATR may be used as transmission data DATT as it is.

  The phase difference adjustment transmission unit 125 receives the transmission data DATT generated by the transmission data generation unit and the transmission data valid signal ENDT, generates a transmission signal SIGT by performing 4Bit / 5Bit pattern conversion, and transmits this to the transmission clock signal CKT. In synchronization with the network 102.

  When the processing time is short relative to the time allowed from the reception of the reception signal SIGR by the reception data recovery unit 122 to the transmission of the transmission signal SIGT by the phase adjustment transmission unit, the phase difference information detection unit 124 has its error time Is detected. The phase difference information detection unit 124 supplies the phase difference information PHD corresponding to the error time to the phase difference adjustment transmission unit 125. The phase difference adjustment transmitting unit 125 waits for the error time by the phase difference information detecting unit 124, that is, waits for the phase difference dummy cycle in which the transmission data is given by the phase difference information to transmit the transmission signal SIGT. Start. In short, even if the processing is completed early with respect to the allowable time, the timing from signal reception to signal transmission can be made uniform by waiting for the expiration of the allowable time.

  The processing time is, for example, a reception data reproduction processing time for obtaining reception data by reverse conversion of 4Bit / 5Bit pattern in the reception data reproduction unit between signal reception and signal transmission, and transmission data generation in the transmission data generation unit 123. Processing time and processing time for obtaining a transmission signal by 4Bit / 5Bit pattern conversion of transmission data DATT in the phase adjustment transmission unit 125. The phase difference information detection unit 124 receives the reception data valid signal ENRD indicating the validity of the reception data from the reception data reproduction unit 122 and receives the clock signals CKR, CKRd, and CKTd in order to grasp the error time. . By using this, the phase difference information detection unit 124 receives the reception signal from the reception data reproduction unit 122 until the reception data valid signal ENRD is activated (until reproduction of valid reception data is started). A) detecting a first error cycle number (ERN1 in FIGS. 2 and 3) with respect to a target cycle number (DES = 9 cycles in FIGS. 2 and 3) based on the clock cycle number of the reception clock signal CKR; A second error cycle number (ERN2 in FIGS. 2 and 3) of the phase delay of the internal clock signal CKTd with respect to the divided clock signal CKRd is detected with reference to the clock cycle of the received clock signal CKR, and the first The time corresponding to the sum of the number of error cycles and the second number of error cycles (ERN1 + ERN2 in FIGS. 2 and 3) is an error. It is between.

  Hereinafter, the detection of the phase difference and the control of the transmission timing using the detected phase difference will be described in more detail using a specific example with reference to FIG. 2 and FIG.

  FIG. 2 illustrates a timing chart of transfer processing by the communication processing circuit. In FIG. 2, the hatched portions of the reception signal SIGR, reception reproduction data DATR, transmission data (transfer data) DATT, and transmission signal SIGT indicate that they are effective as transmission or reception frames. A hatched portion of the phase difference information PHD indicates that the value is valid.

  The reception clock recovery unit 121 and the reception data recovery unit 122 sequentially receive transmission frame data applied by a data link partner (not shown) in the network 102 as a reception signal SIGR. The reception signal SIGR is a 1-bit signal in a 125 MHz cycle in which a 125 MHz clock signal is convoluted.

  The reception clock recovery unit 121 recovers the 125 MHz reception clock signal CKR used for transmission by the data link partner from the reception signal SIGR. Further, a 25 MHz frequency-divided clock signal CKRd is generated by dividing the clock signal by 1/5.

  The reception data reproduction unit 122 sequentially reproduces the reproduction signal for each bit from the reception signal SIGR in accordance with the 125 MHz reception clock CKR, and sequentially deserializes the reproduction signal in accordance with the 25 MHz reception clock signal (divided clock signal) CKRd to generate a 5-bit signal. The code signal is sequentially generated, and 4 bits of reception reproduction data DATR is sequentially generated for every 5 bits of the code signal by 4 Bit / 5 Bit pattern inverse conversion. The reception reproduction data DATR is data of 4 bits per cycle synchronized with the 25 MHz reception clock signal CKRd.

  The transmission data generation unit 123 sequentially receives the reception reproduction data DATR from the reception data reproduction unit 122, extracts the data, adds or corrects the data, and sequentially generates the transfer data DATT. In this specification, the processing delay performed by the transmission data generation unit 123 is set to two fixed cycles (fixed cycle) with reference to the 25 MHz transmission clock signal (internal clock signal) CKTd. The transfer data DATT is 1-cycle 4-bit data synchronized with the 125 MHz transmission clock signal CKT.

  The example of FIG. 2 shows an example in which the head of the reception frame appears in the reception reproduction data DATR with a delay of 5 cycles from the reception signal SIGR in units of 125 MHz reception clock signal CKR. This delay range is 5 to 9 cycles in view of the above-described processing characteristics. At least 5 cycles are required for 5 bits of the received signal SIGR to be prepared, and the remaining 4 cycles are reserved cycles. Further, an example is shown in which the rising edge of the 25 MHz reception clock signal appears with a shift of 4 cycles from the rising edge of the 25 MHz transmission clock signal CKTd in units of 125 MHz reception clock signal CKR. The range of this deviation is naturally 0 to 4 cycles.

  The phase difference information detection unit 124 uses the 125 MHz reception clock signal CKR as a unit, the number of delay cycles from the reception signal SIGR to the reception reproduction data DATR (5 cycles in FIG. 2), and the 25 MHz reception clock signal CKRd with respect to the 25 MHz transmission clock signal CKTd. The number of shift cycles (4 cycles = ERN2 in FIG. 2) is detected. Then, a 25 MHz transmission clock signal is obtained by subtracting the detected value (5 cycles in FIG. 2) from the maximum number of delay cycles (9 cycles in FIG. 2) from the received signal to the received reproduction data (ERN1 = 9-5). A value obtained by adding the detection value of the number of shift cycles (ERN2 = 4) of the 25 MHz reception clock signal CKRd with respect to CKTd is calculated as phase difference information PHD (4 + 4 = 8 cycles). ERN1 is the number of cycles when the 4-bit / 5-bit pattern reverse conversion process is completed earlier than the permissible cycle (DES = 9 cycles), and ERN2 is a fixed cycle for obtaining transmission data DATT from reception data DATR. This is the number of extra cycles when the processing timing is earlier than the worst timing.

  The phase difference adjustment transmission unit 125 sequentially uses a 125 MHz transmission clock signal CKT obtained by multiplying the 25 MHz transmission clock signal CKTd by 5 times, and sequentially converts a 5-bit code signal per 4 bits to the transfer data DATT by 4 Bit / 5 Bit pattern conversion. Generate and sequentially serialize 5 bits of the code signal generated according to the 125 MHz transmission clock CKT, and sequentially delay by the number of cycles (ERN1 + ERN2) indicated by the phase difference information PHD in units of 125 MHz transmission clock signal CKT, and output as the transmission signal SIGT To do. The target time from the reception of the signal SIGR to the transmission of the naked body SIGT in the example of FIG. 2 is 196 nanoseconds, and this time is the processing time for 4-bit / 5-bit pattern reverse conversion and the processing for obtaining the transmission data from the reception data Is the time when the start timing is worst, and the cycle number (ERN1 + ERN2) indicated by the phase difference information PHD corresponds to an error time in the sense of a margin with respect to the worst case. Therefore, in the case of FIG. 2, the phase difference adjusting transmission unit 125 outputs the transmission signal SIGT with a delay of 8 cycles, so that, as a whole, the beginning of the transmission frame appears after the beginning of the reception frame appears in the reception signal SIGR. It is to spend 196 nanoseconds until it appears in the transmission signal SIGT. In short, even when the processing necessary for transfer can be completed in the best time, the worst processing time is spent to transmit the signal.

  FIG. 3 illustrates a timing chart of transfer processing when processing necessary for transfer is completed in the worst time. 3 differs from FIG. 2 in that there are two points, with the 125 MHz reception clock signal CKR as a unit, the beginning of the reception frame appears in the reception reproduction data after being delayed by 9 cycles from the reception signal, and the rising edge of the 125 MHz transmission clock signal CKT. This is the point at which the rising edge of the 25 MHz reception clock signal CKRd appears with a shift of 0 cycle from the edge (that is, the shift is less than 1 cycle, not shifted).

  In the case of FIG. 3, the phase difference information PHD is (9−9) + 0 = 0 cycle, and the phase difference information detection unit 124 calculates this value 0. Then, according to the value, the phase difference adjustment transmission unit 125 outputs the transmission signal SIGT with 0 cycle delay (that is, without delay). Overall, it takes 196 nanoseconds from the time when the head of the received frame appears in the received signal SIGR to the time when the head of the transmitted frame appears in the transmitted signal SIGT.

  In this way, by using the reception clock signal CKR as a unit, the delay of the reception reproduction data and the phase difference of the transmission clock signal are calculated, and the values are used for the transmission timing, thereby enabling low jitter transfer. In this example, the jitter generated in one transfer (processing from signal reception to signal transmission) in one communication processing overcolor 120 is caused by the difference between the 125 MHz reception clock CKR and the 125 MHz transmission clock CKT, and a maximum of 8 nanoseconds. Jitter can be suppressed to be small.

  FIG. 4 shows an example of the procedure of the communication processing operation performed by the communication processing circuit 120. The reception signal SIGR is received and the reception clock signal CKR and the divided clock signal CKRd are reproduced (S1), and the reception data DATR is reproduced using the reception clock signal CKRd (S2). The reception data DATR is extracted, added, and modified to generate transmission data DATT (S3), and a first target cycle number (DES) with respect to the number of clock cycles of the reception clock signal CKR is set. Along with detection of the error cycle number (ERN1), detection of a second error cycle number (ERN2) of the phase delay of the internal clock signal CKTd with respect to the divided clock signal CKRd with reference to the clock cycle of the reception clock signal CKR is performed. (S4). A transmission signal SIGT obtained by 4-bit / 5-bit pattern conversion with respect to the transmission data DATT is output after being delayed by the cycle of the phase difference information PHD = ERN1 + ERN2 obtained in this way (S5).

  FIG. 5 illustrates a data processing system using the data processing apparatus 101. This system is a system based on 100BASE-TX, and is applied to, for example, an industrial control network according to the EtherCAT standard.

  The data processing system includes a configuration in which a plurality of data processing nodes are connected to a communication path with a predetermined topology. The data processing node includes a master device 401, relay devices 421 and 422, and slave devices 411 to 416 arranged at the base point of the communication path, and outputs from the master device 401 are relay devices 421 and 422 and slave devices 411. ... 416 are cyclically transferred and returned to the master device 401.

  Each of the plurality of data processing nodes 401, 411 to 416, 421, and 422 includes the data processing apparatus 101 described with reference to FIG. Although not particularly limited, the allowable time represented by 169 nanoseconds described with reference to FIG. 2 and the like is set equally among all the data processing apparatuses 101.

  The master device 401 transmits control frame data to the first relay device 421. The first relay device 421 receiving it transfers it to the first slave device 411, and the first slave device 411 receiving it transfers it to the second slave device 412. To do. Receiving it, the second slave device 412 transfers (sends back) it to the first slave device 411.

  Thereafter, the first slave device 411, the first relay device 421, the third slave device 413, the second relay device 421, the fourth slave device 414, the second relay device 422, and the fifth slave device 415. Are transferred to the sixth slave device 416, the fifth slave device 415, the second relay device 422, the third slave device 413, and the first relay device 421, and finally received by the master device 401. When all the devices are circulated in this way, since the number of devices is nine, (9-1) × 2 = 16 times are transmitted as the connection between devices (the branch of the graph), and the device transfer processing (intermediate node) is 16−. 1 = 15 occurrences.

  If the jitter of each device is a maximum of 40 nanoseconds, the data processing of FIG. 1 is a jitter of a maximum of 8 nanoseconds while the jitter of the entire communication processing system is a maximum of 15 × 40 = maximum 600 nanoseconds When the apparatus 101 is adopted, the jitter when it is circulated in the entire data processing system and returned to the master apparatus 401 is 15 × 8 = 120 nanoseconds at maximum. As a result, each data processing device 101 can reduce the timing error from signal reception to signal transmission, so that it is possible to reduce the accumulation of jitter in a data processing system that circulates a plurality of data processing nodes and transfers signals. The real-time property and accuracy of the data processing system can be guaranteed. In short, a highly accurate data processing system can be realized.

  Furthermore, when the jitter of the entire data processing system is set to a maximum of 600 nanoseconds, up to nine devices can be connected if the jitter of each data processing device is a maximum of 40 nanoseconds, whereas the jitter is a maximum of 8 nanoseconds. When constructing a data processing system using the data processing apparatus 101 of FIG. 1 that is second, up to 39 data processing apparatuses can be connected (600 ÷ 8 = 75 transfer processes, 76 transmissions). . That is, a data processing system in which the number of data processing devices is further expanded can be realized.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, FIG. 1 assumes that the data processing apparatus 101 includes one network port (connector), but the data processing apparatus 101 includes a plurality of ports (for example, port A, It is also possible to provide three ports (port B and port C). Processing such as reception from port A is transmitted at port B, reception from port B is transmitted at port C, and reception from port C is transmitted at port A is also possible.

  In addition, the configuration of the data processing device 101 is such that the received data reproducing unit 122 updates data in the memory 112 and peripheral block (not shown) connected via the peripheral circuit 113 according to the contents of the received frame data, The transmission data generation unit 123 can embed data in the memory 112 and data in peripheral blocks (not shown) connected via the peripheral circuit 113 in the transmission frame data. Further, the communication processing circuit 120 processes the physical layer and the data link layer, and the processor 111 processes the upper layer than the data link layer while using the memory 112, so that general communication protocol processing can be performed. is there.

  The present invention is not limited to the IEEE 802.3 standard and the EtherCAT standard, and can be widely applied to data processing apparatuses and data processing systems for communication that are required to perform transfer with low jitter. Of course, the data processing apparatus 101 can be applied not only to the terminal apparatus constituting the data communication node but also to the relay apparatus.

  According to the embodiment described above, the data processor of each data processing node can reduce the timing error from signal reception to signal transmission. Further, it is possible to reduce the accumulation of jitter in a data processing system that circulates a plurality of data processing nodes and transfers signals, and to improve the real-time property and accuracy of the data processing system.

Reference Signs List 101 Data processing device 110 Data processing circuit 120 Communication processing circuit 111 Central processing unit (CPU)
112 memory 113 peripheral circuit 115 clock pulse generator (CPG)
114 Internal bus CKS System clock signal CKTd Internal clock signal CKT Transmission clock signal 121 Reception clock recovery unit 122 Reception data recovery unit 123 Transmission data generation unit 124 Phase difference information detection unit 125 Phase difference adjustment transmission unit CKR Reception clock signal CKRd Divided clock Signal SIGR Reception signal SIGT Transmission signal PHD Phase difference information DATR Reception data DATT Transmission data 401 Master device 421, 422 Relay device 411-416 Slave device

Claims (12)

A communication processing circuit and a data processing circuit;
The communication processing circuit includes a clock recovery unit that recovers a reception clock signal based on a reception signal;
A reception data reproduction unit that reproduces reception data from a reception signal in synchronization with the reception clock signal reproduced by the clock reproduction unit;
A transmission data generation unit that generates transmission data for the reception data reproduced by the reception data reproduction unit;
A transmission unit that generates a transmission signal from transmission data generated by the transmission data generation unit and transmits the transmission signal to the outside in synchronization with the transmission clock signal;
A detection unit that detects an error time when a processing time is short with respect to a time allowed from reception of a signal by the reception data reproduction unit to transmission of a transmission signal by the transmission unit;
The data processing apparatus, wherein the transmission unit waits for an error time by the detection unit to start transmission of a transmission signal. The clock recovery unit generates a divided clock signal having a frequency of 1 / n with respect to the received clock signal together with the received clock signal,
The received data reproduction unit reproduces a bit unit signal in synchronization with the reproduced reception clock signal, and decodes the reproduced bit signal in a plurality of bit units in synchronization with the divided clock signal. To play the received data,
The transmission data generation unit generates transmission data in synchronization with an internal clock signal having the same frequency as the divided clock signal,
The data processing apparatus according to claim 1, wherein the transmission unit encodes the transmission data and generates the transmission signal that is bit-synchronized with a transmission clock signal obtained by multiplying a frequency of the internal clock signal by n.   The detection unit detects a first error cycle number with respect to a target cycle number based on the number of clock cycles of the reception clock signal from when the reception data reproduction unit receives the reception signal until reproduction of valid reception data. And detecting a second error cycle number of the phase delay of the internal clock signal with respect to the divided clock signal with reference to the clock cycle of the received clock signal, and the first error cycle number and the second error cycle. The data processing apparatus according to claim 2, wherein a time corresponding to a cycle number summed with a number is an error time. The reception data generation unit provides reproduction data to the transmission data generation unit and, if necessary, to the data processing circuit,
4. The data processing according to claim 3, wherein the transmission data generation unit generates transmission data by performing data extraction, data addition, or data correction on the reproduction data in accordance with an instruction from the data processing circuit. apparatus. The data processing circuit has a central processing unit that executes instructions, a memory that is accessed by the central processing unit, a peripheral circuit that is controlled by the central processing unit, and a clock pulse generator that generates the internal clock signal,
The data processing apparatus according to claim 4, wherein the central processing unit operates in synchronization with the internal clock signal. A data processing system in which a plurality of data processing nodes are connected to a communication path with a predetermined topology,
Each of the plurality of data processing nodes includes a data processing device,
The data processing device has a communication processing circuit connected to the communication path and a data processing circuit connected to the communication circuit,
The communication processing circuit includes a clock recovery unit that recovers a received clock signal based on a received signal received from a communication path;
A reception data reproduction unit for reproducing reception data from a reception signal in synchronization with the reception clock signal reproduced by the clock reproduction unit;
A transmission data generation unit that generates transmission data for the reception data reproduced by the reception data reproduction unit;
A transmission unit that generates a transmission signal from transmission data generated by the transmission data generation unit and transmits the transmission signal to the communication path in synchronization with the transmission clock signal;
A detection unit that detects an error time when a processing time is short with respect to a time allowed from reception of a signal by the reception data reproduction unit to transmission of a transmission signal by the transmission unit;
The data processing system, wherein the transmission unit waits for an error time by the detection unit to start transmission of a transmission signal.   The plurality of data processing nodes include a master device, a relay device, and a slave device arranged at a base point of a communication path, and an output from the master device is cyclically transferred to the relay device and the slave device and returned to the master device. The data processing system according to claim 6.   The data processing system of claim 7, wherein the allowed time is set equal among all data processing devices. The clock recovery unit reproduces the received clock signal and generates a divided clock signal having a frequency of 1 / n with respect to the received clock signal.
The received data reproduction unit reproduces a bit unit signal in synchronization with the reproduced reception clock signal, and decodes and receives the bit signal reproduced in synchronization with the generated divided clock signal. Play the data,
The transmission data generation unit generates transmission data in synchronization with an internal clock signal having the same frequency as the divided clock signal,
9. The data processing system according to claim 8, wherein the transmission unit encodes the transmission data and generates the transmission signal that is bit-synchronized with a transmission clock signal obtained by multiplying the frequency of the internal clock signal by n.   The detection unit detects a first error cycle number with respect to a target cycle number based on the number of clock cycles of the reception clock signal from when the reception data reproduction unit receives the reception signal until reproduction of valid reception data. And detecting a second error cycle number of the phase delay of the internal clock signal with respect to the divided clock signal with reference to the clock cycle of the received clock signal, and the first error cycle number and the second error cycle. The data processing system according to claim 9, wherein a time corresponding to a cycle number summed with a number is an error time. The reception data generation unit provides reproduction data to the transmission data generation unit and, if necessary, to the data processing circuit,
The data processing according to claim 10, wherein the transmission data generation unit generates transmission data by performing data extraction, data addition, or data correction on the reproduction data according to an instruction from the data processing circuit. system. The data processing circuit has a central processing unit that executes instructions, a memory that is accessed by the central processing unit, a peripheral circuit that is controlled by the central processing unit, and a clock pulse generator that generates the internal clock signal,
The data processing system according to claim 11, wherein the central processing unit operates in synchronization with the internal clock signal.

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