JPH11308259A - Serial bus test device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To acquire all packets sent on a serial bus with a simple configuration. SOLUTION: When a physical layer circuit 4n receives a packet transmission signal from a serial bus 1 and outputs received data, a reception control circuit 31 writes sequentially the received data from data lines D0 -D7 via a register circuit 20 to a capture memory 30. Furthermore, when a link layer circuit 5. outputs transmission data configuring a transmission packet addressed to a node device 21 of a test object to the physical layer circuit 4n , the physical layer circuit 4n converts the data into a transmission signal and outputs it to a high speed serial bus 1, and the reception control circuit 31 writes sequentially transmission data received from the data lines D0 -D7 via the register circuit 20 in parallel with above to the capture memory 30. A controller displays contents of the capture memory 30 on a display device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a serial bus tester, and more particularly to a serial bus tester capable of taking in a series of a large amount of packets transferred on a serial bus and enabling processing such as display.

[0002]

2. Description of the Related Art In recent years, printers, digital cameras, external hard disks, and the like have been connected to a personal computer body in a daisy chain or tree structure to enable high-speed communication between arbitrary node devices. , A "high-speed serial bus"). This high-speed serial bus can connect a large number of node devices using a small cable,
Moreover, it has a feature that large-capacity data such as moving image data can be smoothly transferred.

As shown in FIG. 6, a high-speed serial bus 1 comprises:
Made by a serial bus cables ₁ 1 ~1 n-1 multiple-node device 2 ₁ to 2 _n are serially connected, each node device 2 _i, in accordance with an instruction of the controller 3 _i of the upper, the serial communication hardware level protocol It has a physical layer circuit 4 _{i for} controlling and a link layer circuit 5 _i . The physical layer circuit 4 _i is a serial bus cable 1 _i-1 , 1 _i
When a transmission signal from another node device transmitted on the serial bus cable 1 _i-1 (or 1 _i ) is received, the same transmission signal is transmitted to the serial bus cable 1 _i (or 1 _i-). and outputs to _1), and converts the received data, and outputs to the link layer circuit 5 _i. Further, when transmission data is input from the link layer circuit 5 _i , it is converted into a transmission signal and output to the serial bus cables 1 _i and 1 _i-1 .

The link layer circuit 5 _i generates a transmission packet addressed to another node device in accordance with an instruction from the upper controller 3 _i , and outputs transmission data constituting the transmission packet to the physical layer circuit 4 _i . Specifically, when the isochronous packet transfer is assured at 125 microsecond cycle, data length, channel number, when receiving the header information and data including the synchronization code from the controller 3 _i,
An isochronous packet of a predetermined format consisting of an integer multiple of 4 bytes is generated while adding a header CRC for error detection / correction obtained by calculation, a data block CRC, and the like (see FIG. 7), and two bits from the beginning (100 Mbi)
t / s transfer rate) or 4 bits at a time (200Mbi
t / s transfer rate) or one byte at a time (400Mbi
and outputs the transmission data divided in the case of a transfer rate of t / s) to the physical layer circuit 4 _i. In the case of asynchronous packets transferred asynchronously, there is a difference that a destination node ID and a source node ID are added to a header instead of a channel number.

[0005] When receiving data is input from the physical layer circuit 4 _i , the receiving packet to be taken by the own node is taken out and outputted to the controller 3 _i . The link layer circuit 5 _i and the physical layer circuit 4 _i include three control lines CTL0 and CT
L1, and受授a control signal via the LReq, among the eight data lines D ₀ to D ₇ while handshaking, 2 D ₀ and D ₁
This (if the transfer rate of 100Mbit / s), or D ₀ to D ₃
(In the case of 200 Mbit / s) or eight of D _{0 to} D ₇ (400 Mbit / s or more) to transmit and receive transmission data or reception data. The physical layer circuit 4 _i also has a function of performing bus arbitration at the time of transmission and outputting a clock SCLK synchronized with a control signal and data exchanged with the link layer circuit 5 _i .

[0006] A serial bus tester for performing operation tests of various node devices connected to a high-speed serial bus has been developed. This serious bus tester is bus-connected as one node device like other node devices, as shown by reference numeral 2 _n in FIG. 6, and a bus test controller 3 _n constituted by a microcomputer, for example. , A link layer circuit 5 _n , a physical layer circuit 4 _n , a memory 10, a display device 11, an operation panel 12, and the like. For example,
If the channel number 1 wants to test the node equipment 2 ₁ for isochronous transfer, various test data used for testing the previously node device 2 ₁ in the memory 10, the channel number node device 2 ₁ performs isochronous transfer, the node equipment 2 ₁ node ID, stores the node ID or the like of the serial bus tester.

[0007] instructs activation on the control panel 12 node device 2 _1, transmit controller 3 _n refers to the memory 10, the transfer speed (a 100Mbit / s in this case), a node ID of the node device 2 ₁ previous ID, the node ID is a source ID of the serial bus tester, and header information including the data length of the asynchronous packet, and outputs data including a start instruction to the link layer circuit 5 _n. Link layer circuit 5 _n header CRC, while wipe and data block CRC and generates an asynchronous packet in a predetermined format (see FIG. 8), notifies the transmission request and transfer rate physical layer circuit 4 _n through the control line LReq Then, when the physical layer circuit 4 _n wins the arbitration of access to the high-speed serial bus and gives the transfer permission through the control lines CTL0 and CTL1, the link layer circuit 5 _n sees the clock SCLK for a certain number of clocks ( CTL0, CTL1) = (01),
The data lines D _{0 to} D ₇ are all set to 0, and then the transmission data divided into two bits from the beginning of the asynchronous packet using the data lines D ₀ and D ₁ in synchronization with the clock SCLK is transmitted to the physical layer circuit 4 _n. (At this time, the link layer circuit 5 _n outputs (CTL0, CTL1) = (10) to indicate that transmission data is being output.)

The physical layer circuit 4 _n to which the transmission data is input
Converts the signal into an electrical transmission signal according to the standard and outputs the signal to a high-speed serial bus. Link layer circuit 5 _n has finished transmitting data output of one packet, when the packet to be transmitted to the other is not, the link layer circuit 5 _n completion transmitted to the (CTL 0, CTL1) from (10) (00) The physical layer circuit 4 _n receives the signal and shifts to another process.

[0009] When a transmission signal of isochronous packet node device 2 ₁ receiving a transmission signal of the asynchronous packet transmitted from the serial bus tester 2 _n is at a transfer rate of 100Mbit / s returned in a constant cycle, all other node device ₂ 2-2 physical layer circuit 4 ₂ to 4 _n receives the _n, the link layer circuit 5 ₂ to 5 _n to convert the received data
And outputs (in this case, indicates that the physical layer circuit 4 ₂ to 4 _n is the received data output by outputting via the control line CTL 0, CTL1 and (CTL0, CTL1) = (10 )).

[0010] link layer circuit 5 ₂ to 5 _n, the control line CT
When a control signal indicating that the received data is being output appears on L0 and CTL1, the received data is input in synchronization with the clock SCLK, and error detection / correction is performed on the header and data using the header CRC and the data CRC. And restore the received packet. Since it is an isochronous packet, it is checked whether the channel number included in the header has been instructed to be received from the upper controller, and if so, it is output to the upper controller. Ignore In the serial bus tester 2 _n, assuming that the received advance has been designated by the controller 3 _n, the link layer circuit 5 _n outputs the received packet from the node device 2 ₁ to the controller 3 _n, the controller 3 _n memory Stored in 10. Each time the isochronous packet is repeatedly received from the node device 2 _1, the same processing is repeated.

[0011] If it is instructed displayed on the operation panel 12, the controller 3 _n is to display the received packet stored in the memory 10 to the display device 11, the operator is to be checked.

[0012]

When testing a node device connected to a serial bus, it is necessary to check whether the node device under test is transmitting and receiving packets correctly. All packets transmitted on the serial bus must be monitored. Some link layer circuits have a snoop function that captures all received packets from the received data sequence input from the physical layer circuit and outputs them to the controller.
In order to transmit a desired packet to another node device in parallel, an extremely high processing speed is required, which imposes a heavy burden on the configuration. Further, since packets transmitted by the snoop function of the link layer circuit do not include transmission packets, all packets transmitted on the serial bus cannot be monitored in chronological order.

The present invention has been made in view of the above-mentioned problems of the prior art,
It is an object of the present invention to provide a serial bus tester that can acquire a series of packets transmitted on a serial bus with a simple configuration without any omission.

[0014]

In the serial bus tester according to the first aspect of the present invention, the serial bus tester is connected to a serial bus.
A physical layer circuit that receives a transmission signal from another node device transmitted on the serial bus, converts it to received data and outputs it, or converts transmission data to a transmission signal and transmits it on the serial bus; A link layer circuit that is connected to the physical layer circuit, generates a transmission packet addressed to another node device according to an instruction of a controller for a serial bus test, and outputs transmission data constituting the transmission packet to the physical layer circuit. In a bus tester, a controller for a serial bus test reads stored contents and is connected to a storage means capable of performing predetermined processing, and a data output side of a physical layer circuit and a link layer circuit, and a physical layer circuit and a link layer circuit. The input and output of the received data and the transmitted data, which are transmitted and received between the physical layer circuit and the link layer circuit A packet capture means for storing the packet in the storage means, further comprising a are characterized.

The physical layer circuit receives a transmission signal transmitted from another node device on the serial bus, converts it into reception data, and outputs it. Further, the link layer circuit generates a transmission packet addressed to another node device according to an instruction of the controller for the serial bus test, and outputs transmission data forming the transmission packet to the physical layer circuit. The packet capturing unit inputs the reception data and the transmission data output by the physical layer circuit and the link layer circuit, and stores a series of packets transmitted and received between the physical layer circuit and the link layer circuit in the storage unit. A series of packets stored in the storage means is read out by a controller for a serial bus test, subjected to predetermined processing such as display and printing, and used for analysis by an operator.

Thus, a series of packets transmitted on the serial bus, including the packets transmitted from the serial bus tester, can be taken into the storage means via a separate path from the serial bus test controller. Even without increasing the processing speed, the serial bus tester can transmit a desired packet to another node device in parallel while taking in a large number of packets transmitted on the serial bus.

According to the serial bus tester of the present invention, setting means for setting a packet serving as a reference for capturing is provided, and the packet capturing means has a fixed time relationship with respect to the reference packet set by the setting means. It is characterized in that a certain packet is stored in the storage means. As a result, it is possible to obtain a packet in any desired time range required for analysis, such as before and after transmitting a packet to the node device to be tested. According to the serial bus tester of the third aspect, the packet capturing means stores the packet timing information together. This makes it possible to analyze the timing of a packet transmitted on the serial bus.

In the serial bus tester according to the fourth aspect,
A physical device that is connected to the serial bus and receives transmission signals from other node devices transmitted on the serial bus and converts them into reception data, or converts transmission data into transmission signals and transmits them on the serial bus. According to the instruction of the controller for the serial bus test connected to the layer circuit and the physical layer circuit, generates a transmission packet addressed to another node device,
A link layer circuit for outputting transmission data constituting a transmission packet to a physical layer circuit, wherein the physical layer circuit and the link layer circuit receive and transmit a control signal via a control line and transmit and receive data while handshaking. In a serial bus tester, a controller for a serial bus test reads out stored contents and is connected to storage means capable of performing predetermined processing, and to a data output side and a control signal output side of a physical layer circuit and a link layer circuit, Received data and a control signal output from the physical layer circuit and transmission data and a control signal output from the link layer circuit are input, and a series of packets transmitted and received between the physical layer circuit and the link layer circuit are temporally synchronized with the control signal data. And a packet fetching means for storing the packet in the storage means in association with.

The physical layer circuit receives a transmission signal transmitted from another node device on the serial bus, converts the signal into reception data, and outputs the data. Further, the link layer circuit generates a transmission packet addressed to another node device according to an instruction of the controller for the serial bus test, and outputs transmission data forming the transmission packet to the physical layer circuit. At this time, the physical layer circuit and the link layer circuit exchange control signals via control lines and exchange data while performing handshaking. The packet capturing means receives the received data and control signal output from the physical layer circuit and the transmitted data and control signal output from the link layer circuit, and controls a series of packets transmitted and received between the physical layer circuit and the link layer circuit. The signal data is stored in the storage means in association with the time. A controller for a serial bus test reads out a series of packets and control signal data stored in the storage means, and performs predetermined processing such as display and printing.

Thus, in addition to a series of packets transmitted on the serial bus including the packet transmitted from the serial bus tester, the control signal data transmitted and received between the physical layer circuit and the link layer circuit is also transmitted by the packet. Since it can be taken in association with, more advanced analysis is possible.

According to the serial bus tester of the present invention, setting means for setting a packet to be a reference for capturing is provided, and the packet capturing means has a fixed time relationship with the reference packet set by the setting means. A certain packet is stored in the storage unit together with the corresponding control signal data. As a result, it is possible to obtain packets and control signal data in any desired time range required for analysis, such as before and after transmitting a packet to the node device to be tested. According to the serial bus tester of the sixth aspect, the packet capturing means stores the packet timing information together. This makes it possible to analyze the timing of a packet transmitted on the serial bus.

[0022]

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a serial bus tester according to the present invention, and the same components as those in FIG. 6 are denoted by the same reference numerals. Reference numeral 20 denotes a register circuit, which includes three 10-bit parallel registers (hereinafter simply referred to as registers) 21, 22, and 23 connected in series. Input side of the register 21 is the upper two control lines on the side of CTL 0, CTL1, a data line D of 8 to the lower ₀ to D ₇ are connected. Register 21 every time the input clock SCLK, and outputs captures simultaneously CTL0 and CTL1 and D ₀ to D _7. Each time the register 22 inputs the clock SCLK,
CTL0 output from the register 21 and CTL1 and D ₀ to D ₇
At the same time and output. Register 23 is clock
Each time SCLK is input, CTL0 output from register 22
Simultaneously it takes in and outputs the CTL1 and D ₀ to D _7. Therefore, the value of the control lines CTL 0, CTL1 and the data lines D ₀ to D ₇ are
The data is sequentially transferred from the registers 21 to 23.

Reference numeral 24 denotes a transfer rate identification circuit which monitors the output of the register 23 and the control line LReq, identifies the transfer rate from the output of the register 23 when receiving a packet, and outputs the output of the control line LReq when transmitting a packet. Identify the transfer speed from That is, the physical layer circuit 4 _n receives a transmission signal from the high-speed serial bus 1, when outputting the received data in synchronization with the clock SCLK, first, converted to a (00) from (10) (CTL 0, CTL1) , (D _{0 to} D ₇ ) = (11111111) = (FF) for a certain number of clocks as viewed from the clock SCLK
After outputting ₁₆ , the transfer rate code is output, and then the received data is output from the beginning of the received packet. Ten
In the case of ₀ Mbit / s, the transfer rate code is (D _{0 to} D ₇ ) =
(00xxxxxx), the case of 200 Mbit / s, the transfer rate code _{(D 0 ~D 7) = (} 0100xxxx), 400Mbi
For t / s, the transfer rate code _{(D 0 ~D 7) = (} 01
000000) (x is set to 0 and ignored by the link layer circuit 5 _n ).

In the case of 100 Mbit / s, the received data is D ₀ and D
Outputs 2 bits at a time using ₁ and at 200 Mbit / s,
Received data is output 4 bits by using the D ₀ to D _3, the case of 400 Mbit / s, the received data is output 8 bits using D ₀ to D _7. The transfer speed identification circuit 24 monitors CTL0 and CTL1 output from the register 23,
When (CTL 0, CTL1) is changed to (00) from (10), then, (D ₀ to D ₇₎ is (FF) identifies the transfer rate from the value of ₁₆ from the unusual first (D ₀ to D ₇₎ Then, it immediately outputs the transfer speed identification data to the byte position detection circuit, the pattern detection circuit, and the capture control circuit, which will be described later.

When the link layer circuit 5 _n intends to transmit a packet, the link layer circuit 5 _n outputs a transmission request and a transfer rate data to the physical layer circuit 4 _n via a control line Req in advance. Transfer speed identification circuit 2
When the transfer speed data is input through Req, the transfer speed identification unit 4 identifies the transfer speed, and then outputs the transfer speed identification data when (CTL0, CTL1) changes from (00) to (01).

Reference numeral 25 denotes a byte position detection circuit. Based on CTL0 and CTL1 output from the register 23 and the transfer speed identification data input from the transfer speed identification circuit 24, the byte number of the transmission packet or the reception packet is represented by D _{0 of the} register 23. ~ D
Detect whether it is output from ₇ . Specifically, (CTL
0, CTL1) when inputting the transfer speed identification data in a state of change in the (00) from (10), the head of the reception of the received packet from D ₀ to D ₇ of the register 23 upon receiving the next clock SCLK Data is output. Therefore, if the transfer rate is 100 Mbit / s, the count value K initialized to −1 when (CTL0, CTL1) changes from (00) to (10) is input to the transfer rate identification data, clock
Each time SCLK is input, the count is incremented by +1 and a value obtained by adding +1 to a quotient q obtained by dividing the count value K by 4 is output as byte position detection data (the byte position detection circuit 25 sets the byte position detection data to zero in advance. And).

If the transfer rate is 200 Mbit / s, (CTL0,
When (CTL1) changes from (00) to (10), the count value K initialized to -1 is incremented by +1 each time the clock SCLK is input after the transfer speed identification data is input, and the count value is counted. The quotient q obtained by dividing the value K by 2
Is output as byte position detection data.
If the transfer speed is 400 Mbit / s, (CTL0, CTL1)
After the transfer rate identification data is input, the count value K initialized to -1 at the time of the change from 0) to (10) is incremented by +1 each time the clock SCLK is input, and the count value K is incremented by +1. The value obtained is output as byte position detection data.

Conversely, when (CTL0, CTL1) changes from (00) to (01), the transfer speed identification data is input, and when (CTL0, CTL1) changes from (01) to (10), in the beginning of the transmission data of the transmission packet from D ₀ to D ₇ of the register 23 is output. Therefore, (CTL0,
After the count value K is initialized to zero when (CTL1) changes from (01) to (10), if the transfer rate is 100 Mbit / s, the count is incremented by +1 each time the clock SCLK is input, and A value obtained by adding +1 to a quotient q obtained by dividing the count value K by 4 is output as byte position detection data. If the transfer speed is 200 Mbit / s, (CTL0, CTL1)
After the count value K is initialized to zero at the time when the count value changes from 1) to (10), the count value is incremented by +1 each time the clock SCLK is input, and a value obtained by adding 1 to a quotient q obtained by dividing the count value K by 2 Is output as byte position detection data. If the transfer speed is 400Mbit / s, (CTL0, CTL1)
When the value changes from (01) to (10), the count value K
After initializing to zero, every time the clock SCLK is input, +
While counting up by one, the count value K is output as byte position detection data.

Reference numeral 26 denotes a pattern detection circuit which detects an 8-bit pattern at a byte position in the transmission packet or the reception packet detected by the byte position detection circuit 25. After inputting the transfer speed identification data indicating 100 Mbit / s, the pattern detection circuit 26 thereafter outputs the outputs D ₀ and D ₁ of the register 23 to d ₀ and d ₁ , and outputs the outputs D ₀ and D _{1 of} the register 22.
₁ is d ₂ and d ₃ , and the outputs D ₀ and D ₁ of the register 21 are d ₄
And d ₅ , and outputs D ₀ and D ₁ of the link layer circuit 5 _n to d ₆
And d ₇ , and (d ₀ d ₁ d ₂ d ₃ d ₄ d ₅ d
₆ d ₇ ), and output 8-bit pattern data by parallel output (here, 100 Mbit / s)
, The MSB of each byte data constituting the packet,
2SB, 3SB, 4SB, 5SB, 6SB, 7SB, L
SB is 2 bits, (D ₀ D ₁ ) = (MSB 2S
_{B), (D 0 D 1} ) = (3SB4SB), (D 0 D 1)
_{= (5SB6SB), (D 0} D 1) = (7SBLSB)
It shall be transferred between the physical layer circuit 4 _n and the link layer circuit 5 _n divided so on).

The pattern detection circuit 26 operates at 200 Mbit / s
Is input, the outputs D _{0 to} D ₃ of the register 23 are extracted as d ₀ to d ₃ , and the outputs D _{0 to} D ₃ of the register 22 are extracted as d ₄ to d ₇ , and (d ₀ d
₁ d ₂ d ₃ d ₄ d ₅ d ₆ d ₇ ) are arranged in this order and output in parallel, thereby outputting 8-bit pattern data (here, at 200 Mbit / s, the MSB of each byte data constituting the packet) , 2SB, 3SB, 4SB, 5S
B, 6SB, 7SB, and LSB are 4 bits each, (D ₀
D ₁ D ₂ D ₃ ) = (MSB2SB3SB4SB), (D
₍₀ D ₁ D ₂ D ₃ ) = (5SB6SB7SBLSB) and transferred between the physical layer circuit 4 _n and the link layer circuit 5 _n ).

When the transfer speed identification data indicating 400 Mbit / s is input, the outputs D _{0 to} D _{7 of the} register 23 are thereafter output.
As d ₀ to d ₇ , and (d ₀ d ₁ d ₂ d ₃ d ₄
By performing parallel output in the order of d ₅ d ₆ d ₇ ), 8-bit pattern data is output (here, 400 Mbit / s)
, The MSB of each byte data constituting the packet,
2SB, 3SB, 4SB, 5SB, 6SB, 7SB, L
SB is (D ₀ D ₁ D ₂ D ₃ D ₄ D ₅ D ₆ D ₇ ) = (M
It shall be transferred between the physical layer circuit 4 _n and the link layer circuit 5 _n divided so on SB2SB3SB4SB5SB6SB7SBLSB)).

Reference numeral 27 denotes a reference packet setting circuit, in which information for specifying a reference packet when a series of packets is taken in from the high-speed system bus 1 is set by the controller 3 _n . Here, as one example, one or a plurality of combinations of byte positions in a packet and 1-byte data at the byte positions are set. When a plurality is set, the order is the byte position (see FIG. 2). Numeral 28 denotes a collating circuit which determines whether the combination of the byte position set by the reference packet setting circuit 27 and the one-byte data at the byte position matches the combination detected by the byte position detecting circuit 25 and the pattern detecting circuit 26. When the data is collated, and all the data match in the order set by the reference packet setting circuit 27, the reference packet detection signal is fetched and output to the control circuit.

A timer 29 measures the current time in units of ten nanoseconds or hundred nanoseconds. 30 is a capture memory having a first area and a second area,
The first area includes the physical layer circuit 4 _n and the link layer circuit 5
A series of a large number of packets transmitted and received between _n are stored in time series in association with the control signal data CTL0 and CTL1, and the second area stores the storage location of the first area, the transfer speed,
The start time is stored.

Reference numeral 30 denotes a capture control circuit, which is a control signal data output from the register 23 of the register circuit 20.
With reference to CTL0, CTL1 and the transfer rate identified by the transfer rate identification circuit 24, data of a series of packets having a fixed time relationship with respect to a reference packet among received packets or transmitted packets output from the register 23 is stored. In addition, the first area of the capture memory 30 is stored in association with the control signal data CTL0 and CTL1, and the storage location, transfer speed, and start time of the first area are stored in the second area for each packet. A packet capture circuit 32 is configured by the register circuit 20, the transfer speed identification circuit 24, the byte position detection circuit 25, the pattern detection circuit 26, the collation circuit 28, the timer 29, and the capture control circuit 31.

The controller 3 _n ′ instructs the link layer circuit 5 _n to instruct transmission of a packet to a desired node device, or instructs transmission of a packet to a desired node device in accordance with a packet transmission or reception instruction on the operation panel 12. To receive a packet from Further, in accordance with an instruction on the operation panel 12, the received packet stored in the memory 10 is displayed on the display device 11, and the packet and control signal data stored in the capture memory 30 are displayed on the display device 11. The reference packet is set in the reference packet setting circuit 27 of the packet capture circuit 32, and the capture range is specified in the capture control circuit 31. The other components of the serial bus tester 2 _n are configured exactly the same as in FIG.

Next, the operation of the above-described embodiment will be briefly described with reference to FIGS. 3 is an explanatory diagram of the stored contents of the first area of the capture memory 30, FIG. 4 is an explanatory view of the stored contents of the second area of the capture memory 30, and FIG. 5 is an explanatory view showing a display example of the display device 11. Here, it is assumed to perform the operation test of the node devices 2 _1, node equipment 2
_In FIG. 1, an example is shown in which all transmission packets on the high-speed serial bus 1 are monitored over a fixed time range before and after a transmission packet for a certain start command is transmitted. Memory 1
0 Various test data used for testing in advance node device 2 _1, the node channel number the device 2 ₁ performs isochronous transfer, the node equipment 2 ₁ node ID, the node ID or the like of the serial bus tester 2 ₅ are stored Shall be It is assumed that the link layer circuit 5 _n does not have a snoop function.

(1) Packet Reception When the node devices 2 ₁ , 2 _2, etc. are outputting a packet transmission signal on the high-speed serial bus 1, the physical layer circuit 4 _{n of} the serial bus tester 2 _n receives the packet. And the clock SC
Outputs received data in synchronization with LK. At this time, first,
Change (CTL0, CTL1) from (00) to (10). When the physical layer circuit 4 _n receives the packet and changes the control lines CTL0 and CTL1 from (00) to (10), the link layer circuit 5 _n inputs the received data in synchronization with the clock SCLK. Then, the received packet is restored while performing error detection / correction on the header and data using the header CRC and the data CRC.

And even if it is an isochronous packet,
If the channel number included in the header is
Ruler 3_n´ Check if it was instructed to receive
Controller 3 if shown_n´ output to the finger
If not indicated, the current received packet is ignored. Ma
In the case of an asynchronous packet, the destination ID is
Check if it matches the node ID, and match
Then controller 3 _nOutput to ´, not instructed
If so, the current received packet is ignored. Controller 3
_n'Is the link layer circuit 5_nInput received packet from
Then, it is stored in the memory 10. Then, the operation panel 12
Necessary processing such as displaying on the display device 11
Work.

The link layer circuit 5 _n does not have a snoop function, and cannot take in all received packets based on the received data input from the physical layer circuit 4 _n . In this embodiment, the provision of the packet capturing circuit 32 and the capture memory 30 enables capturing of a series of large amounts of packets transmitted on the high-speed serial bus 1.

That is, when the physical layer circuit 4 _n receives a transmission signal from the high-speed serial bus 1 and outputs received data in synchronization with the clock SCLK, first, (CTL0, CTL1)
Is changed from (00) to (10). Capture control circuit 3
1 monitors CTL0 and CTL1 of the register 23, and (CT
L0, CTL1) from unusual point (10) from (00), the synchronization with the clock SCLK register 23 (D ₀ to D
₇ ) Write 10-bit data including (CTL0, CTL1) in order from address 0 in the first area of the memory 30 (see FIG. 3).

When the transfer speed data is output from D _{0 to} D _{7 of the} register 23, the transfer speed identification circuit 24 identifies the transfer speed and outputs it to the byte position detection circuit 25, pattern detection circuit 26, and capture control circuit 31. I do. When the transfer rate identification data is input, the capture control circuit 31 next displays D _{0 to} D ₇ output from the register 23 on the reception packet P.
Since the received data is the first received data of A, the address (7) written in the first area is used as the first address of the received packet _PA together with the transfer speed indicated by the transfer speed identification data and the time data TPA measured by the timer 29. Write in two areas.

Assuming that the transfer speed is 400 Mbit / s,
The received data PA ₀ , PA ₁ ,... In units of 1 byte are output from D _{0 to} D ₇ of the register 23 and stored in the first area together with CTL 0 and CTL 1. When writing of the last 1-byte data PA _m of the received packet PA is completed, the register 2
(CTL0, CTL1) output from 3 becomes (00),
Since (D ₀ to D ₇₎ become (00000000), after writing these data in the first area, the last (0
Since D ₀ to D ₇ corresponding to 1) is the last received data of the received packet PA, is written in the second area addresses when writing to the first region (206) as the end address of the received packet PA .

Thereafter, when the next packet PB is received, the capture control circuit 31 synchronizes with the clock SCLK from the time when the output (CTL0, CTL1) of the register 23 changes from (00) to (10). (D _0-
D ₇ ) and (CTL0, CTL1) are sequentially written in 10-bit data starting from the address 208 in the first area of the memory 30 (see the address 208 and thereafter in FIG. 3).

When the transfer speed data is output from D _{0 to} D _{7 of the} register 23, the transfer speed identification circuit 24 identifies the transfer speed and outputs it to the byte position detection circuit 25, pattern detection circuit 26, and capture control circuit 31. I do. When the transfer rate identification data is input, the capture control circuit 31 next displays D _{0 to} D ₇ output from the register 23 on the reception packet P.
Since the received data is the first received data of B, the address (214) at the time of writing into the first area is used as the first address of the received packet _PB together with the transfer speed indicated by the transfer speed identification data and the time data T _PB measured by the timer 29. Write in two areas.

Assuming that the transfer speed is 200 Mbit / s,
The received data PB ₀ , PB ₁ ,... In units of 4 bits are output from D ₀ to D _{3 of the} register 23 and stored in the first area together with CTL 0 and CTL 1 (x in FIG. , Is ignored as packet data). When writing of the last 4-bit data PB _y of the received packet PB is finished, is outputted from the register 23 (CTL 0, CTL1) is (0
0) and (D _{0 to} D ₇ ) become (00000000), so after writing these data in the first area, the last D _{0 to} D ₃ corresponding to (01) is the last of the received packet PB. Therefore, the address (673) at the time of writing to the first area is written to the second area as the end address of the received packet PB (see FIG. 4). Hereinafter, the same operation is repeated every time a new packet is received. When writing data to the last address of the first area, the capture control circuit 31 returns to the first address and performs writing.

[0046] (2) to instruct the start of the node equipment 2 ₁ transmits the operation panel 12 of the packet,
The controller 3 _n 'refers to the memory 10, the transfer speed (here a 100Mbit / s), the destination ID is a node ID of the node device 2 _1, the transmission source ID is a node ID of the serial bus tester, the data length of the asynchronous packet, the header information including the synchronization code, and outputs data including a start instruction to the link layer circuit 5 _n. To set the asynchronous packet as a reference packet, first, the first byte (upper byte) of the destination ID
And the second byte (lower byte) are paired with the byte position in the packet and set in the reference packet setting circuit 27. Next, the first byte (upper byte) and the second byte (lower byte) of the transmission source ID Is set in the reference packet setting circuit 27 as a pair with the byte position in the packet (see FIG. 2).
Then, it instructs the capture control circuit 31 to capture packets over a fixed time range before and after the reference packet.

The link layer circuit 5 _n receiving the transmission instruction from the controller 3 _n ′ generates an asynchronous packet of a predetermined format (see FIG. 8) while adding a header CRC, a data block CRC, and the like, and transmits the asynchronous packet through the control line LReq. When the physical layer circuit 4 _n notifies the physical layer circuit 4 _n of the transmission request and the transfer speed, and the physical layer circuit 4 _n wins the arbitration of the access to the high-speed serial bus and gives the transfer permission through the control lines CTL0 and CTL1, the link layer circuit 5 _n some clock only a few minutes (CTL0, CTL1) (01) , (D 0 ~
After D ₇ ) is set to (00) ₁₆ , the transmission data divided into two bits from the beginning of the asynchronous packet is output to the physical layer circuit 4 _n using the data lines D ₀ and D ₁ in synchronization with the clock SCLK. (At this time, the link layer circuit 5
_n indicates (CTL0, CTL1) = (10) and indicates that transmission data is being output).

The physical layer circuit 4 _n to which the transmission data has been input
Converts the signal into an electrical transmission signal conforming to the standard and outputs the signal to the high-speed serial bus 1. When the link layer circuit 5 _n finishes outputting one packet of transmission data and there are no other packets to be transmitted, the link layer circuit 5 _n (CTL0, CTL1)
Is changed from (10) to (00) to indicate transmission completion, and upon receiving this signal, the physical layer circuit 4 _n shifts to another processing.

Meanwhile, the packet capture circuit 32, the link layer circuit 5 _n outputs the transfer speed together with the transmission request via a control line LReq, the transfer rate identification circuit 24 identifies the transfer rate, then the output of the register 23 ( CTL0,
(CTL1) changes from (00) to (01)
The transfer rate identification data indicating 100 Mbit / s is transferred to the byte position detection circuit 25, the pattern detection circuit 26, and the capture control circuit 3.
Output to 1.

When the output (CTL0, CTL1) of the register 23 changes from (00) to (10), the capture control circuit 31 synchronizes the (D) of the register 23 with the clock SCLK.
_{0 to} D ₇ ) and (CTL0, CTL1) are sequentially written into the first area of the capture memory 30 (see the address (j-5) and thereafter in FIG. 3). Capture control circuit 31 D ₀ to D _7, which is output from the register 23 at the time of changing the output of the register 23 (CTL 0, CTL1) from (01) to (10) is received data of the head of the transmission packet RA Therefore, the address (j) written in the first area is written in the second area together with the transfer speed and the time data T _PB measured by the timer 29 as the head address of the transmission packet RA.

Assuming that the transfer speed is 100 Mbit / s,
The transmission data RA ₀ , RA ₁ ,... In 2-bit units are output from D ₀ and D ₁ of the register 23, and are stored in the first area together with CTL0 and CTL1. When writing of the last 1-byte data RA _z of the transmission packet RA is completed, the register 2
(CTL0, CTL1) output from 3 becomes (00),
Since (D ₀ to D ₇₎ become (00000000), after writing these data in the first area, the last (1
Since D ₀ and D ₁ corresponding to (0) are the last transmission data of the transmission packet RA, the address (j + 600) written in the first area is written in the second area as the end address of the transmission packet RA. .

When transmitting the current packet, the byte position detection circuit 25 outputs the output (CT
(L0, CTL1) changed from (00) to (01)
When inputting transfer speed identification data indicating 0 Mbit / s,
When (CTL0, CTL1) changes from (01) to (10), the count value K is initialized to zero, and is incremented by +1 each time the clock SCLK is input. Then, a value obtained by adding +1 to a quotient q obtained by dividing the count value K by 4 is output as byte position detection data (the byte position detection circuit 25 previously initializes the byte position detection data to zero).

Further, the pattern detection circuit 25 is 100 Mbit / s
Is input, the outputs D ₀ and D ₁ of the register 23 are set to d ₀ and d ₁ , the outputs D ₀ and D ₁ of the register 22 are set to d ₂ and d ₃ , and the output D _{0 of the} register 21 is set.
And D ₁ to d ₄ and d ₅ , and the output D ₀ of the link layer circuit 5 _n
And D ₁ as d ₆ and d ₇ , and (d ₀ d ₁ d ₂ d
Side by side in the order of _{3 d 4 d 5 d 6 d} 7) by a parallel output, and outputs the 8-bit per Tan data.

Each time the byte position detected by the byte position detection circuit 25 changes from zero to 1, 1 to 2, 2 to 3,..., The collation circuit 28 immediately sets each byte set in the reference packet setting circuit 27. It is checked whether the byte position matches the byte position. When the byte position matches, the 8-bit pattern detected by the pattern detection circuit 26 at that time matches the byte data set in the reference packet setting circuit 27 in association with the byte position. Check if.

The detection pattern when the detected byte position is 1 matches the upper byte data of the transmission destination ID set corresponding to the first byte position 1 set in the reference packet setting circuit 27. The detection pattern when the detected byte position is 2 is the transmission destination ID set corresponding to the second byte position 2 set in the reference packet setting circuit 27.
The detection pattern when the detected byte position is 5 is the same as the lower byte data of the reference packet setting circuit 27.
The detection pattern when the upper byte data of the transmission source ID set in correspondence with the third byte position 5 set in the above is set, and finally, the detection pattern when the detected byte position is 6 is set in the reference packet setting circuit 27. When the data matches the lower byte data of the transmission source ID set corresponding to the fourth byte position 6, the matching circuit 28 takes in the reference packet detection signal and outputs it to the control circuit 31.

When the capture control circuit 31 receives the reference packet detection signal, the capture in a fixed time range centered on the reference packet is instructed in advance by the controller 3 _n ′. Thereafter, all the addresses in the first area are read. an amount of half the (D ₀ ~D ₇₎ writes the 10-bit data (CTL0, CTL1). As a result, a series of packets for approximately the same time before and after the current transmission packet RA can be captured in the first area.

All the transmission data for the transmission packet RA is written in the first area, and the output (CT
When L0, CTL1) becomes (00), the capture control circuit 31
Temporarily suspends writing to the first area, and then, when a new packet transmitted on the high-speed serial bus 1 is received, writes the new packet to the capture memory 30 in the same manner as described above.

[0058] When a transmission signal of isochronous packet node device 2 ₁ receiving a transmission signal of the asynchronous packet transmitted from the serial bus tester 2 _n is at a transfer rate of 100Mbit / s returned in a constant cycle, the physical layer circuit 4 _n it is received and outputs the converted reception data to the link layer circuit 5 _n. The link layer circuit 5 _n receives the clock SCLK
Received data is input in synchronism with the above, and the received packet is restored while performing error detection / correction on the header and data using the header CRC and the data CRC. Since isochronous packet, the controller 3 as long as the channel number included in the header is checked or not is instructed to receive from the controller 3 _n 'of the upper, is instructed _n
'. The controller 3 _n ′ stores the data in the memory 10.

Meanwhile, the packet received from the node device 2 _1, in the same manner as described above, receiving circuit 32 by CTL 0,
The data is written in the first area of the capture memory 30 in chronological order in association with the control signal data of CTL1. Also, the start address and end address, the transfer speed, and the time data at which the received packet is written are written to the second area of the capture memory 30. Each time the isochronous packet is repeatedly received from the node device 2 _1, the same processing is repeated.

Thereafter, after the reference packet detection signal is input first, 10-bit data of (D ₀ -D ₇ ) and (CTL 0, CTL 1) corresponding to half of all addresses of the first area are newly added. After writing, capture memory 3
Writing to 0 is completed. As a result, the capture memory 30, centered on the transmission packet RA given as an activation command to the node device 2 _1, including the front and rear of the received packet, a sequence of transmitted over a high-speed serial bus 1 within a predetermined time because the information of all packets are stored, it is possible later to accurately check the operation characteristics of the node equipment 2 _1.

When the operator instructs the operation panel 12 to display the received packet fetched into the memory 10, the controller 3 _n ′ reads out the received packet from the memory 10 and displays it on the display device 11. However, not all received packets are fetched into the memory 10 and there are no transmitted packets, so that the number of analysis items that can be performed is limited. On the other hand, when the operator instructs the operation panel 12 to display the packet captured in the capture memory 30, the controller 3 _n ′ reads out the packet from the capture memory 30 and displays it on the display device 11 as shown in FIG. 5 (FIG. 5). In the figure, the contents of the beginning of a series of packets transmitted on the high-speed serial bus 1 are displayed in chronological order.By scrolling right, the back of each packet can be seen. By scrolling down, you can see the packet later in time.)

[0062] in the capture memory 30 are incorporated all the packets transmitted over the high-speed serial bus 1, the control signal the data CTL 0, CTL1 are also associated, which is a node device 2 ₁ to be tested It is possible to analyze in detail what kind of operation is performed at such timing.

The reference packet can be set for a received packet. Controller 3
_{If n} 'indicates that the capture starting from the reference packet has been instructed, the capture control circuit 31 writes to the last address of the first area, returns to the first address, and starts counting from the start address of the reference packet. The writing may be completed when the writing is performed up to the address ten clocks earlier. Alternatively, when the capture with the reference packet as the end point is instructed, the capture control circuit 31
May be completed at the point of time when writing has been completed to the end of the reference packet.

According to the above-described embodiment, a serial bus test controller 3 _n ′ includes a series of packets transmitted on the high-speed serial bus 1 including a packet transmitted from the serial bus tester 2 _n. Since the data is fetched into the capture memory 30 through a separate path and read out from the capture memory 30 and desired processing such as display can be performed later, the serial bus tester 2 _n can be used without increasing the processing speed of the controller 3 _n ′. Can capture a large number of packets transmitted on the high-speed serial bus 1 and transmit a desired packet to another node device in parallel.

A reference packet setting circuit 27 for setting a packet to be a reference for capturing is provided. A packet capturing circuit 32 captures a packet having a fixed time relationship with respect to the reference packet set by the reference packet setting circuit 27. Since the packet is stored in the memory 30, it is possible to obtain a packet in any desired time range required for analysis, such as before and after transmitting a packet to the node device to be tested. Further, since the packet capturing circuit 32 also stores the packet timing information, the timing of the packet transmitted on one high-speed serial bus can be analyzed.

Further, in addition to a series of packets transmitted on the high-speed serial bus 1 including the packet transmitted from the serial bus tester 2 _n , transmission and reception between the physical layer circuit 4 _n and the link layer circuit 5 _n Since the obtained control signal data can also be taken in association with the packet, it is possible to perform more advanced analysis such as whether or not the transfer rate of the received packet is correctly detected.

[0067]

According to the present invention, a series of packets transmitted on the serial bus, including the packets transmitted from the serial bus tester, are loaded into the storage means via a path separate from the serial bus test controller. Thus, the controller can transmit a desired packet to another node device in parallel while taking in a large number of packets transmitted on the serial bus without increasing the processing speed.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial bus tester according to one embodiment of the present invention.

FIG. 2 is an explanatory diagram of data set in a reference packet setting circuit in FIG. 1;

FIG. 3 is an explanatory diagram of storage contents of a first area of a memory in FIG. 1;

FIG. 4 is an explanatory diagram of storage contents of a second area of the memory in FIG. 1;

FIG. 5 is an explanatory diagram of a display example of the display device in FIG. 1;

FIG. 6 is an explanatory diagram showing a connection method of a high-speed serial bus.

FIG. 7 is an explanatory diagram showing a format of an isochronous packet used in a high-speed serial bus.

FIG. 8 is an explanatory diagram showing a format of an asynchronous packet used in a high-speed serial bus.

[Explanation of symbols]

1 high-speed serial bus 2 _1, 2 _i-node device 2 _n serial bus tester 3 _n 'controller 4 _n physical layer circuit 5 _n the link layer circuit 10 memory 11 display 12 operation panel 20 register circuits 21, 22 and 23 register 24 transfers Speed discrimination circuit 25 Byte position detection circuit 26 Pattern detection circuit 27 Reference packet setting circuit 28 Collation circuit 29 Timer 30 Capture memory 31 Capture control circuit 32 Packet capture circuit

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[Procedure amendment]

[Submission date] May 14, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG. 2

FIG.

FIG. 3

FIG. 4

FIG. 7

FIG. 8

FIG. 5

FIG. 6

Claims (6)

[Claims] 1. A serial bus connected to a serial bus to receive a transmission signal from another node device transmitted on the serial bus, convert the transmission signal into reception data, and output the transmission data, or convert the transmission data into a transmission signal to transmit the serial signal. A physical layer circuit to be transmitted on the bus, and a transmission packet that is connected to the physical layer circuit and that is transmitted to another node device according to an instruction of a controller for a serial bus test, and that transmits transmission data constituting the transmission packet to the physical layer. A serial layer tester including: a link layer circuit for outputting to a circuit; a serial bus test controller which reads out stored contents and performs predetermined processing; storage means; and a data output side of the physical layer circuit and the link layer circuit To receive the transmission data and the transmission data output from the physical layer circuit and the link layer circuit, and Serial bus tester packet capture means for storing a series of packets in the storage unit exchanged between the link layer circuit, comprising the a. 2. Setting means for setting a packet serving as a reference for capturing is provided. The packet capturing means stores a packet having a fixed temporal relationship with the reference packet set by the setting means in the storage means. The serial bus tester according to claim 1, wherein: 3. The serial bus tester according to claim 1, wherein the packet capturing means stores packet timing information together. 4. A serial bus, which receives a transmission signal from another node device transmitted on the serial bus and converts it into reception data, or converts transmission data into a transmission signal and places it on the serial bus. Generates a transmission packet addressed to another node device according to the instruction of the controller for the serial bus test connected to the physical layer circuit to be transmitted and the physical layer circuit, and outputs transmission data constituting the transmission packet to the physical layer circuit. A physical layer circuit and a link layer circuit for transmitting and receiving control signal data via a control line and transmitting and receiving data while performing handshaking. A storage unit capable of reading stored contents and performing predetermined processing; data output of a physical layer circuit and a link layer circuit Connected to the control signal output side to receive the received data and control signal data output by the physical layer circuit, and the transmission data and control signal data output by the link layer circuit, and to transmit and receive between the physical layer circuit and the link layer circuit. And a packet capturing means for storing a series of packets to be stored in the storage means in a time-related manner with control signal data. 5. Setting means for setting a packet serving as a reference for capturing is provided. The packet capturing means is configured to transmit a series of packets having a fixed time relationship with respect to the reference packet set by the setting means in time and control signal data. 5. The serial bus tester according to claim 4, wherein the serial bus tester is stored in a storage unit in association with the serial bus tester. 6. The serial bus tester according to claim 4, wherein the packet capturing means stores packet timing information together.