JPH11308246A - Serial bus testing equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To produce an error intentionally with a simple configuration. SOLUTION: A link layer circuit 5n generates a transmission packet whose destination is other node device 21 according to an instruction of a serial bus test controller 3n and outputs a transmission data stream configuring transmission packets toward a physical layer circuit 4n . A transmission error generating circuit 20 that is interposed between the physical layer circuit 4n and the link layer circuit 5n gives transmission data to the physical layer circuit 4n while part of the transmission data stream configuring the transmission packets are changed into different data when the link layer circuit 5n generates and outputs a transmission packet whose destination is the other node device 21 . The physical layer circuit 4n converts the transmitted data into a transmission signal and outputs it to a high speed serial bus 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a serial bus tester, and more particularly, to a serial bus tester capable of transmitting an erroneous packet to a node device to be tested.

[0002]

2. Description of the Related Art In recent years, printers, digital cameras, external hard disks, and the like have been connected to a personal computer body in a daisy chain or tree structure to enable high-speed communication between arbitrary node devices. , A "high-speed serial bus"). This high-speed serial bus can connect a large number of node devices using a small cable,
Moreover, it has a feature that large-capacity data such as moving image data can be smoothly transferred.

As shown in FIG. 3, a high-speed serial bus 1 comprises:
Made by a serial bus cables ₁ 1 ~1 n-1 multiple-node device 2 ₁ to 2 _n are serially connected, each node device 2 _i, in accordance with an instruction of the controller 3 _i of the upper, the serial communication hardware level protocol It has a physical layer circuit 4 _{i for} controlling and a link layer circuit 5 _i . The physical layer circuit 4 _i is a serial bus cable 1 _i-1 , 1 _i
When a transmission signal from another node device transmitted on the serial bus cable 1 _i-1 (or 1 _i ) is received, the same transmission signal is transmitted to the serial bus cable 1 _i (or 1 _i-). and outputs to _1), and converts the received data, and outputs to the link layer circuit 5 _i. Further, when transmission data is input from the link layer circuit 5 _i , it is converted into a transmission signal and output to the serial bus cables 1 _i and 1 _i-1 .

The link layer circuit 5 _i generates a transmission packet addressed to another node device in accordance with an instruction from the upper controller 3 _i , and outputs a transmission data sequence constituting the transmission packet to the physical layer circuit 4 _i . Specifically, 125 case of isochronous packet transfer is guaranteed in microseconds cycle, data length, channel number, and header information including a synchronization code, receives data from the controller 3 _i, the error determined by calculation Header CR for detection / correction
C, a data block CRC and the like are added, and an isochronous packet of a predetermined format consisting of an integer multiple of 4 bytes is generated (see FIG. 4), and two bits from the beginning (in the case of a transfer rate of 100 Mbit / s), or (If the transfer rate of 200 Mbit / s) bit by, or outputs transmission data sequence divided into 8-bit (if a transfer rate of 400 Mbit / s) to the physical layer circuit 4 _i. In the case of an asynchronous packet transferred asynchronously, there is a difference that a destination node ID and a source node ID are added to header information instead of a channel number.

When a received data sequence is input from the physical layer circuit 4 _i , a received packet to be captured by the own node is extracted and output to the controller 3 _i . The link layer circuit 5 _i and the physical layer circuit 4 _i include three control lines CTL0,
CTL1, and受授a control signal via the LReq, handshake while the eight data lines D ₀ ~D _7, (if the transfer rate of 100Mbit / s) 2 pieces of D ₀ and D _1, D _{0 to} D ₃ 4
8 (in the case of 200 Mbit / s), 8 of D _{0 to} D ₇ (400 Mbit / s)
s) to transmit or receive data. The physical layer circuit 4 _i also has a function of performing bus arbitration at the time of transmission and outputting a clock SCLK synchronized with a control signal and data exchanged with the link layer circuit 5 _i .

[0006] A serial bus tester for performing operation tests of various node devices connected to a high-speed serial bus has been developed. This serious bus tester is bus-connected as one node device like other node devices, as indicated by reference numeral 2 _n in FIG. 3, and a bus test controller 3 _n configured by a microcomputer, for example. , A link layer circuit 5 _n , a physical layer circuit 4 _n , a memory 10, a display device 11, an operation panel 12, and the like. For example,
If the channel number 1 wants to test the node equipment 2 ₁ for isochronous transfer, various test data used for testing the previously node device 2 ₁ in the memory 10, the channel number node device 2 ₁ performs isochronous transfer, the node equipment 2 ₁ node ID, stores the node ID or the like of the serial bus tester.

[0007] instructs activation on the control panel 12 node device 2 _1, transmit controller 3 _n refers to the memory 10, the transfer speed (a 100Mbit / s in this case), a node ID of the node device 2 ₁ previous ID, the node ID is a source ID of the serial bus tester, and header information including the data length of the asynchronous packet, and outputs data including a start instruction to the link layer circuit 5 _n. Link layer circuit 5 _n header CRC, and generates an asynchronous packet of predetermined format (see FIG. 5) while wipe and data CRC, and notifies the transmission request and transfer rate physical layer circuit 4 _n through the control line LReq , the physical layer circuit 4 _n wins the arbitration for access to high-speed serial bus, given a transfer permission through the control lines CTL 0, CTL1, a data line D ₀ and D ₁ and the link layer circuit 5 _n synchronizes the clock SCLK and outputs the transmission data into 2 bits from the head of the asynchronous packet to the physical layer circuit 4 _n using (this time, the control indicating that the link layer circuit 5 _n is transmitting data output to the control line CTL 0, CTL1 Signal).

The physical layer circuit 4 _n to which the transmission data is input
Converts the signal into an electrical transmission signal according to the standard and outputs the signal to a high-speed serial bus. Link layer circuit 5 _n has finished transmitting data output of one packet, when the packet to be transmitted to the other is not, the link layer circuit 5 _n control lines CTL 0, CTL1
, A control signal indicating the completion of transmission is output, and upon receiving this signal, the physical layer circuit 4 _n shifts to another process.

[0009] When a transmission signal of isochronous packet node device 2 ₁ receiving a transmission signal of the asynchronous packet transmitted from the serial bus tester 2 _n is at a transfer rate of 100Mbit / s returned in a constant cycle, all other node device ₂ 2-2 physical layer circuit 4 ₂ to 4 _n receives the _n, the link layer circuit 5 ₂ to 5 _n to convert the received data
And outputs (in this case, the physical layer circuit 4 ₂ to 4 _n outputs a control signal indicating that it is receiving data output to the control line CTL 0, CTL1).

[0010] link layer circuit 5 ₂ to 5 _n, the control line CT
When a control signal indicating that the received data is being output appears on L0 and CTL1, the received data is input in synchronization with the clock SCLK, and error detection / correction is performed on the header and data using the header CRC and the data CRC. And restore the received packet. Since it is an isochronous packet, it is checked whether the channel number included in the header has been instructed to be received from the upper controller, and if so, it is output to the upper controller. Ignore In the serial bus tester 2 _n, assuming that the received advance has been designated by the controller 3 _n, the link layer circuit 5 _n outputs the received packet from the node device 2 ₁ to the controller 3 _n, the controller 3 _n memory 11 is stored. Each time the isochronous packet is repeatedly received from the node device 2 _1, the same processing is repeated.

[0011] If it is instructed displayed on the operation panel 12, the controller 3 _n is to display the received packet stored in the memory 11 to the display device 11, the operator is to be checked.

[0012]

[SUMMARY OF THE INVENTION Incidentally, with respect to the node device 2 ₁ tested, or are incorrect value of deliberately data length, and transmits the incorrect packet header CRC and data CRC, I want a performance test In this case, a commercially available link layer circuit 5 _n generates a correct packet in accordance with the standard, so that it is necessary to specially manufacture a link layer circuit that generates an error packet, which is difficult to realize. An object of the present invention is to provide a serial bus tester capable of performing an operation test of a target device by intentionally generating an error with a simple configuration in view of the above-described problems of the related art.

[0013]

In the serial bus tester according to the first aspect of the present invention, the serial bus tester is connected to a serial bus.
A physical layer circuit that receives a transmission signal from another node device transmitted on the serial bus and converts it into received data, or converts transmission data into a transmission signal and outputs it on the serial bus, and a physical layer circuit In accordance with the instruction of the controller for the serial bus test, a transmission packet addressed to another node device is generated, and a transmission data sequence constituting the transmission packet is output to the physical layer circuit, and a reception data sequence is output from the physical layer circuit. A link layer circuit for inputting and extracting a predetermined received packet and outputting the received packet to a controller for a serial bus test, wherein the link layer circuit is interposed between the physical layer circuit and the link layer circuit. Generates and outputs a transmission packet addressed to the other node device, the transmission data That the provision of the transmission error generation circuit for input to the physical layer circuit while changing the data, it is characterized in.

According to the first aspect of the present invention, when the link layer circuit generates and outputs a transmission packet addressed to the other node device, the packet is input to the physical layer circuit while changing part of the packet to different data. Thus, a packet having an error can be transmitted with a simple configuration without using a special link layer circuit, and an operation test at the time of receiving an error packet can be realized.

In the serial bus tester according to the second aspect of the present invention, the transmission error generation circuit includes a setting unit for setting an error occurrence position in the transmission packet, and a transmission error generation circuit for transmitting each transmission data of the transmission packet output by the link layer circuit. On the other hand, the detecting means for detecting the position in the packet, and when the position detected by the detecting means does not match the error occurrence position set by the setting means, the transmission data output from the link layer circuit is directly transmitted to the physical layer circuit. When the position detected by the detection unit matches the error occurrence position set by the setting unit, the transmission data output by the link layer circuit is replaced with different data and input to the physical layer circuit. Means.

According to the second aspect of the present invention, for each transmission data of the transmission packet output by the link layer circuit, the position in the packet is detected by the detecting means, and coincides with the error occurrence position set by the setting means. If not, the transmission data output from the link layer circuit is directly input to the physical layer circuit. If the detection position of the detection unit matches the error occurrence position set by the setting unit, the link layer circuit outputs the data. The transmission data to be transmitted is replaced with different data and input to the physical layer circuit. Thereby, by changing the error occurrence position set by the setting means, an error can be generated at any desired position in the packet,
A wide range of tests is possible.

[0017]

Next, an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a serial bus tester according to the present invention, and the same components as those in FIG. 3 are denoted by the same reference numerals. Reference numeral 20 denotes a transmission error generation circuit which, when the link layer circuit 5 _n generates a transmission packet for another node device and outputs a transmission data sequence constituting the transmission packet, partially replaces the data with another data to replace the physical layer. It is input to a circuit to generate a transmission packet having an error.

[0018] Among the transmission error generation circuit 20, 21 is a transfer direction discrimination circuit, the physical from the control signal, the data lines D ₀ to D ₇ are now from the link layer circuit 5 _n which is output to the control line CTL0 and CTL1 whether identified are used for data transfer to the layer circuit 4 _n, and outputs the L level when being used to transfer data from the link layer circuit 5 _n to the physical layer circuit 4 _n, not used At this time, an H level is output. Reference numerals 22 and 23 denote buffer circuits connected to the output side of the transfer direction discriminating circuit 21. Reference numeral 22 denotes an L level when the input is at the L level, and an H level when the input is at the H level. At the H level and the H level, the L level is output.

Reference numerals 24 and 25 _denote buffer circuits connected in series between the D ₀ terminal of the physical layer circuit 4 _{n and} the D ₀ terminal of the link layer circuit 5 _n . Becomes active, physical layer circuit 4
_{n D0} terminal output as it is, link layer circuit 5 _n D
Input to terminal ₀ . Buffer circuit 26, EX-NOR
After the circuit 27 and the buffer circuit 28 are connected in series, they are connected in parallel with the buffer circuits 24 and 25 connected in series. While the output of the buffer circuit 23 is at the H level, the buffer circuits 26 and 28 become active, and the EX-NOR
The input from the data replacement instructing circuit of the circuit 27 described later is H
Between, as it is input to the D ₀ terminal of the physical layer circuit 5 _n the D ₀ pin output link layer circuit 5 _n, between the input from the data replacement instruction circuit is L, the link layer circuit 5
by inverting the _n D ₀ pin output of the physical layer circuit 5 _n of D ₀
Input to terminal.

[0020] 29 is an error occurrence position setting circuit, the instruction of the controller 3 _n, the position to generate an error in the transmitted packet is set in the byte position from the packet head. One or a plurality of error occurrence positions may be set, and by setting none, an error-free packet can be transmitted. Reference numeral 30 denotes a byte position detection circuit for detecting a byte position from the head of the packet when the link layer circuit 5 _n outputs a transmission data sequence forming a transmission packet. Specifically, when the control signal is output to the control line CTL0 and CTL1 showed output start of the transmission data for one certain packets from the link layer circuit 5 _n to the physical layer circuit 4 _n, detection byte position Byte position 1 is output, and then the number of times the clock SCLK is input is counted and the count value is set to k. When the transfer rate indicated by LReq is 100 Mbit / s, every time k becomes a multiple of 4, The byte position is incremented by +1 and output,
When the transfer rate is 200 Mbit / s, the byte position is incremented by 1 each time k becomes a multiple of 2 and output. When the transfer rate is 400 Mbit / s or more, the byte position is incremented by 1 each time k increases by 1. The output is incremented (see FIG. 2).

Reference numeral 31 denotes a data replacement instructing circuit. When the byte position detected by the byte position detecting circuit 30 coincides with the position set by the error occurrence position setting circuit 29, the L level is changed to the EX-NOR circuit 27. Out of the transmission data output from the link layer circuit 5 _n
0 is inverted and input to the physical layer circuit 4 _n , otherwise, the H level is output to the EX-NOR circuit 27, and D ₀ is inverted among the transmission data output from the link layer circuit 5 _n. It is input to the physical layer circuit 4 _n without. The other components of the serial bus tester 2 _n are exactly the same as those shown in FIG.

Next, the operation of the above embodiment will be described with reference to FIG. Here, it is assumed that node equipment 2 ₁ performs an operation test when receiving a packet having the error, for convenience of explanation, the transfer rate of the transmission packet from the serial bus tester 2 _n is assumed to be 100Mbit / s . Also,
It is assumed that an error occurs in the 13th and 14th bytes where the data length value exists in the asynchronous packet.

When the start of the node device 2 ₁ is instructed on the operation panel 12, the controller 3 _n refers to the memory 10 and sets the transfer speed (here, 100 Mbit / s) and the node device 2 _1.
Destination ID is the node ID, the node ID is a source ID of the serial bus tester, and header information including the data length of the asynchronous packet, and outputs data including a start instruction to the link layer circuit 5 _n. Further, it instructs the error occurrence position setting circuit 29 of the transmission error generation circuit 20 to set the 13th byte and the 14th byte.

The link layer circuit 5 _n adds the correct header CRC, data CRC, etc. obtained by calculation to the asynchronous packet of a predetermined format (see FIG. 5).
To generate a, and notifies the physical layer circuit transmission request to 4 _n and the transfer rate through the control line LReq, the physical layer circuit 4 _n wins the arbitration for access to high-speed serial bus, control lines CTL, transfer permission through CTL When given, the link layer circuit 5 _n synchronizes the data line D ₀ with the clock SCLK.
The transmission data is output to the physical layer circuit 4 _n by two bits from the beginning of the asynchronous packet by using the D and D ₁ (in this case, the link layer circuit 5 _n indicates that the transmission data is being output to the control lines CTL0 and CTL1). A control signal is output (see FIG. 2).

[0025] The link layer circuit 5 _n the control line CTL0, CTL1
While outputting the control signal indicating that the transmission data is being output to the transfer direction identification circuit 21, the transfer direction identification circuit 21 outputs the L level,
Since the buffer circuit 22 outputs the L level, both the buffer circuits 24 and 25 become inactive, and the buffer circuit 23 outputs the H level.
8 are both active.

On the other hand, the transfer speed = 100 Mbit /
The byte position detection circuit 30 to which s has been input transmits a control signal output from the link layer circuit 5 _n to the control lines CTL0 and CTL1 for one packet from the link layer circuit 5 _n to the physical layer circuit 4 _n . When the start of data output is indicated, byte position 1 is output, followed by clock SCLK
Is counted and the count value is k,
Each time k becomes a multiple of 4, the byte position is incremented by +1 and output (see FIG. 2).

[0027] The link layer circuit 5 _n the control line CTL0 CTL1
When the output of the control signal indicating that the transmission data is being output is started, the _first two bits of the transmission packet are output to D ₀ and D ₁ , and thereafter, two bits are output in synchronization with the clock SCLK. In the first to twelfth bytes and the fifteenth to last bytes of the transmission packet, the byte position detected by the byte position detection circuit 30 does not match the error occurrence position set by the error occurrence position setting circuit 29. , Data replacement instructing circuit 31 outputs an H level. Therefore, the output of D ₀ of the link layer circuit 5 _n is supplied to the buffer circuit 26, EX.
-NOR circuit 27, is directly input to the physical layer circuit 4 _n via a buffer circuit 28. Link layer circuit 5
_n output D ₁ of the are of course be directly input to the physical layer circuit 4 _n.

At the 13th and 14th bytes of the transmission packet, the byte position detected by the byte position detection circuit 30 matches the error occurrence position set by the error occurrence position setting circuit 29, and the data replacement instruction circuit 31 Output level. Therefore, the output of D ₀ of the link layer circuit 5 _n is E
It is inverted by the X-NOR circuit 27 is input to the physical layer circuit 4 _n (the output of the link layer circuit 5 _n of D ₁ is directly input to the physical layer circuit 4 _n). As a result, the physical layer circuit 4 _n outputs a transmission signal of a transmission packet having an error in the data length value to the high-speed serial bus 1.

The link layer circuit 5 _n has finished transmitting data output of one packet, when the packet to be transmitted to the other is not, the link layer circuit 5 _n outputs a control signal indicating the transmission completion to the control line CTL 0, CTL1 Upon receiving the signal, the physical layer circuit 4 _n shifts to another process.

[0030] By transmitting the packet having the error to the node device 2 _1, it is possible to node equipment 2 ₁ checks whether correct handling error packets. Wakashi, when node device 2 ₁ is returned to the transmission signal of isochronous packet at a predetermined period at a transfer rate of 100Mbit / s, receives the physical layer circuit 4 _n is, converts the received data to the link layer circuit 5 _n I do. At this time, the physical layer circuit 4 ₂
Since to 4 _n outputs a control signal indicating that it is receiving data output to the control line CTL 0, CTL1, transfer direction discrimination circuit 21 of the transmission error generation circuit 20 outputs the H level, the buffer circuit 26 and 28 Becomes inactive, the buffer circuits 24 and 25 become active, and the physical layer circuit 4
receiving data outputted from the _n is inputted as it is to the link layer circuit 5 _n.

The link layer circuit 5 ₂ to 5 _n, the control line CT
When a control signal indicating that the received data is being output appears on L0 and CTL1, the received data is input in synchronization with the clock SCLK, and error detection / correction is performed on the header and data using the header CRC and the data CRC. And restore the received packet. Since it is an isochronous packet, it is checked whether the channel number included in the header has been instructed to be received from the upper controller, and if so, it is output to the upper controller. Ignore In the serial bus tester 2 _n, assuming that the received advance has been designated by the controller 3 _n, the link layer circuit 5 _n outputs the received packet from the node device 2 ₁ to the controller 3 _n, the controller 3 _n memory Stored in 10. Each time the isochronous packet is repeatedly received from the node device 2 _1, the same processing is repeated.

[0032] If it is instructed displayed on the operation panel 12, the controller 3 _n is to display the received packet stored in the memory 10 to the display device 11, examiner to allow checking.

According to this embodiment, when the link layer circuit 5 _n generates and outputs a transmission packet addressed to another node device, the transmission error generation circuit 20 changes the physical packet in the physical layer circuit while changing a part of the packet to different data. 4 Input to _n . Therefore, without using a special link layer circuit,
With a simple configuration, a packet having an error can be transmitted to a node device to be tested, and an operation test when an error packet is received can be realized.

For each transmission data of the transmission packet output from the link layer circuit 5 _n , the position in the packet is detected by the byte position detection circuit 30, and the error occurrence position set by the error occurrence position setting circuit 29 is determined. If they do not match, the transmission data output from the link layer circuit 5 _n is directly input to the physical layer circuit 4 _n, and the detection position of the byte position detection circuit 30 is set to the error occurrence position setting circuit 2.
If the position matches the error occurrence position set in step 9,
Since the transmission data output from the link layer circuit 5 _n is replaced with different data and input to the physical layer circuit 4 _n , by changing the error occurrence position in the error occurrence position setting circuit 29, it can be set at any desired position in the packet. An error can be generated and a wide range of tests can be performed.

[0035]

According to the present invention, when the link layer circuit generates and outputs a transmission packet addressed to another node device, the packet is input to the physical layer circuit while changing the predetermined data position of the packet to different data. Without using a simple link layer circuit, a packet having an error can be transmitted with a simple configuration, and an operation test upon reception of an error packet can be realized.

[Brief description of the drawings]

FIG. 1 is a block diagram of a serial bus tester according to one embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the transmission error generation circuit in FIG. 1;

FIG. 3 is an explanatory diagram showing a connection method of a high-speed serial bus.

FIG. 4 is an explanatory diagram showing a format of an isochronous packet used in a high-speed serial bus.

FIG. 5 is an explanatory diagram showing a format of an asynchronous packet used in a high-speed serial bus.

[Explanation of symbols]

1 High-speed serial bus 2 ₁ , 2 ₂ , 2 _i
Node equipment 2 _n serial bus tester 3 _i , 3 _n controller 4 _i , 4 _n physical layer circuit 5 _i , 5 _n link layer circuit 10 memory 11 display device 12 operation panel 20 transmission error generation circuit 21 transfer direction identification circuit 22, 23, 24, 25, 26, 28 Buffer circuit 27 EX-NOR circuit 29 Error occurrence position setting circuit 30 Byte position detection circuit 31 Data replacement instruction circuit

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[Procedure amendment]

[Submission date] May 14, 1998

[Procedure amendment 1]

[Document name to be amended] Drawing

[Correction target item name] All figures

[Correction method] Change

[Correction contents]

FIG. 2

FIG.

FIG. 3

FIG. 4

FIG. 5

Claims (2)

[Claims] 1. A serial bus connected to a serial bus for receiving a transmission signal from another node device transmitted on the serial bus and converting the transmission signal into reception data, or converting transmission data into a transmission signal and transmitting the transmission signal on the serial bus. A physical layer circuit to be output, and a transmission packet destined for another node device is generated according to an instruction of a controller for a serial bus test connected to the physical layer circuit, and a transmission data sequence constituting the transmission packet is transmitted to the physical layer circuit. A link layer circuit that outputs a received data sequence from a physical layer circuit, extracts a predetermined received packet, and outputs the packet to a controller for a serial bus test. Interposed between the circuits,
When the link layer circuit generates and outputs a transmission packet destined for another node device, a transmission error generation circuit is provided for inputting to the physical layer circuit while changing a part of the transmission data sequence constituting the transmission packet to different data, A serial bus tester. 2. A transmission error generating circuit, comprising: setting means for setting an error occurrence position in a transmission packet; and detecting means for detecting a position in the packet for each transmission data of the transmission packet output by the link layer circuit. If the position detected by the detecting means does not match the error occurrence position set by the setting means, the transmission data output by the link layer circuit is directly input to the physical layer circuit, and the position detected by the detecting means is set. And a data replacement means for replacing the transmission data output by the link layer circuit with different data and inputting the data to the physical layer circuit when the error occurrence position set by the means is matched. 2. The serial bus tester according to 1.