JPH11307645A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which is possessed of an equivalent parasitic capacitance reduction effect in a low frequency range as well as in a high-frequency range by a method, wherein a semiconductor layer in a range where no transistor is formed is lessened in conductance, and a manufacturing method thereof. SOLUTION: A semiconductor device is equipped with a bipolar transistor where a collector layer is formed of an epitaxial layer, in which a high-resistance embedded layer 3 is formed in a region on a semiconductor substrate 1 where a bipolar transistor is not formed, whereby a polysilicon electrode 9a and a polysilicon resistor 9b which are a thin film device and an aluminum wiring 18 are lessened in parasitic capacitance to facilitate acceleration of a circuit in the operation speed having no effect on the characteristic of the transistor. Therefore, a high-resistance embedded layer 3 with lower in carrier concentration than that in the substrate 1 is formed beforehand in a region of the P-type silicon substrate 1 before an n<-> -epitaxial layer 4 is formed through an ion implantation method. With this constitution, a semiconductor layer in a region where no transistor is formed is lessened in conductance, whereby a semiconductor device can be made to possess an equivalent parasitic capacitance reduction effect in a high-frequency range at a low frequency range as well as.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, which are particularly suitable for bipolar integrated circuits.

[0002]

2. Description of the Related Art FIGS. 9 and 10 show a conventional semiconductor device and a method of manufacturing the same. FIGS. 9 and 10 are longitudinal sectional views of a semiconductor chip arranged in a process order for explaining a conventional method of manufacturing a bipolar semiconductor integrated circuit. It is shown.

First, as shown in FIG. 9A, a high-concentration n ⁺ -type buried layer 2 is formed only in a region on a p-type silicon substrate 1 where a bipolar transistor is to be formed.
As shown in (b), the n ⁻ -type epitaxial layer 4 is grown on the entire surface to form a collector layer. Next, an insulation trench 5 as shown in FIG. Subsequently, as shown in FIG. 9D, an n ⁺ -type collector extraction layer 6 for electrically extracting the n ⁺ -type buried layer 2 to the surface of the n ^-- type epitaxial layer 4 with low resistance is formed by ion implantation. Is formed.

Then, as shown in FIG. 9E, an oxide film 7 is grown on the entire surface, and a base contact 8 is opened in a region where a base and a graft base layer are to be formed. A polysilicon base electrode 9a as shown in FIG. 10F is formed so as to cover the base contact 8. At this time,
At the same time, a polysilicon resistor 9b is formed. FIG.
As shown in (g), after the entire surface is covered with the first interlayer insulating film 10, an emitter contact 11 is opened in the emitter formation region.

Further, as shown in FIG. 10 (h), a p ⁺ -type graft base layer 12 is formed by ion implantation using the polysilicon base electrode 9a as a diffusion source, and a p-type base layer 13 is formed. Polysilicon emitter electrode 1
4, an n-type impurity is diffused on the very surface of the p-type base layer 13 to form an emitter layer. Further, the entire surface is covered with a second interlayer insulating film 15 to form a polysilicon base electrode 9a.
And a contact hole 16 for electrically connecting the polysilicon emitter electrode 14, the n ⁺ -type collector lead-out layer 6, and the polysilicon resistor 9b. FIG.
As shown in (i), the inside of the contact hole 16 is buried with a tungsten plug 17 and the respective elements are interconnected via an aluminum wiring 18 to complete an integrated circuit.

The polysilicon resistor 9b or the aluminum wiring 1 of the bipolar integrated circuit manufactured as described above is used.
8 has a structure as shown in FIG. That is, the polysilicon resistor 9b is connected to the oxide film 7 (capacitance C _OX ), n
^- type epitaxial layer 4 (conductance G _n, capacitance C
_n ), n ⁻ type epitaxial layer 4-p type silicon substrate 1
Interface pn junction (capacitance C _j ) and p-type silicon substrate 1
(Conductance G _p , capacitance C _p ).

Similarly, the aluminum wiring 18 comprises an insulating film (capacitance C _OX ) composed of the first interlayer insulating film 10, the second interlayer insulating film 15 and the oxide film 7, and the n ⁻ -type epitaxial layer 4. (Conductance G _n , capacitance C _n ), pn junction (capacitance C _j ) at the interface of n ⁻ -type epitaxial layer 4-p-type silicon substrate 1, and series impedance of p-type silicon substrate 1 (conductance G _p , capacitance C _p ) Is coupled with the back surface of the p-type silicon substrate 1.

FIG. 1 is an equivalent circuit showing this impedance.
2, the resistance R is equivalently obtained for a certain frequency.
It can be considered by replacing with the series impedance of _eff and capacitance C _eff . Here, the p-type silicon substrate 1 and n ⁻
Since the type epitaxial layer 4 is formed with a relatively low impurity concentration, it functions as a series capacitance between the wiring and the substrate at a high frequency. This has the effect of reducing the equivalent parasitic capacitance C _eff of the polysilicon resistor 9 b and the aluminum wiring 18, and is particularly advantageous for high-frequency circuit operation.

[0009]

However, a problem in the conventional semiconductor device and the method of manufacturing the same is that the equivalent capacitance (C _n ) and conductance component (G _n ) of the epitaxial layer are relatively large. There is a problem that a sufficient capacity reduction effect cannot be obtained unless the frequency that can be regarded as the capacitance is relatively high and does not reach a considerably high frequency such as several tens of GHz or more.

The first reason is that although the impedance of the epitaxial layer depends on its growth thickness, the growth thickness cannot be increased unnecessarily in order to maintain the high performance of the transistor.

The second reason is that although the impedance of the epitaxial layer also depends on the impurity concentration, in order to stabilize the variation in the characteristics of the transistor, the n-type can be maintained and the variation in the impurity concentration can be tolerated. It is necessary to grow under the growth conditions that can be obtained in a stable manner, and the impurity concentration cannot be thinly reduced.

According to the present invention, a capacitance reduction effect can be obtained at a lower frequency without affecting transistor characteristics with respect to a circuit element insulated from a semiconductor substrate such as a polysilicon resistor or a parasitic capacitance of a wiring. It is an object of the present invention to provide a semiconductor device and a method of manufacturing the same, which can easily manufacture a semiconductor device having such a substrate structure, thereby facilitating a high-speed circuit operation.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device having a bipolar semiconductor integrated circuit, wherein a bipolar transistor on a surface of a first conductivity type semiconductor substrate is not formed. A high-resistance buried layer in which a first conductivity type impurity or a second conductivity type impurity is added at a low concentration is provided in the region.

According to a second aspect of the present invention, in the first aspect, a semiconductor layer having a carrier concentration lower than at least the first conductivity type semiconductor substrate is formed in the high-resistance buried layer. I do.

According to a third aspect of the present invention, in the first aspect of the present invention, a depth of the high resistance buried layer into the first conductivity type semiconductor substrate is 3 μm or more.

According to a fourth aspect of the present invention, in the first aspect, the high-resistance buried layer comprises two or more semiconductor layers of different conductivity types.

According to a fifth aspect of the present invention, a first semiconductor region serving as a high resistance buried layer in which a second conductivity type impurity is added at a low concentration is formed in a region on the surface of the first conductivity type semiconductor substrate where no bipolar transistor is formed. Forming a second semiconductor region to be a collector buried layer by adding a second conductive type impurity at a high concentration to a region for forming a bipolar transistor on a surface of the first conductive type semiconductor substrate; Growing a second conductivity type epitaxial layer on the substrate surface;
Forming an insulating isolation region reaching the first conductivity type semiconductor substrate from the surface of the epitaxial layer separating the first semiconductor region and the second semiconductor region and deeper than the high-resistance buried layer;
The method includes a step of growing an insulating film on the surface of the epitaxial layer and a step of forming a thin film element or a wiring on the insulating film.

According to a sixth aspect of the present invention, in the fifth aspect of the invention, a semiconductor layer having a carrier concentration lower than at least the first conductivity type semiconductor substrate is formed in the high resistance buried layer. I do.

According to a seventh aspect of the present invention, in the fifth aspect of the present invention, the depth of penetration of the high-resistance buried layer into the semiconductor substrate is 3 μm or more.

According to an eighth aspect of the present invention, in the fifth aspect of the present invention, a high-resistance buried layer is formed by adding an impurity of the second conductivity type by ion implantation and thermally diffusing the same. .

According to a ninth aspect of the present invention, in the fifth aspect of the present invention, the high-resistance buried layer comprises two or more semiconductor layers of different conductivity types.

<Operation> For example, in a manufacturing process of a bipolar transistor in which a collector layer is formed by an epitaxial layer, an impurity having a conductivity type opposite to that of a substrate is added to a substrate region where a transistor is not formed, and at least a carrier is transferred from the substrate. by forming a low density high resistance buried layer, the conductance of the high-resistance buried layer portion (the G _n If the high-resistance buried layer is n-type, contributes to the G _p in the case of p-type) Is reduced, the frequency at which this region can be regarded as a capacitance decreases, and at lower frequencies, the high-resistance buried layer functions as a series capacitance, so that the entire equivalent parasitic capacitance is reduced.

Further, regardless of the conductivity type of the high resistance buried layer,
The depletion layer of the pn junction expands toward the high-resistance buried layer, and the junction capacitance (C _j ) decreases. Further, since the high-resistance buried layer is not formed in the transistor formation region, the formation of the high-resistance buried layer does not affect the transistor characteristics.

[0024]

Next, embodiments of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1A, in a semiconductor device and a method of manufacturing the same according to an embodiment of the present invention, a second-conductivity-type impurity is added at a high concentration to a bipolar transistor formation region on the surface of a first-conductivity-type semiconductor substrate 1. When forming the n ⁺ -type buried layer 2 serving as a collector layer, the second conductivity type impurity is also added to a region of the semiconductor substrate 1 where no transistor is formed at substantially the same concentration as the first conductivity type impurity of the semiconductor substrate 1. As a result, at least the semiconductor substrate 1
It is characterized in that a high resistance buried layer 3 including a region having a lower carrier concentration is formed in advance.

However, the region of the high resistance buried layer 3 does not necessarily have to be adjacent to the transistor forming region, and may be formed only in the region where the parasitic capacitance is desired to be reduced. Also,
The conductivity type of the high-resistance buried layer 3 may be any of the first conductivity type and the second conductivity type, and may be formed in a multilayer structure including a plurality of layers of the first conductivity type layer and the second conductivity type layer. .

Next, as shown in FIG. 1B, an n ⁻ -type epitaxial layer 4 of the second conductivity type is grown on the entire surface to form a collector layer, and the transistor is isolated as shown in FIG. 1C. An insulating trench 5 as a region is formed to achieve insulation between the transistor forming region and the periphery including the high-resistance buried layer 3.
Subsequently, as shown in FIG. 1D, an n ⁺ -type collector extraction layer 6 is formed.

Thereafter, as shown in FIG.
Is grown on the entire surface to form a polysilicon resistor 9b which is a conductive thin film element as shown in FIG. The polysilicon resistor 9b is an element insulated from the semiconductor substrate via the oxide film 7, and includes a resistance element, an electrode of a capacitance element, an inductance element, and the like.

Further, a first interlayer insulating film 10 as shown in FIG. 2 (g) is formed, a contact hole 16 as shown in FIG. 2 (h) is opened, and as shown in FIG. An aluminum wiring 18 made of a suitable conductive film is formed.

As shown in FIG. 3, the bipolar type integrated circuit manufactured as described above has an n-type high integrated circuit in the semiconductor substrate 1 immediately below the polysilicon resistor 9b, which is a conductive thin film element, or immediately below the aluminum wiring 18, as shown in FIG. The structure is such that the resistance burying layer 3a is formed. However, in the embodiment of the present invention, it is not always necessary to include the polysilicon resistor 9b, and only the aluminum wiring 18 may be used.

Next, the operation of the present invention will be described. When the high-resistance buried layer 3 is formed of the same second conductivity type as the n ⁻ -type epitaxial layer 4 as shown in FIG. 3, the polysilicon base electrode 9a, which is a thin-film element, becomes the first conductivity type serving as a ground plane. A second conductive type semiconductor layer (conductance G) comprising an oxide film 7 (capacitance C _OX ), an n ⁻ -type epitaxial layer 4 and an n-type high-resistance buried layer 3 a is formed on the back surface of the semiconductor substrate 1.
_n , capacitance C _n ), n-type high resistance buried layer 3a-semiconductor substrate 1
The coupling is performed by the series impedance of the pn junction at the interface (capacitance C _j ) and the first conductivity type semiconductor substrate 1 (conductance G _p , capacitance C _p ).

Similarly, the aluminum wiring 18 includes an insulating film (capacitance C _OX ) composed of the first interlayer insulating film 10 and the oxide film 7, the n ⁻ -type epitaxial layer 4 and the n-type high-resistance buried layer 3a. Second conductivity type semiconductor layer (conductance G)
_n , capacitance C _n ), n-type high resistance buried layer 3a-semiconductor substrate 1
The coupling is performed by the series impedance of the pn junction at the interface (capacitance C _j ) and the first conductivity type semiconductor substrate 1 (conductance G _p , capacitance C _p ). FIG. 4 shows an equivalent circuit showing this impedance, which can be equivalently replaced with a series impedance of a resistance R _eff and a capacitance C _eff for a certain frequency.

Here, the second conductivity type n-type high resistance buried layer 3
The formation of a has the effect of lowering the conductance (G _n ) of the second conductivity type semiconductor layer because the thickness of the second conductivity type semiconductor layer is increased, and the carrier concentration thereof is lower than that of the semiconductor substrate 1. Therefore, even if the first conductivity type semiconductor substrate conductance (G _p ) is expected to increase due to the replacement of a part of the first conductivity type semiconductor substrate 1 with the second conductivity type n-type high resistance buried layer 3a, the whole Can be reduced.

Thus, the frequency at which the semiconductor region functions as a series capacitance between the thin film element and the substrate or between the wiring and the substrate is
Shift to lower frequency side. The carrier concentration of the second conductivity type n-type high-resistance buried layer 3a the n ^- be formed than the carrier concentration of the type epitaxial layer 4 lower, n ^- -type epitaxial layer 4 semiconductor pn junction between the substrate 1 The pn junction at the interface between the n-type high-resistance buried layer 3a and the semiconductor substrate 1 has a larger depletion layer spread toward the n-type high-resistance buried layer 3a than the pn junction, so that the junction capacitance (C _j ) is smaller. Become. Therefore, in a more practical frequency range, the equivalent parasitic capacitance C _eff of the thin film element and the wiring can be reduced.
This is advantageous for high-speed operation of the circuit.

On the other hand, when the high resistance buried layer 3 is formed of the same first conductivity type as the semiconductor substrate 1 as shown in FIG.
A polysilicon base electrode 9a, which is a thin film element, has an oxide film 7 on the back surface of the first conductivity type semiconductor substrate 1 serving as a ground plane.
(Capacitance C _OX ), second conductivity type n ⁻ -type epitaxial layer 4
(Conductance G _n , capacitance C _n ), pn junction (capacitance C _j ) at the interface of n ⁻ type epitaxial layer 4-p type high resistance buried layer 3b, and p type high resistance buried layer 3b and semiconductor substrate 1 First conductivity type semiconductor layer (conductance G _p , capacitance C
_p ) is coupled with the series impedance.

Similarly, the aluminum wiring is formed on the interlayer insulating film 1.
0 and an oxide film 7 (capacitance C _OX ), a second conductivity type n ⁻ -type epitaxial layer 4 (conductance G _n ,
Capacitance C _n ), pn junction (capacitance C _j ) at the interface of n ⁻ -type epitaxial layer 4-p-type high-resistance buried layer 3b, and first conductivity type semiconductor composed of p-type high-resistance buried layer 3b and semiconductor substrate 1 It is coupled with the series impedance of the layers (conductance G _p , capacitance C _p ). FIG. 7 shows an equivalent circuit showing this impedance, which can be equivalently replaced with a series impedance of a resistance R _eff and a capacitance C _eff for a certain frequency.

Here, since a part of the p-type silicon substrate 1 is replaced by the p-type high-resistance buried layer 3b having a low carrier concentration, the first conductivity type semiconductor layer conductance (G _p ).
Is smaller than the state where the p-type high resistance buried layer 3b is not formed. Thereby, the frequency at which the semiconductor layer functions as a series capacitance between the thin film element and the substrate or between the wiring and the substrate is
Shift to lower frequency side. Further, as compared with the pn junction between the n ⁻ epitaxial layer 4 and the p-type silicon substrate 1, n ⁻
-Type epitaxial layer 4-p type high resistance buried layer 3b
In the case of the n-junction, the depletion layer spreads more toward the p-type high-resistance buried layer 3b, so that the junction capacitance (C _j ) also decreases.
Therefore, also in this case, in a more practical frequency range, the equivalent parasitic capacitance C _eff of the thin film element or the wiring can be reduced, which is advantageous for the high-speed operation of the circuit. Since the p-type high-resistance buried layer 3b is not formed in the transistor formation region, the formation of the high-resistance buried layer 3 does not affect the transistor characteristics.

Next, a method of manufacturing a bipolar semiconductor integrated circuit as an embodiment of the present invention will be described in detail with reference to FIGS. First, as shown in FIG.
An n-type impurity is implanted into a region of the silicon substrate on the surface of the p-type silicon substrate 1 where no bipolar transistor is to be formed by ion implantation, and then thermally diffused to form a high-resistance buried layer 3 having a low carrier concentration. An n ⁺ -type buried layer 2 is formed by ion-implanting high-concentration n-type impurities into the transistor formation region. The ion implantation conditions and the thermal diffusion conditions when forming the high-resistance buried layer 3 are set so that the n-type impurity concentration after thermal diffusion is substantially the same as the p-type impurity added to the semiconductor substrate 1. By doing so, the buried layer has a high resistance.

Next, as shown in FIG. 1B, an n ⁻ type epitaxial layer 4 is grown on the entire surface to form a collector layer.
The conductivity type of the high-resistance buried layer 3 may be either p-type or n-type, but ion implantation conditions for n-type impurities are set so that the carrier concentration is lower than at least the semiconductor substrate 1. When the high-resistance buried layer 3 is of the n-type, it is better to set the ion implantation conditions of the n-type impurity so that the carrier concentration of the n ⁻ -type epitaxial layer 4 is also low.

Next, an insulating trench 5 as shown in FIG.
Insulation from surroundings including Subsequently, as shown in FIG. 1D, an n ⁺ -type collector extraction layer 6 for electrically extracting the n ⁺ -type buried layer 2 to the surface of the n ^-- type epitaxial layer 4 with low resistance is formed by ion implantation. Formed.

Thereafter, as shown in FIG. 1E, an oxide film 7 is grown on the entire surface, and a base contact 8 is opened in a region where a base and a graft base layer are to be formed. A polysilicon base electrode 9a as shown in FIG. 2F is formed so as to cover the base contact 8. At this time, a polysilicon resistor 9b is formed at the same time. FIG.
As shown in (g), after the entire surface is covered with the first interlayer insulating film 10, an emitter contact 11 is opened in the emitter formation region.

Further, as shown in FIG. 2H, a p ⁺ -type graft base layer 12 is formed using the polysilicon base electrode 9a as a diffusion source, and a p-type base layer 13 is formed by ion implantation. An emitter is formed by diffusing an n-type impurity on the extreme surface of the p-type base layer 13 covered with the emitter electrode 14. Further, the entire surface is covered with a second interlayer insulating film 1.
5, a contact hole 16 for electrical connection with the polysilicon base electrode 9a, the polysilicon emitter electrode 14, the n ⁺ -type collector lead-out layer 6, and the polysilicon resistor 9b is opened.

Then, as shown in FIG. 2 (i), the inside of the contact hole 16 is buried with a tungsten plug 17, and the elements are interconnected via an aluminum wiring 18 to complete an integrated circuit.

The polysilicon resistor 9b or the aluminum wiring 1 of the bipolar integrated circuit manufactured as described above is used.
8 has a structure as shown in FIG. 3 or FIG.

Next, the operation will be described in detail as a first embodiment in which the high resistance buried layer 3 is formed of the same n-type as the n ⁻ -type epitaxial layer 4 as shown in FIG.

In this case, the polysilicon resistor 9b is formed on the back surface of the p-type silicon substrate 1 serving as the ground plane, with respect to the oxide film 7 (capacitance C _OX ), the n ⁻ -type epitaxial layer 4, and the n-type high-resistance buried layer. 3a (conductance G)
_n , capacitance C _n ), the series impedance of the pn junction (capacitance C _j ) at the interface of the n-type high resistance buried layer 3a-p type silicon substrate 1 and the p-type silicon substrate 1 (conductance G _p , capacitance C _p ). Coupled.

Similarly, the aluminum wiring 18 comprises an insulating film (capacitance C _OX ) composed of the first interlayer insulating film 10, the second interlayer insulating film 15 and the oxide film 7, and the n ⁻ -type epitaxial layer 4. An n-type semiconductor layer (conductance G _n , capacitance C _n ) composed of an n-type high resistance buried layer 3a and a pn junction (capacitance C _j ) at the interface between the n-type high resistance buried layer 3a and the p-type silicon substrate 1 , And the p-type silicon substrate 1 (conductance G _p , capacitance C _p ). FIG. 4 shows an equivalent circuit showing this impedance, which can be equivalently replaced with a series impedance of a resistance R _eff and a capacitance C _eff for a certain frequency.

Here, the formation of the n-type high resistance buried layer 3a is performed by n
Increasing the thickness of the p-type silicon substrate 1 has an effect of lowering the conductance (G _n ) of the n-type semiconductor layer, and the carrier concentration thereof is lower than that of the p-type silicon substrate 1. Can be reduced even if the conductance (G _p ) of the p-type silicon substrate 1 is expected to increase due to the replacement of a part of the p-type silicon substrate 1 with the n-type high resistance buried layer 3a. As a result, the frequency at which the semiconductor region functions as a series capacitance between the polysilicon resistor 9b and the p-type silicon substrate 1 and between the aluminum wiring 18 and the p-type silicon substrate 1 shifts to a lower frequency side.

FIG. 5 shows a thickness of 300 μm and a specific resistance of 1Ω · c.
m on a p-type silicon substrate 1 having a depth of 3 μm and a specific resistance of 5Ω
to form an n-type high-resistance buried layer 3a of cm, thickness 1 [mu] m, n in the specific resistance 1 [Omega · cm ^- on the growth of the type epitaxial layer 4, through the silicon oxide film 7 having a thickness of 0.25 [mu] m 1
0 μm wide polysilicon resistor 9b and total thickness 1 μm
Each unit length when an aluminum wiring 18 having a width of 1 μm is formed via an oxide film 7 as an interlayer insulating film made of a silicon oxide film, and a first interlayer insulating film 10 and a second interlayer insulating film 15 6 is a graph comparing the frequency dependence of the equivalent parasitic capacitance C _eff in the case where the n-type high resistance buried layer 3a is formed and the case where it is not formed.

Although the equivalent parasitic capacitance C _eff tends to decrease on the high frequency side irrespective of the presence or absence of the n-type high-resistance buried layer 3a, the equivalent parasitic capacitance C _eff is lower than that of the prior art in which the n-type high-resistance buried layer 3a is not formed. In contrast, the formed invention is smaller for the same frequency. That is, the reduction rate of the parasitic capacitance of the aluminum wiring of 1 μm width according to the present invention is only 1% at 1 GHz, but 10% at 30 GHz and 18% at 80 GHz.
become. The parasitic capacitance reduction rate of the 10 μm-wide polysilicon resistor is 13% at 1 GHz, 34% at 30 GHz, and 50%.
37% at GHz.

The effect of reducing the capacitance at low frequencies is mainly due to the junction capacitance C
_{This is} a reduction effect of _{j, and} the reduction effect at high frequencies is due to a decrease in conductance. The frequency at which the parasitic capacitance of the 1 μm wide aluminum wiring is reduced by 10% with respect to the low frequency is n
48 GHz when there is no mold type high resistance buried layer 3a, n
When there is a mold high resistance buried layer 3a, the frequency is lowered to 24 GHz. The frequency at which the parasitic capacitance of the 10 μm-wide polysilicon resistor is reduced by 30% with respect to the low frequency is 34 GHz in the absence of the n-type high-resistance buried layer 3a, whereas the n-type high-resistance buried layer 3a is provided. In this case, the frequency becomes as low as 22 GHz.

As described above, according to the present embodiment, the effect of reducing the parasitic capacitance of the polysilicon resistor 9b and the aluminum wiring 18 can be obtained at a lower frequency, so that the load on the high-speed operation circuit is reduced. There is an advantage that high-frequency operation can be designed, and if the frequency is the same, design with lower power consumption becomes possible.

Next, a case where the high resistance buried layer 3 is formed of the same p-type as the p-type silicon substrate 1 as shown in FIG. 6 will be described as a second embodiment. In this case, the polysilicon resistor 9b is provided between the oxide film 7 (capacitance C _OX ) and the n ⁻ -type epitaxial layer 4 on the back surface of the p-type silicon substrate 1 serving as a ground plane.
(Conductance G _n , capacitance C _n ), pn junction (capacitance C _j ) at the interface of n ⁻ -type epitaxial layer 4-p-type high-resistance buried layer 3b, and p-type high-resistance buried layer 3b and p-type silicon substrate 1 P-type semiconductor layer (conductance G _p , capacitance C
_p ) is coupled with the series impedance.

Similarly, the aluminum wiring 18 comprises an insulating film (capacitance C _OX ) composed of the first interlayer insulating film 10, the second interlayer insulating film 15, the oxide film 7, and the n ⁻ -type epitaxial layer 4. (Conductance G _n , capacitance C _n ), pn junction (capacitance C _j ) at the interface of n ⁻ -type epitaxial layer 4-p-type high-resistance buried layer 3b, and p-type high-resistance buried layer 3b and p-type silicon substrate 1 Are coupled by the series impedance of a p-type semiconductor layer (conductance G _p , capacitance C _p ) composed of An equivalent circuit showing this impedance is as shown in FIG.
It can be considered that a certain frequency is equivalently replaced with the series impedance of the resistance R _eff and the capacitance C _eff .

Here, since a part of the p-type silicon substrate 1 is replaced by the p-type high-resistance buried layer 3b having a low carrier concentration, the conductance (G _p ) of the p-type semiconductor layer becomes
The size is smaller than when the p-type high resistance buried layer 3b is not formed. As a result, the semiconductor layer becomes the polysilicon resistor 9.
The frequency functioning as a series capacitance between the bp silicon substrate 1 and between the aluminum wiring 18 and the p silicon substrate 1 shifts to a lower frequency side.

FIG. 8 shows a thickness of 300 μm and a specific resistance of 1Ω · c.
m on a p-type silicon substrate 1 having a depth of 3 μm and a specific resistance of 5Ω
cm p-type high-resistance buried layer 3b, an n ⁻ -type epitaxial layer 4 having a thickness of 1 μm and a specific resistance of 1 Ω · cm is grown, and a silicon oxide film 7 having a thickness of 0.25 μm is interposed.
0 μm wide polysilicon resistor 9b and total thickness 1 μm
Equivalent to each unit length when an aluminum wiring 18 having a width of 1 μm is formed via an oxide film 7 made of a silicon oxide film, a first interlayer insulating film 10 and a second interlayer insulating film 15. 9 is a graph comparing the frequency dependence of the parasitic capacitance C _eff with and without the p-type high-resistance buried layer 3b.

As in the first embodiment, the equivalent parasitic capacitance C _eff tends to decrease on the high frequency side regardless of the presence or absence of the p-type high resistance buried layer 3b. In contrast to the prior art where no is formed, the formed invention is smaller for the same frequency. That is, 1
The reduction rate of the parasitic capacitance of the μm-wide aluminum wiring according to the present invention is as follows.
Only 1% at 1GHz, but 10% at 30GHz,
It becomes 20% at 80 GHz.

The parasitic capacitance reduction rate of a 10 μm-wide polysilicon resistor is 13% at 1 GHz, 29% at 30 GHz,
It becomes 38% at 70 GHz. That is, the n-type high-resistance buried layer 3a is formed at a frequency at which the parasitic capacitance of the 1 μm-wide aluminum wiring is reduced by 10% with respect to the low frequency, compared to 50 GHz when the n-type high-resistance buried layer 3a is not provided. 30
GHz. The frequency at which the parasitic capacitance of the 10 μm-wide polysilicon resistor is reduced by 30% with respect to the low frequency is 34 GHz when the n-type high-resistance buried layer 3a is not provided, whereas the n-type high-resistance buried layer 3a is formed. 24G by doing
Hz.

As described above, in the second embodiment, almost the same effect as in the first embodiment can be obtained. Therefore, it is not necessary to limit the high-resistance buried layer to either the p-type or the n-type. It is important that the resistance is high and the conductance is reduced. In other words, as a method of forming the high-resistance buried layer, a carrier of the substrate is neutralized by adding an impurity of a conductivity type opposite to that of the substrate under the condition that the concentration is substantially the same as that of the impurity of the substrate. It is desirable to form them as close to each other. Since the high resistance buried layer 3 is not formed in the transistor formation region, the formation of the high resistance buried layer has no effect on the transistor characteristics.

Next, another embodiment of the present invention will be described.
As a method for forming the high-resistance buried layer 3, it is preferable to add an impurity of the conductivity type opposite to that of the substrate under conditions that result in substantially the same concentration as the impurity of the substrate. Although it is difficult to form a high-resistance layer with a uniform concentration distribution due to the restrictions of the impurity pull file, a certain degree of uniformity can be obtained by adding a heat treatment.

For example, boron having a specific resistance of 1 Ω · cm
In the case of a silicon substrate, boron is distributed almost uniformly at a concentration of about 2 × 10 ¹⁶ cm ⁻³ . When a high-resistance buried layer having a depth of about 3 μm is formed by ion implantation of phosphorus, about 2 × 10 ¹² cm ^{−2 is} implanted at an accelerating voltage of about 1 MeV and then at 1200 ° C. for about 1 to 2 hours. It can be formed by performing heat treatment.

However, even in this case, the concentration of phosphorus is not completely uniform, and the vicinity of the center of the high resistance layer is higher than the boron concentration, and the deeper side and the surface side are lower than the boron concentration. The layer has a pnp structure. However, since the p-type layer in the high-resistance layer has a lower carrier concentration than the substrate, the effect of lowering the conductance of the entire semiconductor region unless the n-type layer of the high-resistance layer has a significantly higher carrier concentration with respect to the substrate. It is possible to get

[0062]

As is clear from the above description, the first effect of the present invention is that the conductance of the high resistance buried layer portion is reduced, and the frequency at which this region can be regarded as a capacitance is reduced, so that the lower effect is obtained. At a frequency, the high resistance buried layer functions as a series capacitance, and the equivalent parasitic capacitance of the wiring and the thin film element is reduced.

The second effect of the present invention is that the depletion layer of the pn junction expands to the high resistance buried layer side by forming the high resistance layer having a low carrier concentration, so that the junction capacitance of the substrate is reduced and the wiring is reduced. And the parasitic capacitance of the thin film element is reduced.

The third effect of the present invention is that the high resistance buried layer is not formed in the transistor forming region, so that the first and second effects can be obtained without affecting the transistor characteristics. That is.

Further, a fourth effect of the present invention is that an impurity of a conductivity type opposite to that of the substrate is implanted into the substrate by ion implantation to neutralize the carrier of the substrate and form a high-resistance buried layer. Therefore, the first and second effects can be easily obtained without adding a complicated process.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a semiconductor chip arranged in the order of manufacturing steps of a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a longitudinal sectional view of the semiconductor chips arranged in the order of the manufacturing process of the semiconductor device according to the embodiment of the present invention.

FIG. 3 is a longitudinal sectional view of a polysilicon resistance section for explaining the first embodiment.

FIG. 4 is an equivalent circuit diagram showing impedance between a polysilicon resistor and a back surface of a silicon substrate or between an aluminum wiring back surface and a back surface of a silicon substrate for explaining the first embodiment;

FIG. 5 is a graph showing the frequency dependence of the equivalent capacitance between the back surface of the polysilicon resistor and the back surface of the silicon substrate and between the back surface of the aluminum wiring and the back surface of the silicon substrate for explaining the effect of the first embodiment.

FIG. 6 is a cross-sectional view of a polysilicon resistor for explaining a second embodiment.

FIG. 7 illustrates a polysilicon resistor back surface-a silicon substrate back surface or an aluminum wiring back surface for explaining the second embodiment;
FIG. 3 is an equivalent circuit diagram illustrating impedance between the back surfaces of the silicon substrates.

FIG. 8 is a graph showing the frequency dependence of the equivalent capacitance between the back surface of the polysilicon resistor and the back surface of the silicon substrate and the back surface of the aluminum wiring and the back surface of the silicon substrate for explaining the effect of the second embodiment.

FIG. 9 is a longitudinal sectional view of a semiconductor chip arranged in the order of manufacturing steps of a conventional semiconductor device.

FIG. 10 is a longitudinal sectional view of a semiconductor chip arranged in the order of manufacturing steps of a conventional semiconductor device.

FIG. 11 is a longitudinal sectional view of a polysilicon resistance portion for explaining a conventional example.

FIG. 12 shows a polysilicon resistor for explaining a conventional example.
It is an equivalent circuit diagram showing impedance between the silicon substrate back surface or between the aluminum wiring back surface and the silicon substrate back surface.

[Explanation of symbols]

Reference Signs List 1 p-type silicon substrate (first conductivity type semiconductor substrate) 2 n ⁺ type buried layer (second conductivity type buried layer) 3 high resistance buried layer 3 a n-type high resistance buried layer (second conductivity type buried layer) 3b p-type high resistance buried layer (first conductivity type buried layer) 4 n ⁻ -type epitaxial layer (second conductivity type epitaxial layer) 5 insulating trench (insulation isolation region) 6 n ⁺ -type collector lead-out layer 7 oxidation Film (insulating film) 8 base contact 9a polysilicon base electrode 9b polysilicon resistance (thin film element) 10 first interlayer insulating film (interlayer insulating film) 11 emitter contact 12 p ⁺ type graft base layer 13 p type base layer 14 poly Silicon emitter electrode 15 Second interlayer insulating film 16 Contact hole 17 Tungsten plug 18 Aluminum wiring

Claims (9)

[Claims] 1. A semiconductor device comprising a bipolar semiconductor integrated circuit, wherein a first conductive type impurity or a second conductive type impurity is added at a low concentration to a region on a surface of a first conductive type semiconductor substrate where no bipolar transistor is formed. A semiconductor device provided with a resistance burying layer. 2. The semiconductor device according to claim 1, wherein a semiconductor layer having a carrier concentration lower than at least said first conductivity type semiconductor substrate is formed in said high-resistance buried layer. 3. The semiconductor device according to claim 1, wherein a penetration depth of said high resistance buried layer into said first conductivity type semiconductor substrate is 3 μm or more. 4. The semiconductor device according to claim 1, wherein said high resistance buried layer comprises two or more semiconductor layers of different conductivity types. 5. A step of forming a first semiconductor region serving as a high-resistance buried layer doped with a second conductive type impurity at a low concentration in a region where a bipolar transistor is not formed on the surface of the first conductive type semiconductor substrate; Forming a second semiconductor region serving as a collector buried layer by adding a second conductive type impurity at a high concentration to a region of the surface of the first conductive type semiconductor substrate where a bipolar transistor is to be formed; Growing a two-conductivity-type epitaxial layer; and reaching the first-conductivity-type semiconductor substrate from the surface of the epitaxial layer separating the first semiconductor region and the second semiconductor region; Forming a deeper isolation region, growing an insulating film on the surface of the epitaxial layer, and forming a thin film element or a wiring on the insulating film. The method of manufacturing a semiconductor device, characterized in that. 6. The method of manufacturing a semiconductor device according to claim 5, wherein a semiconductor layer having a carrier concentration lower than at least the first conductivity type semiconductor substrate is formed in the high resistance buried layer. 7. The method of manufacturing a semiconductor device according to claim 5, wherein the depth of penetration of the high resistance buried layer into the semiconductor substrate is 3 μm or more. 8. The method for manufacturing a semiconductor device according to claim 5, wherein the high-resistance buried layer is formed by adding the second conductivity type impurity by an ion implantation method and then thermally diffusing the impurity. 9. The method according to claim 5, wherein the high-resistance buried layer comprises two or more semiconductor layers of different conductivity types.