JPH11307578A - Bonding method of bump and electronic component - Google Patents

Bonding method of bump and electronic component

Info

Publication number
JPH11307578A
JPH11307578A JP10115316A JP11531698A JPH11307578A JP H11307578 A JPH11307578 A JP H11307578A JP 10115316 A JP10115316 A JP 10115316A JP 11531698 A JP11531698 A JP 11531698A JP H11307578 A JPH11307578 A JP H11307578A
Authority
JP
Japan
Prior art keywords
bumps
bump
flat
electronic component
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10115316A
Other languages
Japanese (ja)
Other versions
JP3752836B2 (en
Inventor
Yoshitaka Fujita
義高 藤田
Satoshi Suzuki
聡 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP11531698A priority Critical patent/JP3752836B2/en
Publication of JPH11307578A publication Critical patent/JPH11307578A/en
Application granted granted Critical
Publication of JP3752836B2 publication Critical patent/JP3752836B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To exclude that a part of bumps can not contribute to connection, by forming a plurality of bumps on the flat outer surface of an electronic component which bumps have flat tip surfaces almost parallel to the outer surface and almost the same height. SOLUTION: Bumps formed on an LSI 10 are pressed against the upper surface of a forming board by applying a specified load to each of the LSI 10, and forming bumps 11a are formed. In this case, pressing is so performed that the upper surface of the forming board and the surface of the LSI 10 become parallel to each other. The forming bumps 11a nave sufficiently flat end surfaces almost equal in height. The LSI 10 is connected with, e.g. a glass substrate 13 of a liquid crystal display panel by COG system. As the result, all the bump 11a are brought closely into contact with facing ITO electrodes 14 in the same state. Thereby it can be excluded that a part of bumps can not contribute to connection.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バンプ及びそのバ
ンプを用いた電子部品のボンディング方法に関する。
The present invention relates to a bump and a method for bonding an electronic component using the bump.

【0002】[0002]

【従来の技術】近年、電子製品において、大規模集積回
路(以下、LSIという)等の電子部品を、その電子製
品を構成するその他の部品の電極と接続する場合、LS
I等にバンプを形成し、該バンプを介して、接続する方
法が多く用いられている。例えば、バンプを利用した接
続方法の1つである、COG(Chip On Glass)方式で
LSIと液晶表示パネルとを接続する様子を図8及び図
9に示した。図8及び図9において、同一の部材につい
ては、同符号を付している。これらの図において、ガラ
ス基板1の上部に形成されているITO電極2、2…
と、LSI3に形成されているバンプ4、4…は、導電
性フィラー5、5…を樹脂に分散させてなる異方性導電
膜(Anisotoropic Conductive Film)6を介して電気的
に接続されている。
2. Description of the Related Art In recent years, in electronic products, when an electronic component such as a large-scale integrated circuit (hereinafter referred to as LSI) is connected to electrodes of other components constituting the electronic product, LS
A method of forming a bump on an I or the like and connecting via the bump is often used. For example, FIGS. 8 and 9 show a state in which an LSI and a liquid crystal display panel are connected by a COG (Chip On Glass) method, which is one of the connection methods using bumps. 8 and 9, the same members are denoted by the same reference numerals. In these figures, ITO electrodes 2, 2,.
And the bumps 4, 4,... Formed on the LSI 3 are electrically connected via an anisotropic conductive film (Anisotoropic Conductive Film) 6 in which conductive fillers 5, 5,. .

【0003】[0003]

【発明が解決しようとする課題】しかしながら、図8に
示すように、他のバンプ4…と比較して高さが不足して
いるバンプ4aや、図9に示すように、表面の凹凸が大
きいバンプ4bがあると、その部分においては、それら
のバンプと対向するITO電極2との間隔が導電性フィ
ラー5…の粒径より大きくなってしまうので、電気的に
接続されなくなってしまう。この課題を解決するため
に、導電性フィラー5…の粒径を大きくする方法も考え
られるが、導電性フィラー5…の直径を大きくすると、
隣接するバンプ間でのショートが発生し易くなり、その
ためにバンプ間のピッチを大きくしなければならず、高
密度実装には適さない。
However, as shown in FIG. 8, as shown in FIG. 8, bumps 4a whose height is insufficient as compared with other bumps 4,..., And as shown in FIG. If the bumps 4b are present, the space between the bumps and the ITO electrode 2 facing the bumps 4b becomes larger than the particle size of the conductive fillers 5, so that the bumps 4b are not electrically connected. To solve this problem, a method of enlarging the particle size of the conductive fillers 5 is also conceivable. However, if the diameter of the conductive fillers 5 is increased,
Short-circuiting between adjacent bumps is likely to occur, and therefore the pitch between the bumps must be increased, which is not suitable for high-density mounting.

【0004】さらに、上記のような異方性導電膜を用い
るCOG方式に限らず、TAB(Tape Automated Bondi
ng)方式で、フィルムフャリアのインナリード電極とL
SIを、半田接続する場合においても、LSI側の各バ
ンプが均一な高さや平坦な面を有していないと、接続不
良が生じることがあった。
Further, the present invention is not limited to the COG method using an anisotropic conductive film as described above.
ng) method, the film lead inner lead electrode and L
Even when the SI is connected by soldering, a connection failure may occur if the bumps on the LSI side do not have a uniform height or a flat surface.

【0005】上記の問題点に鑑み、本発明は、良好な接
続状態を得ることができ、高密度実装にも適しているバ
ンプ、及びそのようなバンプが得られるバンプの形成方
法、さらには、本発明のバンプを利用して、確実に電気
的な接続が得られるボンディング方法を提供することを
目的とする。
[0005] In view of the above problems, the present invention provides a bump capable of obtaining a good connection state and suitable for high-density mounting, a method of forming a bump capable of obtaining such a bump, and a method of forming a bump. An object of the present invention is to provide a bonding method capable of reliably obtaining an electrical connection by using the bump of the present invention.

【0006】[0006]

【課題を解決するための手段】以上の課題を解決すべ
く、本発明の請求項1に記載の発明は、電子部品の平坦
な外面に、複数、形成されていて、前記電子部品と電気
的に接続されているバンプであって、前記外面に対して
ほぼ平行で平坦な先端面をそれぞれ有していて、かつ、
互いにほぼ同じ高さであることを特徴とする。
In order to solve the above-mentioned problems, the invention according to claim 1 of the present invention comprises a plurality of electronic components formed on a flat outer surface to electrically connect with the electronic components. Are connected to the bumps, each having a flat tip surface substantially parallel to the outer surface, and
It is characterized in that they have substantially the same height.

【0007】請求項1に記載のバンプによれば、電子部
品の平坦な外面に形成されている複数のバンプが、その
外面に対してほぼ平行する、平坦な端面をそれぞれ有し
ていて、かつ、それらバンプが同じ高さであることか
ら、この電子部品を、他の部品と、これらバンプを介し
て接続する際に、全てのバンプが、前記他の部品の電極
に対して、同じ状態で密着することができ、一部のバン
プが接続に寄与できないといったことが生じることがな
く、電子部品全体として、良好な接続状態が得られる。
また、バンプと、他の部品の電極とを導電性粒子を介在
させて、接続するような場合にも、導電性粒子の粒径等
に関係なく良好な状態で接続することができることか
ら、バンプ間のピッチを大きくしなくてもよく、高密度
実装にも適したバンプとなる。
According to the first aspect of the present invention, the plurality of bumps formed on the flat outer surface of the electronic component have flat end faces substantially parallel to the outer surface, respectively, and Since these bumps have the same height, when this electronic component is connected to other components via these bumps, all the bumps are in the same state with respect to the electrodes of the other components. Adhesion can be made, and there is no occurrence that some of the bumps cannot contribute to the connection, and a good connection state can be obtained as the entire electronic component.
In addition, even in the case where the bump and the electrode of another component are connected with conductive particles interposed therebetween, the bump can be connected in a good state regardless of the particle size of the conductive particle. It is not necessary to increase the pitch between the bumps, and the bump is suitable for high-density mounting.

【0008】ここで、電子部品とは、バンプが形成され
得る外面を有し、バンプを介して電気的に他の部品等と
接続され得るものであればよく、例えば、大規模集積回
路(LSI)等が挙げられる。また、バンプは、一般的
にバンプ材料として用いられているものからなり、たと
えば、金、銅、あるいは、半田からなる。
Here, the electronic component may have any outer surface on which a bump can be formed and can be electrically connected to another component or the like via the bump. For example, a large-scale integrated circuit (LSI) ) And the like. The bump is made of a material generally used as a bump material, for example, gold, copper, or solder.

【0009】請求項2に記載の発明は、請求項1に記載
のバンプにおいて、前記平坦な先端面は、平坦面に凸部
または凹部のいずれか一方が、均等に形成された実質的
に平坦な先端面であることを特徴とする。
According to a second aspect of the present invention, in the bump according to the first aspect, the flat tip surface is substantially flat in which either a convex portion or a concave portion is uniformly formed on the flat surface. It is characterized by a simple tip surface.

【0010】請求項2に記載のバンプによれば、請求項
1の効果に加えて、さらに、平坦面に、凸部または凹部
が均等に形成されていることから、より一層、強固な状
態で接続できるバンプとなる。具体的には、例えば、異
方性導電膜を用い、この異方性導電膜中の導電性粒子を
介して、バンプと他の部品の電極とを間接的に接続する
場合、凸部によって形成される凹所や、凹部に導電性粒
子がはまることで、個々の導電性粒子が固定され、より
確実に接続される。また、バンプと、他の部品の電極
を、直接接続するような場合、凸部や、凹部によって区
切られる凸状の部分が、その電極に、食い込むような状
態になり、より確実に接続される。
According to the second aspect of the invention, in addition to the effect of the first aspect, since the convex portions or the concave portions are formed evenly on the flat surface, the bumps can be further strengthened. It becomes a bump that can be connected. Specifically, for example, when using an anisotropic conductive film and indirectly connecting a bump and an electrode of another component via conductive particles in the anisotropic conductive film, the bump is formed by a convex portion. When the conductive particles fit into the recesses or the recesses to be formed, the individual conductive particles are fixed and connected more reliably. In the case where the bump and the electrode of another component are directly connected, the convex portion or the convex portion separated by the concave portion is in a state where the electrode bites into the electrode and is more reliably connected. .

【0011】ここで、凸部としては、例えば、直線状あ
るいは曲線状の突条や、突起が挙げられ、また、凹部と
しては、例えば、直線状あるいは曲線状の溝や、窪みな
どが挙げられる。さらに、凸部や凹部は、前記端面に局
所的に形成されるものではなく、端面にほぼ一様に形成
されることが好ましい。具体的には、格子状や、うずま
き状に形成するといったことが挙げられる。
Here, examples of the protruding portion include linear or curved ridges and projections, and examples of the recessed portion include linear or curved grooves and depressions. . Further, it is preferable that the convex portions and the concave portions are not formed locally on the end face, but are formed almost uniformly on the end face. Specifically, it may be formed in a lattice shape or a spiral shape.

【0012】また、凸部や凹部の大きさや形状は、バン
プと他の部品の電極との具体的な接続方法により適宜変
更すればよい。例えば、パンプを、他の部品の電極と、
異方性導電膜の導電性粒子を用いて接続する場合、凸部
によって形成される凹所や、凹部に導電性粒子が入り込
んだ場合に、導電性粒子が、バンプと前記電極の双方に
接触できるような、大きさ、形状である。また、バンプ
を、前記電極と直接接続するような場合には、凸部や、
凹部によって区切られる凸状の部分が、電極を傷つけず
に食い込むことができ、かつ、必要とされる接触面積が
得られるような、幅のある形状である。
The size and shape of the projections and depressions may be appropriately changed according to the specific connection method between the bumps and the electrodes of other components. For example, the pump is connected to the electrodes of other parts,
When the connection is made using conductive particles of an anisotropic conductive film, the conductive particles come into contact with both the bump and the electrode when the conductive particles enter the recess formed by the convex portion or the concave portion. The size and shape as possible. In the case where the bump is directly connected to the electrode, a convex portion,
The convex portion separated by the concave portion has a wide shape so that the electrode can bite without damaging the electrode and a required contact area can be obtained.

【0013】請求項3に記載の発明は、電子部品を該電
子部品の平坦な外面に形成されている複数のバンプを介
して他の部品に導通可能に接続するための電子部品のボ
ンディング方法であって、平坦な成形面を備えた成形台
を準備し、前記電子部品の前記外面が前記成形面に平行
な状態を保ちつつ複数の前記バンプ先端面を前記成形面
に押し当てて平坦な面に成形し、この後、前記電子部品
の外面と前記他の部品の電極の表面とがほぼ平行な状態
で、前記複数のバンプと前記電極とを導通可能に接続す
ることを特徴とする。
According to a third aspect of the present invention, there is provided an electronic component bonding method for connecting an electronic component to another component in a conductive manner through a plurality of bumps formed on a flat outer surface of the electronic component. A molding table having a flat molding surface is prepared, and a plurality of bump tip surfaces are pressed against the molding surface while the outer surface of the electronic component is kept parallel to the molding surface to form a flat surface. Then, the plurality of bumps and the electrodes are electrically connected to each other in a state where the outer surface of the electronic component and the surface of the electrode of the other component are substantially parallel to each other.

【0014】請求項3に記載の電子部品のボンディング
方法によれば、平坦なバンプ先端面を容易に形成して信
頼性の高い導通接続を安定的に得ることができる。
According to the electronic component bonding method of the present invention, a flat bump tip surface can be easily formed, and a highly reliable conductive connection can be stably obtained.

【0015】ここで、電子部品と接続される他の部品と
は、例えば、電子部品であるLSIによって駆動される
液晶表示パネルのガラス基板であって、電極とは該ガラ
ス基板に形成されるITOなどの透明電極である。ま
た、TAB方式で接続する場合、他の部品としてはフィ
ルムキャリアテープであり、電極は、フィルムキャリア
テープのインナリードである。
Here, the other component connected to the electronic component is, for example, a glass substrate of a liquid crystal display panel driven by an LSI which is an electronic component, and the electrodes are ITO formed on the glass substrate. And the like. When the connection is made by the TAB method, the other components are a film carrier tape, and the electrodes are inner leads of the film carrier tape.

【0016】[0016]

【発明の実施の形態】以下、本発明について図面を参照
して説明する。 (第1の実施の形態)本発明のバンプの形成方法の一例
を、図1〜図3に示した。これらの図において、10は
LSI(大規模集積回路)、12はフォーミング板、1
3はLCDパネルのガラス基板である。
DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below with reference to the drawings. (First Embodiment) An example of a method for forming a bump according to the present invention is shown in FIGS. In these figures, 10 is an LSI (large-scale integrated circuit), 12 is a forming plate, 1
3 is a glass substrate of the LCD panel.

【0017】まず、電子部品であるLSI10の平坦な
表面(外面)10aに、従来用いられているバンプの形
成方法を用いて、バンプを形成する。具体的には、表面
10aに、チタンやクロム等からなる第1の金属層、タ
ングステン、プラチナ、銀等からなる第2の金属層を形
成し、これら金属層からなるバリアメタル層を形成す
る。次に、バリアメタル層上に、電解めっき法により、
金(Au)からなるバンプ11、11、11を形成す
る。バンプ11…は、LSI10内部の図示しない回路
と電気的に通じるような位置に形成される。バンプ1
1、11、11は、図1に示すように、高さが揃ってい
なかったり、また、端面18…に凹凸が形成されてい
る。
First, bumps are formed on a flat surface (outer surface) 10a of an LSI 10, which is an electronic component, by using a conventional bump forming method. Specifically, a first metal layer made of titanium, chromium, or the like, a second metal layer made of tungsten, platinum, silver, or the like is formed on the surface 10a, and a barrier metal layer made of these metal layers is formed. Next, on the barrier metal layer, by electrolytic plating,
The bumps 11, 11, 11 made of gold (Au) are formed. The bumps 11 are formed at positions that are electrically connected to a circuit (not shown) inside the LSI 10. Bump 1
As shown in FIG. 1, 1, 11, 11 are not uniform in height, and the end faces 18 are formed with irregularities.

【0018】次に、フォーミング板12(板部材)を用
意する。該フォーミング板12は、金より硬質の金属か
らなる、一定の厚さを有する平板で、十分な平坦度を有
するよう、加工されたものである。このフォーミング板
12の上面に対して、LSI10上に形成されたバンプ
11、11、11を、LSI10ごと、所定の大きさの
荷重をかけて、押し付ける(図1の矢印方向)。この場
合、フォーミング板12の上面と、LSI10の表面1
0aが、互いに平行であるような状態で、押し付け、ま
た、この際、必要に応じて、加熱する。その後、フォー
ミング板12とLSI10とを離すと、図2に示すよう
な、成形し直された、フォーミングバンプ11a、11
a、11aが得られる。これらフォーミングバンプ11
a…は、それぞれの高さがほぼ等しく、また、端面18
…にあった凹凸等もフォーミング板12の平坦な表面
に、押しつぶされることによって、ならされ、十分に平
坦な端面18a…となっている。
Next, a forming plate 12 (plate member) is prepared. The forming plate 12 is a flat plate made of a metal harder than gold and having a certain thickness, which is processed to have a sufficient flatness. The bumps 11, 11, and 11 formed on the LSI 10 are pressed against the upper surface of the forming plate 12 by applying a predetermined load to the entire LSI 10 (in the direction of the arrow in FIG. 1). In this case, the upper surface of the forming plate 12 and the upper surface 1 of the LSI 10
0a are pressed in a state where they are parallel to each other, and at this time, if necessary, heating is performed. Thereafter, when the forming plate 12 and the LSI 10 are separated from each other, as shown in FIG.
a and 11a are obtained. These forming bumps 11
a... have substantially the same height and the end faces 18
Are flattened by being crushed on the flat surface of the forming plate 12 to form sufficiently flat end faces 18a.

【0019】次に、図2のLSI10と、液晶表示パネ
ルのガラス基板(他の部品)13とをCOG方式によっ
て接続する。ガラス基板13上にはITO(Indium Tin
Oxide)電極14、14、14が形成されていて、IT
O電極14…は、表面が十分に平坦で、互いにほぼ同じ
高さを有する(図3)。これらITO電極14、14、
14上に、導電性フィラー(導電性粒子)16が樹脂1
5に分散されてなる異方性導電膜(導電部材)17を載
置する。
Next, the LSI 10 of FIG. 2 and a glass substrate (other components) 13 of the liquid crystal display panel are connected by the COG method. On the glass substrate 13, ITO (Indium Tin)
Oxide) The electrodes 14, 14, 14 are formed and the IT
The O-electrodes 14 have a sufficiently flat surface and substantially the same height as each other (FIG. 3). These ITO electrodes 14, 14,
The conductive filler (conductive particles) 16 is formed on the resin 1
The anisotropic conductive film (conductive member) 17 dispersed in Step 5 is placed.

【0020】異方性導電膜17に含有される導電性フィ
ラー16は、ニッケル等の金属粒子、カーボン粒子、金
属膜が被覆されたプラスチック粒子等であって、粒径が
10ミクロン程度である。これら導電性フィラー16を
分散させた状態で保持するバインダー樹脂は、接着性を
有する樹脂で、例えば、ポリエチレン系などの熱可塑性
樹脂、エポキシ系などの熱硬化性樹脂などである。さら
に、異方性導電膜17は、必要に応じて、シリカなどの
分散剤を含有していてもよい。
The conductive filler 16 contained in the anisotropic conductive film 17 is a metal particle such as nickel, a carbon particle, a plastic particle coated with a metal film, or the like, and has a particle size of about 10 μm. The binder resin that holds the conductive filler 16 in a dispersed state is a resin having an adhesive property, such as a thermoplastic resin such as a polyethylene resin or a thermosetting resin such as an epoxy resin. Further, the anisotropic conductive film 17 may contain a dispersing agent such as silica, if necessary.

【0021】次に、異方性導電膜17の上から、図2の
個々のフォーミングバンプ11a…が、ITO電極14
…のそれぞれに対応する位置に来るように、LSI10
の位置合わせを行い、位置が定まったところで、LSI
10を、その上から、図示しないボンディングツールに
よって、所定の条件下、加熱加圧する。加熱加圧を始め
てから、所定時間経過後、前記ボンディングツールを取
り外すと、図3に示すように、フォーミングバンプ11
a…と、ITO電極14…が、異方性導電膜17中の導
電性フィラー16、16…を介して接続される。
Next, the individual forming bumps 11a shown in FIG.
, So as to come to the position corresponding to each of
When the position is determined, the LSI
10 is heated and pressed from above by a bonding tool (not shown) under predetermined conditions. After the elapse of a predetermined time from the start of the heating and pressurization, when the bonding tool is removed, as shown in FIG.
and the ITO electrodes 14 are connected via conductive fillers 16 in the anisotropic conductive film 17.

【0022】以上の本発明のフォーミングバンプ11
a、11a、11aによれば、それぞれの高さがほぼ同
じであって、十分に平坦な端面18a…を有することか
ら、平坦で均一な高さを有するガラス電極14、14、
14と接続する際に、全てのフォーミングバンプ11a
は、対向するガラス電極14と、同じ状態で密着するこ
とができ、LSI10とガラス基板13は、良好な接続
状態になり、電気的に確実に接続される。
The above-described forming bump 11 of the present invention
According to a, 11a, and 11a, since the heights are almost the same and the end surfaces 18a are sufficiently flat, the glass electrodes 14, 14, having flat and uniform heights are provided.
14 and all the forming bumps 11a
Can be brought into close contact with the opposing glass electrode 14 in the same state, and the LSI 10 and the glass substrate 13 are in a good connection state, and are reliably connected electrically.

【0023】(第2の実施の形態)本発明のバンプの形
成方法の他の例を、図4〜図7に示した。これらの図に
おいて、20はLSI、22はフォーミング板である。
LCDパネルのガラス基板、ITO電極、異方性導電膜
等については、第1の実施の形態と同じ符号を付してい
る。まず、LSI20の平坦な表面(外面)20aに、
第1の実施の形態と同様に、バンプ21、21、21を
形成する。バンプ21…は、LSI20内部の図示しな
い回路と電気的に通じる位置に形成される。また、バン
プ21…は、図4に示すように、高さが揃っていなかっ
たり、端面28…に凹凸が形成されている。
(Second Embodiment) Another example of the bump forming method of the present invention is shown in FIGS. In these figures, 20 is an LSI and 22 is a forming plate.
The same reference numerals as in the first embodiment denote the glass substrate, the ITO electrode, the anisotropic conductive film, and the like of the LCD panel. First, on the flat surface (outer surface) 20a of the LSI 20,
The bumps 21, 21, 21 are formed as in the first embodiment. The bumps 21 are formed at positions electrically connected to a circuit (not shown) inside the LSI 20. Further, as shown in FIG. 4, the bumps 21 are not uniform in height or have bumps on the end faces 28.

【0024】次に、フォーミング板(板部材)22を用
意する。該フォーミング板22は、金より硬質の金属か
らなる平板で、図7に示すように、上面の全面には、突
条22a、22a…が、縦横に格子状に形成されてい
る。これら突条22a…は、全て同じ高さであって、断
面形状が、略三角形で、その幅が後述の導電性フィラー
16…の粒径と同程度であるように、形成されている。
また、前記突条22a…以外の、フォーミング板22の
上面を形成する、主たる面は、十分な平坦度を有するよ
う、加工されている。
Next, a forming plate (plate member) 22 is prepared. The forming plate 22 is a flat plate made of a metal harder than gold. As shown in FIG. 7, ridges 22a, 22a... The protruding ridges 22a are all the same height, have a substantially triangular cross-sectional shape, and are formed such that their widths are substantially the same as the particle size of the conductive fillers 16 described below.
Besides, the main surface forming the upper surface of the forming plate 22 other than the protrusions 22a is processed so as to have a sufficient flatness.

【0025】このフォーミング板22の上面に対して、
LSI20上に形成されたバンプ21、21、21を、
LSI20ごと、第1の実施の形態と同様に、押し付け
る(図4の矢印方向)。この場合、フォーミング板22
の上面の主たる面と、LSI20の表面20aが、互い
に平行であるような状態で、押し付け、また、必要に応
じて、加熱する。その後、フォーミング板22とLSI
20とを離すと、図5に示すような、フォーミングバン
プ21a、21a、21aが得られる。これらフォーミ
ングバンプ21a…は、それぞれの高さがほぼ等しく、
また、端面28…にあった凹凸等もフォーミング板12
の上面の主たる面によって、押しつぶされることによっ
て充分にならされ、フォーミング板22の突条22a…
に対応する溝21b、21b・・・が形成されているが他
の大部分の面が平坦である実質的に平坦な端面28a…
を備えたものとなる。
With respect to the upper surface of the forming plate 22,
The bumps 21, 21, 21 formed on the LSI 20 are
The entire LSI 20 is pressed in the same manner as in the first embodiment (in the direction of the arrow in FIG. 4). In this case, the forming plate 22
Is pressed and, if necessary, heated in such a state that the main surface of the upper surface of the device 20 and the surface 20a of the LSI 20 are parallel to each other. After that, the forming plate 22 and the LSI
By separating them from each other, forming bumps 21a, 21a, 21a are obtained as shown in FIG. These forming bumps 21a have substantially the same height,
In addition, irregularities and the like on the end surfaces 28.
Are sufficiently flattened by being crushed by the main surface of the upper surface of the ridge 22a of the forming plate 22.
Are formed, but most other surfaces are flat, and substantially flat end surfaces 28a are formed.
Will be provided.

【0026】次に、図5のLSI20と、液晶表示パネ
ルのガラス基板(他の部品)13とをCOG方式によっ
て接続する。ガラス基板13上にはITO電極14、1
4、14が形成されていて、ITO電極14…は、表面
が十分に平坦で、互いにほぼ同じ高さを有する。ITO
電極14、14、14と、フォーミングバンプ21a、
21a、21aとを、第1の実施の形態と同様の方法
で、図6に示すように、異方性導電膜17を介して、接
続する。この接続工程によって、フォーミングバンプ2
1a…に形成されている溝21b…に、異方性導電膜1
7の導電性フィラー16、16…がはまりこんだ状態に
なる。
Next, the LSI 20 of FIG. 5 and the glass substrate (other components) 13 of the liquid crystal display panel are connected by the COG method. On a glass substrate 13, ITO electrodes 14, 1
4 and 14 are formed, and the ITO electrodes 14 have a sufficiently flat surface and substantially the same height as each other. ITO
Electrodes 14, 14, 14 and forming bumps 21a,
21a and 21a are connected via the anisotropic conductive film 17, as shown in FIG. 6, in the same manner as in the first embodiment. By this connection process, the forming bump 2
1a are formed in the grooves 21b.
The conductive fillers 16, 16,...

【0027】以上の本発明のフォーミングバンプ21
a、21a、21aによれば、それぞれの高さがほぼ同
じであって、十分に平坦な端面28a…を有することか
ら、平坦で均一な高さを有するガラス電極14、14、
14と接続する際に、全てのフォーミングバンプ21a
は、対向するガラス電極14と、同じ状態で密着するこ
とができ、しかも、溝21b…に、導電性フィラー16
が入り込むことから、溝21b…によって導電性フィラ
ー16が捕捉されたような状態になって固定されるか
ら、加熱加圧の際に導電性フィラー16が移動して不均
一な分布状態となることが防止され、LSI20とガラ
ス基板13は、常に良好な接続状態になり、電気的によ
り確実に接続される。加えて、導電性フィラー16…
が、フォーミングバンプ21a…とITO電極14…間
に固定されやすくなっているので、接続に関与する導電
性フィラー16の数が多くなり、フォーミングバンプ2
1a…とITO電極14…間の抵抗が小さくなる。
The above-described forming bump 21 of the present invention
According to a, 21a, and 21a, since the heights are almost the same and the end surfaces 28a are sufficiently flat, the glass electrodes 14, 14, having flat and uniform heights are provided.
14 and all the forming bumps 21a
Can be brought into close contact with the opposing glass electrode 14 in the same state, and the conductive filler 16
, The conductive filler 16 is trapped and fixed by the grooves 21b, so that the conductive filler 16 moves during heating and pressing, resulting in an uneven distribution state. Is prevented, the LSI 20 and the glass substrate 13 are always in a good connection state, and the connection is made more reliably electrically. In addition, conductive filler 16 ...
Are easily fixed between the forming bumps 21a and the ITO electrodes 14, so that the number of conductive fillers 16 involved in the connection increases, and the forming bumps 2
And the resistance between the ITO electrodes 14 becomes small.

【0028】なお、上記第1及び第2の実施の形態のC
OG方式の接続においては、バンプとITO電極を導通
させるものとして、異方性導電膜を用いたが、本発明は
これに限らず、例えば、銀系などの導電性ペーストをバ
ンプに塗布して接続する方法や、導電層としてプラスチ
ックボールを用いる方法等の、各種方法に適用すること
ができる。
Note that C in the first and second embodiments described above.
In the connection of the OG system, an anisotropic conductive film is used as a material for electrically connecting the bump to the ITO electrode. However, the present invention is not limited to this. For example, a conductive paste such as a silver-based paste is applied to the bump. The present invention can be applied to various methods such as a connection method and a method using a plastic ball as a conductive layer.

【0029】(その他の実施の形態)TAB方式で実装
する場合、LSI上に、上記第1の実施の形態または第
2の実施の形態と同様の方法で、フォーミングバンプを
形成して、そのフォーミングバンプとフィルムキャリア
のリード電極とを、共晶合金化反応を利用したり、熱圧
着を利用して接続すれば、各バンプの高さが均一なこと
から、良好な状態で接続できる。さらに、TAB方式で
実装する場合、第2の実施の形態におけるフォーミング
板22を使用する代わりに、上面に複数の溝が格子状に
交差しているフォーミング板を用いて、他は第2の実施
の形態同様に、フォーミングバンプを形成する。この場
合、フォーミングバンプには、フォーミング板の溝に対
応する、凸部が形成される。このようなフォーミングバ
ンプと、リード電極とを接続すれば、各バンプの高さが
均一なことに加えて、バンプには同じ高さの凸部が形成
されているので、その凸部が、リード電極の面に対し
て、食い込むように接触し、強固で安定した接続とな
る。
(Other Embodiments) When mounting by the TAB method, forming bumps are formed on the LSI by the same method as in the first or second embodiment, and the forming bumps are formed. If the bumps are connected to the lead electrodes of the film carrier using a eutectic alloying reaction or thermocompression bonding, the bumps can be connected in good condition because the height of each bump is uniform. Further, when mounting by the TAB method, instead of using the forming plate 22 in the second embodiment, a forming plate in which a plurality of grooves intersect in a lattice pattern on the upper surface is used. Forming bumps are formed in the same manner as in the first embodiment. In this case, a convex portion corresponding to the groove of the forming plate is formed on the forming bump. If such a forming bump is connected to a lead electrode, the height of each bump is uniform and, in addition, the bumps are formed with protrusions of the same height. The surface of the electrode is bitely contacted to provide a strong and stable connection.

【0030】その他、本発明は、COF(Chip On Fil
m)方式等の、バンプを介して接続する、各種実装方式
に、有用である。
In addition, the present invention relates to a COF (Chip On Fil
m) It is useful for various mounting methods such as the method of connecting via bumps.

【0031】[0031]

【発明の効果】請求項1に記載の発明によれば、電子部
品を、これらバンプを介して、他の部品と接続する際
に、全てのバンプが、前記他の部品の電極等に対して、
同じ状態で接触することができ、一部のバンプが接続に
寄与できないといったことが生じることがなく、良好な
接続状態が得られる。また、バンプと、他の部品の電極
とを導電性粒子を介在させて、接続するような場合に
も、導電性粒子の粒径等に関係なく良好な状態で接続す
ることができることから、バンプ間のピッチを大きくし
なくてもよく、高密度実装にも適したバンプとなる。
According to the first aspect of the present invention, when an electronic component is connected to another component via these bumps, all the bumps are connected to the electrodes of the other component. ,
Contact can be made in the same state, and there is no occurrence that some of the bumps cannot contribute to the connection, and a good connection state can be obtained. In addition, even in the case where the bump and the electrode of another component are connected with conductive particles interposed therebetween, the bump can be connected in a good state regardless of the particle size of the conductive particle. It is not necessary to increase the pitch between the bumps, and the bump is suitable for high-density mounting.

【0032】請求項2に記載の発明によれば、請求項1
の効果に加えて、さらに、バンプ先端面に、凸部または
凹部が形成されていることから、より一層、強固な接続
を行うことができるバンプとなる。
According to the invention described in claim 2, according to claim 1
In addition to the effects described above, the bumps or recesses are further formed on the front end surface of the bumps, so that the bumps can be further strongly connected.

【0033】請求項3に記載の発明によれば、バンプ先
端面を容易に平坦化することができ、このバンプを介す
ることにより電子部品間の信頼性の高い導通接続を安定
して得ることができる。
According to the third aspect of the present invention, the front end surface of the bump can be easily flattened, and a highly reliable conductive connection between electronic components can be stably obtained through the bump. it can.

【0034】また、請求項4に記載の発明によれば、平
坦面に凹凸が均等に形成された実質的に平坦なバンプ先
端面を容易に成形でき、より信頼性の高い導通接続を安
定的に得ることができる。
According to the fourth aspect of the present invention, a substantially flat bump tip surface in which unevenness is evenly formed on a flat surface can be easily formed, and a more reliable conductive connection can be stably performed. Can be obtained.

【0035】請求項5に記載の発明によれば、先端面に
凹部が形成されたバンプと接続電極との間に異方性導電
膜を介するから、バンプと接続電極とが電気的により確
実に接続される。
According to the fifth aspect of the present invention, since the anisotropic conductive film is interposed between the connection electrode and the bump having the concave portion formed on the tip end surface, the bump and the connection electrode can be more reliably electrically connected. Connected.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明のバンプの形成方法の一例を示す断面図
である。
FIG. 1 is a cross-sectional view illustrating an example of a method for forming a bump according to the present invention.

【図2】図1のバンプの形成方法で得られたバンプを示
す断面図である。
FIG. 2 is a sectional view showing a bump obtained by the bump forming method of FIG. 1;

【図3】図2のバンプと、ITO電極とを接続した状態
を示す断面図である。
FIG. 3 is a cross-sectional view showing a state where the bumps of FIG. 2 are connected to ITO electrodes.

【図4】本発明のバンプの形成方法の他の例を示す断面
図である。
FIG. 4 is a cross-sectional view showing another example of the bump forming method of the present invention.

【図5】図4のバンプの形成方法で得られたバンプを示
す断面図である。
FIG. 5 is a sectional view showing a bump obtained by the bump forming method of FIG. 4;

【図6】図5のバンプと、ITO電極とを接続した状態
を示す断面図である。
FIG. 6 is a cross-sectional view showing a state where the bumps of FIG. 5 are connected to ITO electrodes.

【図7】図4のバンプの形成方法において、用いられる
フォーミング板を示す斜視図である。
FIG. 7 is a perspective view showing a forming plate used in the bump forming method of FIG. 4;

【図8】従来のバンプとITO電極との接続の状態の一
例を示す断面図である。
FIG. 8 is a cross-sectional view showing an example of a conventional connection state between a bump and an ITO electrode.

【図9】従来のバンプとITO電極との接続の状態の他
の例を示す断面図である。
FIG. 9 is a cross-sectional view showing another example of a conventional connection state between a bump and an ITO electrode.

【符号の説明】[Explanation of symbols]

10、20 LSI(電子部品) 11、21 バンプ 11a、21a フォーミングバンプ 21b 溝(凹部) 12、22 フォーミング板(板部材) 22a 突条(凸部) 13 ガラス基板(他の部品) 14 ITO電極(他の部品の電極) 15 樹脂 16 導電性フィラー(導電性粒子) 17 異方性導電膜(導電部材) 18、28 端面 10, 20 LSI (electronic component) 11, 21 Bump 11a, 21a Forming bump 21b Groove (concave) 12, 22 Forming plate (plate member) 22a Ridge (convex) 13 Glass substrate (other components) 14 ITO electrode ( Electrodes of other parts) 15 Resin 16 Conductive filler (conductive particles) 17 Anisotropic conductive film (conductive member) 18, 28 End face

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 電子部品の平坦な外面に、複数、形成さ
れていて、前記電子部品と電気的に接続されているバン
プであって、 前記外面に対してほぼ平行で平坦な先端面をそれぞれ有
していて、かつ、互いにほぼ同じ高さであることを特徴
とするバンプ。
1. A plurality of bumps, which are formed on a flat outer surface of an electronic component and are electrically connected to the electronic component, each of which has a flat tip surface substantially parallel to the outer surface. A bump having a height that is substantially the same as each other.
【請求項2】 前記平坦な先端面は、平坦面に凸部また
は凹部のいずれか一方が、均等に形成された実質的に平
坦な先端面であることを特徴とする請求項1に記載のバ
ンプ。
2. The flat end surface according to claim 1, wherein the flat end surface is a substantially flat end surface in which one of a convex portion and a concave portion is formed uniformly. bump.
【請求項3】 電子部品を該電子部品の平坦な外面に形
成されている複数のバンプを介して他の部品に導通可能
に接続するための電子部品のボンディング方法であっ
て、 平坦な成形面を備えた成形台を準備し、 前記電子部品の前記外面が前記成形面に平行な状態を保
ちつつ複数の前記バンプ先端面を前記成形面に押し当て
て平坦な面に成形し、 この後、前記電子部品の外面と前記他の部品の電極の表
面とがほぼ平行な状態で、前記複数のバンプと前記電極
とを導通可能に接続することを特徴とする電子部品のボ
ンディング方法。
3. A method for bonding an electronic component to another component via a plurality of bumps formed on a flat outer surface of the electronic component in a conductive manner, the method comprising bonding a flat molded surface. Preparing a molding table provided with, the outer surface of the electronic component is pressed against the molding surface while pressing the plurality of bump tip surfaces against the molding surface while maintaining a state parallel to the molding surface, and thereafter, A method of bonding an electronic component, wherein the plurality of bumps and the electrode are conductively connected with an outer surface of the electronic component and a surface of an electrode of the other component being substantially parallel to each other.
【請求項4】 前記成形台として平坦面に凸部又は凹部
を均等に形成した実質的に平坦な成形面を備える成形台
を使用し、前記バンプ先端面を凸部または凹部が均等に
形成された実質的に平坦な面に成形することを特徴とす
る請求項3に記載の電子部品のボンディング方法。
4. A molding table having a substantially flat molding surface in which projections or depressions are uniformly formed on a flat surface is used as the molding table, and the projections or depressions are uniformly formed on the bump tip surface. 4. The method for bonding electronic components according to claim 3, wherein the bonding is performed on a substantially flat surface.
【請求項5】前記成形台として平坦面に凸部が均等に形
成された成形面を備えるものを使用して前記バンプ先端
面を平坦面に凹部を均等に形成した実質的に平坦な先端
面に成形し、前記電子部品のバンプと前記他の部品の電
極とを導電性粒子を含有する異方性導電膜を介在させて
導電接続することを特徴とする請求項4に記載の電子部
品のボンディング方法。
5. A substantially flat tip surface in which the bump tip is formed evenly on a flat surface by using a molding table having a molding surface on which a projection is uniformly formed on a flat surface. 5. The electronic component according to claim 4, wherein the bump of the electronic component and the electrode of the other component are electrically connected to each other through an anisotropic conductive film containing conductive particles. Bonding method.
JP11531698A 1998-04-24 1998-04-24 Bonding method for electronic components Expired - Fee Related JP3752836B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11531698A JP3752836B2 (en) 1998-04-24 1998-04-24 Bonding method for electronic components

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11531698A JP3752836B2 (en) 1998-04-24 1998-04-24 Bonding method for electronic components

Publications (2)

Publication Number Publication Date
JPH11307578A true JPH11307578A (en) 1999-11-05
JP3752836B2 JP3752836B2 (en) 2006-03-08

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ID=14659600

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Application Number Title Priority Date Filing Date
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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008053427A (en) * 2006-08-24 2008-03-06 Seiko Instruments Inc Semiconductor device and its manufacturing method
JP2014049629A (en) * 2012-08-31 2014-03-17 National Institute Of Advanced Industrial & Technology Joint method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008053427A (en) * 2006-08-24 2008-03-06 Seiko Instruments Inc Semiconductor device and its manufacturing method
JP2014049629A (en) * 2012-08-31 2014-03-17 National Institute Of Advanced Industrial & Technology Joint method

Also Published As

Publication number Publication date
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