JPH11306795A - Test method for semiconductor device and semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor memory whose test time can be shortened sharply by a method wherein data is written collectively into all memory cells. SOLUTION: When a positive power-supply voltage VDD is applied to a p-type well layer 28, a diode which is formed of the p-type well layer 28 and an n<+> type impurity diffusion layer 23 is forward-biased, HIGH data is written into a capacitor which is formed of a storage electrode 24, a dielectric film 25 and a plate electrode 26, and, after that, a substrate voltage VBB is applied to the p-type well layer 28. In addition, when a p-n junction breakdown voltage is applied to the p-type well layer 28, the diode which is formed of the p-type well layer 28 and the n<+> type impurity diffusion layer 23 is broken down, LOW data is written into the capacitor which is formed of the storage electrode 24, the dielectric film 25 and the plate electrode 26, and the substrate voltage VBB is applied to the p-type well layer 28.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory test method and a semiconductor memory capable of writing test data to all memory cells at once.

[0002]

2. Description of the Related Art A conventional semiconductor memory test method and semiconductor memory will be described below. FIG. 8 is a circuit diagram showing a configuration of a conventional semiconductor memory. In FIG. 8, 1 is a memory cell array, 2 is a memory cell composed of an n-type MOS transistor and a storage capacitor, and 3 is a memory cell 2
4 is a bit line connected to the source of the n-type MOS transistor of the memory cell 2, 5 is a row address selection circuit, 6 is a word line connected to the gate of the n-type MOS transistor.
Is a sense amplifier, 7 is a column address selection circuit, 8 is an input / output (I / O) line, and 9 is a substrate voltage generation circuit for generating a predetermined negative voltage as the substrate voltage VBB.

A memory cell array 1 includes a large number of memory cells 2 and a large number of word lines 3 arranged in a matrix.
And a number of bit lines 4. The row address selection circuit 5 selects the word line 3 based on an externally input row address signal. The sense amplifier 6 is connected to the bit line 4
The signal of the memory cell 2 read out is amplified. The column address selection circuit 7 selects a bit line based on a column address signal.

In a read operation, a signal of the memory cell 2 selected by the row address selection circuit 5 and the column address selection circuit 7 is read to the input / output line 8. During a write operation, an external signal is written to the memory cell 2 selected by the row address selection circuit 5 and the column address selection circuit 7 via the input / output line 8. The substrate voltage generation circuit 9 is an internal power supply circuit mounted in the memory chip, and the substrate voltage VBB is applied commonly to the substrates of all the memory cells 2 in the memory cell array 1. The applied voltage is a negative potential, and the power supply voltage is VDD.
(Positive voltage), the substrate voltage VBB is about-(1/2)
It is about VDD. After the power is turned on, the substrate voltage VBB is constantly applied to the substrate of the memory cell 1.

[0005] Normally, a method for testing a semiconductor memory is as follows.
A method is employed in which a predetermined data pattern is written in all memory cells, then data in all memory cells is read, and it is determined whether or not the data matches an expected value. In order to write data to all memory cells, a write operation is performed by sequentially changing the row address and the column address input from the outside. The same applies to the read operation. Here, assuming that the number of row addresses is m, the number of column addresses is n, and the time required for one write operation is t0, the time required for writing all memory cells is m × n × t0. For example, 16M
For a semiconductor memory of bit (number of input / output = 1), m = 409
Assuming that 6, n = 4096 and t0 = 200 ns, the time required for writing to all memory cells is 3.36 seconds.

[0006]

However, in the above-described conventional semiconductor memory configuration and semiconductor memory test method, since the address is input from the outside and the memory cells are selected one bit at a time, the capacity of the semiconductor memory can be increased. As you progress, the test time becomes enormous. For example, 1Mbi
The total memory cell write operation, which took about 0.2 to 0.3 seconds in a semiconductor memory of t capacity, becomes 1024 times larger in a semiconductor memory of 1 Gbit capacity, so that the write operation of all memory cells takes about 200 to 300 seconds. It will be long before. This increase in test time is problematic because it causes an increase in test cost and a decrease in throughput.

An object of the present invention is to provide a test method for a semiconductor memory which enables a test time to be shortened by enabling data to be written to all memory cells at once. Another object of the present invention is to provide a semiconductor memory capable of shortening a test time by enabling data to be collectively written to all memory cells even after a memory chip is sealed in a package. is there.

[0008]

According to a first aspect of the present invention, there is provided a method for testing a semiconductor memory, comprising: providing a pair of n-type impurity diffusion layers in a p-type well layer; An n-type MOS transistor having a gate electrode provided on a p-type well layer, and a storage capacitor having a storage electrode, a dielectric film and a plate electrode provided on one of the n-type impurity diffusion layers of the n-type MOS transistor This is a method for testing a semiconductor memory having a large number of memory cells. During the test of the semiconductor memory, a power supply voltage is applied to a p-type well layer to form a semiconductor memory formed from an n-type impurity diffusion layer and a p-type well layer. The pn junction diode is biased in the forward direction, high data is written to the storage capacitors of a large number of memory cells at once, and then a test is performed by applying a negative voltage to the p-type well layer. To.

According to this method, by changing the potential of the p-type well layer commonly connected to all the memory cells, high data is written to all the memory cells at once, so that data is written for each memory cell. The test time can be significantly reduced as compared with the case of writing. According to the semiconductor memory test method of the present invention, a pair of n-type
An n-type MOS transistor provided with a p-type impurity diffusion layer and a gate electrode on a p-type well layer between a pair of n-type impurity diffusion layers; A method for testing a semiconductor memory provided with a large number of memory cells each having a storage capacitor provided with a storage electrode, a dielectric film, and a plate electrode. At the time of testing the semiconductor memory, a predetermined negative voltage is applied to a p-type well layer. Is applied, the pn junction diode formed from the n-type impurity diffusion layer and the p-type well layer is broken down, and low data is collectively written to the storage capacitors for a large number of memory cells. And applying a negative voltage smaller than a predetermined negative voltage to the test.

According to this method, by changing the potential of the p-type well layer commonly connected to all the memory cells, the low data is written to all the memory cells at once, so that the data is written for each memory cell. The test time can be significantly reduced as compared with the case of writing. 4. The semiconductor memory according to claim 3, wherein a plurality of memory cells, a substrate voltage generation circuit for generating a predetermined negative voltage as a substrate voltage, and a test mode determination circuit for determining a test mode based on an external input signal. And a connection switching circuit that switches and applies either the positive power supply voltage or the output voltage of the substrate voltage generation circuit to the p-type well layer based on the output result of the test mode determination circuit and an external input signal. .

In this case, a large number of memory cells are provided with a pair of n-type impurity diffusion layers in a p-type well layer and a pair of n-type impurity diffusion layers.
An n-type MOS transistor having a gate electrode provided on a p-type well layer between the n-type impurity diffusion layers; and a storage electrode, a dielectric film and a plate electrode on one of the n-type impurity diffusion layers of the n-type MOS transistor. And provided storage capacitors.

The test mode determining circuit receives, for example, an inverted chip select signal, an inverted row address strobe signal, an inverted column address strobe signal, an inverted write enable signal, and an address signal as input signals.
The following configuration is provided. That is, a first CMOS inverter receiving an inverted chip select signal and a second CMOS inverter receiving an inverted row address strobe signal.
CMOS inverter, a third CMOS inverter receiving an inverted column address strobe signal, a fourth CMOS inverter receiving an inverted write enable signal, an output signal of the first CMOS inverter, and a second CMOS inverter.
A first NAND circuit which receives an output signal of the third CMOS inverter, an output signal of the third CMOS inverter, and an output signal of the fourth CMOS inverter, and a first NAN
A fifth CMOS inverter to which an output signal of the D circuit is input, a clock to which an address signal is input, a positive clock input to an output signal of the fifth CMOS inverter, and an inverted clock input to an output signal of the first NAND circuit And a latch circuit that connects the seventh and eighth CMOS inverters in a loop and holds the output signal of the clocked inverter.

The connection switching circuit uses, for example, an inverted chip select signal, an inverted row address strobe signal, an inverted column address strobe signal, an inverted write enable signal, and an output signal of a latch circuit as input signals, and has the following configuration. It has. That is, a ninth CMOS inverter receiving the inverted chip select signal,
10th input of inverted column address strobe signal
CMOS inverter, an eleventh CMOS inverter receiving an inverted write enable signal, and a ninth CM
A second NAND circuit to which the input signal of the output signal of the OS inverter, the output signal of the tenth CMOS inverter, the output signal of the eleventh CMOS inverter, the output signal of the latch circuit, and the inverted row address strobe signal are input; 2, a p-type MOS transistor having a source connected to a power supply voltage and a drain connected to a p-type well layer, and a second NAN connected to a gate.
An output signal of the D circuit is applied, a substrate voltage of a predetermined negative voltage is applied to the source, and an n-type MOS transistor having a drain connected to the p-type well layer is provided.

According to this configuration, in addition to the configuration of the conventional semiconductor memory, a test mode determination circuit and a connection switching circuit are provided, and the test mode is determined based on an external input signal. Since either the positive power supply voltage or the output voltage of the substrate voltage generating circuit is switched and applied to the p-type well layer according to the input signal, even after the memory chip is sealed in the package, it can be applied to all the memory cells. By changing the potential of the commonly connected p-type well layer, high data can be written to all memory cells at once, greatly shortening the test time compared to writing data for each memory cell. Becomes possible.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a sectional view of a memory cell of a DRAM (dynamic random access memory) according to an embodiment of the present invention, and FIG.
Is an equivalent circuit diagram of a memory cell. In FIG. 1A, 20 is an n ⁺ -type impurity diffusion layer, 21 is a bit line, 22
Is a gate electrode, 23 is an n ⁺ -type impurity diffusion layer, 24 is a storage electrode, 25 is a dielectric film, 26 is a plate electrode, and 27 is p
^{A +} -type impurity diffusion layer, 28 is a p-type well layer, 29 is an n ⁺ -type impurity diffusion layer, 30 is an n-type substrate, and 31 is a field oxide film. In FIG. 1B, reference numeral 32 denotes a bit line;
Is a word line, 34 is a storage electrode terminal, 35 is a capacitor,
36 is a plate terminal, 37 is a substrate terminal, 38 and 39 are diodes, and 40 is an n-type MOS transistor.

In the semiconductor memory of FIG. 1, n-type impurity diffusion layer 20, gate electrode 22 and n-type impurity diffusion layer 2
Reference numeral 3 denotes a source, a gate, and a drain of the n-type MOS transistor 40, respectively.
23 is formed in the p-type well layer 28, and the gate electrode 22 is formed on the p-type well layer 28 between the pair of n ⁺ -type impurity diffusion layers 20 and 23. Bit line 21 is connected to n ⁺ -type impurity diffusion layer 20 and corresponds to bit line 32 of the equivalent circuit. Gate electrode 22 corresponds to word line 33 of the equivalent circuit.

Further, a storage capacitor is formed by the storage electrode 24, the dielectric film 25 and the plate electrode 26 which are sequentially laminated on the n ⁺ -type impurity diffusion layer 23. The storage electrode terminal 34, the capacitor 35 and the plate It corresponds to the terminal 36. The plate electrode 26 normally has (1/1 /
2) A positive voltage of VDD is applied. The p ⁺ -type impurity diffusion layer 27 is connected to the p-type well layer 28, and a substrate voltage VBB, which is usually a negative voltage, is applied to the p-type well layer 28 through the p ⁺ -type impurity diffusion layer 27. The p ⁺ -type impurity diffusion layer 27 corresponds to the substrate terminal 37 of the equivalent circuit. The n ⁺ -type impurity diffusion layer 29 is connected to the n-type substrate 30, and a positive power supply voltage VDD is normally applied to the n-type substrate 30 through the n ⁺ -type impurity diffusion layer 29. Field oxide film 31 is an area for separating memory cells. The pn junction diodes formed from the p-type well layer 28 and the n ⁺ -type impurity diffusion layers 20 and 23 correspond to the diodes 38 and 39 of the equivalent circuit, respectively.

Hereinafter, a first embodiment of the method for testing a semiconductor memory according to the present invention will be described with reference to FIG. FIG. 2 is a time sequence diagram, and FIG.
7 shows the potential of the storage electrode terminal 34. FIG. Usually, (1/2) VDD which is a positive voltage is applied to the plate terminal 36, and a substrate voltage VBB which is a negative voltage is applied to the substrate terminal 37. The substrate voltage VBB is − (1 /
2) A negative voltage of about VDD. The potential of the storage electrode terminal 34 is arbitrary between 0 V and the power supply voltage VDD, but is assumed to be 0 V here.

When the voltage applied to the substrate terminal 37 is changed from the substrate voltage VBB to the power supply voltage VDD at time t0, the pn junction diode 39 is forward-biased, so that the potential of the storage electrode terminal 34 becomes VDD-VT. However, the voltage VT is the rising voltage of the pn junction diode 39,
It is about 0.7V. Here, since the substrate potential changes from the substrate voltage VBB which is a negative voltage to the power supply voltage VDD, the back bias effect is reduced, so that the n-type MOS transistor 4
0 may be turned on. However, n-type M
The source and drain of the OS transistor 40 are p
Since the n-junction diodes 38 and 39 have the same potential of VDD-VT, the potential of the storage electrode terminal 34 becomes VDD-VT.
Is kept.

Next, a substrate voltage VBB is applied to the substrate terminal 37 at time t1. Since the pn junction diode 39 is reverse-biased, the potential of the storage electrode terminal 34 remains at V
DD-VT is maintained. With the above operation, high data can be written to the memory cell. During this write operation, the cell plate terminal 36 is kept constant at (1/2) VDD. Since the substrate terminal 37 is provided commonly to all the memory cells, high data can be written to all the memory cells at once by the above operation.

After this operation is completed, the substrate terminals 3
Since the same substrate voltage VBB as in normal use is applied to 7, operations such as reading can be performed. Also,
If the bit line 32 is open at the time of this batch write operation, the potential becomes VDD-VT after the write operation is completed similarly to the accumulated charge terminal 34, so that a bit line precharge operation is necessary.

After the above batch write operation is completed,
By performing a normal read operation, a test of the memory cell can be performed. At this time, the expected value of the data output to the outside of the chip is set so that the data of the memory cell becomes high data. In order to read data from all the memory cells, a read operation is performed by sequentially changing the row address and the column address input from the outside.

Next, a second embodiment of the method for testing a semiconductor memory according to the present invention will be described with reference to FIGS. FIG. 3 shows the current-voltage characteristics of the pn junction diode. The horizontal axis represents the applied voltage, and the vertical axis represents the current flowing through the pn junction diode. In a pn junction diode, when the reverse bias voltage is increased, a current starts to flow in a reverse direction at a certain voltage. The voltage at which the reverse current starts to flow is called the breakdown voltage. The breakdown voltage varies depending on the carrier density of the pn junction, but is approximately -4V to -7V. In this test method, batch writing of raw data is performed using this breakdown phenomenon.

FIG. 4 is a time sequence diagram in the case of batch writing of row data. FIG. 4A shows the potential of the substrate terminal 37, and FIG. 4B shows the potential of the storage electrode terminal 34. Normally, (1/1 /
2) VDD, substrate voltage VB which is a negative voltage at substrate terminal 37
B is applied. The substrate voltage VBB is-(1/2) V
This is a negative voltage of about DD. The potential of the storage electrode terminal 34 is 0
It is arbitrary between V and the power supply voltage VDD, but here it is assumed that it is the same as the power supply voltage VDD.

At time t0, when the voltage applied to the substrate terminal 37 is changed from the substrate voltage VBB to the breakdown voltage VBD of the pn junction diode 38, the storage electrode terminal 34, whose potential is the same as the power supply voltage VDD, changes the breakdown current until the voltage becomes 0V. , The potential of the storage electrode terminal 34 can be set to 0V. Next, at time t1, the breakdown voltage VB is applied to the substrate terminal 37.
A substrate voltage VBB which is a negative voltage smaller than D is applied. Since the potential of the storage electrode terminal 34 is 0 V, and the pn junction diode 38 is kept reverse-biased, the potential of the storage electrode terminal 34 is kept at 0 V.

With the above operation, low data can be written to the memory cell. During this write operation, the cell plate terminal 36 is kept constant at (1/2) VDD. Since the substrate terminal 37 is provided in common to all the memory cells, the row data can be collectively written to all the memory cells by the above operation. After this operation is completed, the substrate terminal 37 is set to the same substrate voltage V as in normal use.
Since BB is applied, operations such as reading can be performed. If the bit line 32 is open during the batch write operation, the potential becomes 0 V after the end of the write operation as in the case of the accumulated charge terminal 34, so that a bit line precharge operation is required.

After the above batch write operation is completed,
By performing a normal read operation, a test of the memory cell can be performed. At this time, the expected value of the data output to the outside of the chip is set so that the data of the memory cell becomes low data. In order to read data from all the memory cells, a read operation is performed by sequentially changing the row address and the column address input from the outside.

Next, an embodiment of the semiconductor memory according to the present invention will be described with reference to FIGS. 5, 6 and 7. FIG. FIG. 5 is a circuit diagram showing a configuration of the semiconductor memory.
In FIG. 5, 1 is a memory cell array, 2 is a memory cell, 3 is a word line, 4 is a bit line, 5 is a row address selection circuit, 6 is a sense amplifier, 7 is a column address selection circuit, 8
Denotes an input / output line, and 9 denotes a substrate voltage generating circuit, which are the same as those of the conventional example. Reference numeral 10 denotes a test mode determination circuit formed on the memory chip, 11 denotes a connection switching circuit formed on the memory chip, 12 denotes a test mode determination output, and 13 denotes a connection switching circuit output.

The test mode determination circuit 10 includes an inverted chip select signal (hereinafter, referred to as a / CS signal) and an inverted row address strobe signal (hereinafter, referred to as a / RAS signal).
And an inverted column address strobe signal (hereinafter, / CA)
S signal) and an inverted write enable signal (hereinafter, referred to as S signal).
/ WE signal) and an address signal (here, A0, hereinafter referred to as A0 signal) are input signals. /
CS signal, / RAS signal, / CAS signal, / WE signal,
The A0 signal is a signal input from outside the memory chip.

In test mode determination circuit 10,
When all of the CS signal, the / RAS signal, the / CAS signal, and the / WE signal are at the low level, the test mode is determined. At this time, if the A0 signal is at a high level, a high level (meaning the test mode) is output as the test mode determination output 12. If the A0 signal is at a low level, a low level (meaning the normal mode) is output as the test mode determination output 12. The state of the test mode determination output 12 is maintained while the semiconductor memory is powered on.

The connection switching circuit 11 outputs a signal / CS and a signal / R
The AS signal, the / CAS signal, the / WE signal, and the test mode determination output 12 are input signals, and the power supply voltage VDD and the substrate voltage VBB are input as switching power supply voltages. When the test mode determination output 12 is at the high level, the connection switching circuit 11 outputs the / CS signal, the / CAS signal, and the / WE signal.
When the signal goes low and the / RAS signal goes high, the power supply voltage VDD is output as the connection switching circuit output 13. In other periods, the substrate voltage VBB is output as the connection switching circuit output 13. The connection switching output 13 is commonly applied to the substrate terminals of all the memory cells 2 of the memory cell array 1.

FIG. 6 is a circuit diagram showing a specific example of the test mode determination circuit 10 and the connection switching circuit 11 of FIG. 6, reference numeral 10 denotes a test mode determination circuit, 11 denotes a connection switching circuit, 12 denotes a test mode determination output output from the test mode determination circuit 10, and 13 denotes a connection switching circuit output output from the connection switching circuit 11. 101,10
2, 103 and 104 are CMOS inverters and 105 is N
AND circuit, 106 is a clocked inverter, 107 is a CMOS inverter, 108 is a latch circuit in which two CMOS inverters 108a, 108b are connected in a loop, 111, 112, 113 are CMOS inverters,
14 is a NAND circuit, 115 is a p-type MOS transistor, and 116 is an n-type MOS transistor.

CMOS inverters 101, 102, 10
3 and 104 are / CS signal, / RAS signal, / 104, respectively.
The CAS signal and the / WE signal are input. The NAND circuit 105 includes CMOS inverters 101, 102, and 10.
3,104 output signals are input, / CS signal,
When the / RAS signal, the / CAS signal, and the / WE signal all go low, a low level is output.

The clocked inverter 106 receives an A0 signal, which is an address signal, as an input.
The output signal 05 is an inverted clock signal, and the output signal of the CMOS inverter 107 is a positive clock signal. Therefore, if the output signal of the NAND circuit 105 is at a low level, the clocked inverter 106 is turned on,
An inverted signal of the A0 signal is output. Conversely, when the output signal of the NAND circuit 105 is at a high level, the clocked inverter 106 is turned off and its output is opened.

The latch circuit 108 receives the output of the clocked inverter 106 as an input and
6 is held. For example, / CS signal, / R
When the AS signal, the / CAS signal, and the / WE signal are all at low level and the A0 signal is at high level, the output of the clocked inverter 106 is at low level, and the latch circuit 108
Hold the high level. Thereafter, even if the / CS signal, / RAS signal, / CAS signal and / WE signal are changed to other states and the output of the clocked inverter 106 is opened, the output signal of the latch circuit 108, that is, the test mode determination output Reference numeral 12 holds the previous state. When the test mode determination output 12 is set again, the / CS signal, / RAS signal, / CAS signal and /
The setting is performed by setting all the WE signals to low level and setting the A0 signal to low level or high level.

CMOS inverters 111, 112, 11
3 receives a / CS signal, a / CAS signal, and a / WE signal, respectively. The NAND circuit 114 receives the output signal of the CMOS inverter 111, the / RAS signal, the output signal of the CMOS inverter 112, the output signal of the CMOS inverter 113, and the test mode determination output 12, and the / RAS signal becomes high level and the / CS signal becomes ,
When the / CAS signal and the / WE signal go low and the test mode determination output 12 goes high,
Low level is output.

The p-type MOS transistor 115 has a gate to which the output signal of the NAND circuit 114 is applied, a source to which the power supply voltage VDD is applied, and a drain serving as the connection switching circuit output 13. n-type MOS transistor 1
In 16, the output signal of the NAND circuit 114 is applied to the gate, the substrate voltage VBB is applied to the source, and the drain is the connection switching circuit output 13. CMO with p-type MOS transistor 115 and n-type MOS transistor 116
S is formed.

When the output of the NAND circuit 114 is at a low level, the p-type MOS transistor 115 is turned on and n
Since the type MOS transistor 116 is turned off, the power supply voltage VDD is output as the connection switching circuit output 13. Conversely, when the output of the NAND circuit 114 is at a high level,
The p-type MOS transistor 115 is turned off and the n-type MOS
Since the S transistor is turned on, the substrate voltage VBB is output as the connection switching circuit output 13.

Next, the usage and operation of the test mode determination circuit 10 and the switching connection circuit 11 will be described with reference to FIG.
This will be described with reference to FIG. FIG. 7 is a time sequence diagram showing a / CS signal, a / RAS signal, a / CAS signal, and a / WE signal.
3 shows waveforms of a signal, an A0 signal, a test mode determination output 12, and a connection switching circuit output 13. The hatched portion of the A0 signal indicates an arbitrary state.

First, the test mode is set in the period t0. During this period, the / CS signal, / RAS signal, /
The CAS signal and the / WE signal are all at low level, and the A0 signal is at high level. At this time, a high level is output to the test mode determination output 12, and
Even if the CS signal, the / RAS signal, the / CAS signal and the / WE signal are returned to the high level, the test mode determination output 12
Is maintained at a high level. Note that the / CS signal,
/ CAS signal and / WE signal are low level,
Since the RAS signal is not at the high level, the connection switching circuit output 13 outputs the substrate voltage VBB.

Next, at the time t1, all the memory cells are simultaneously written. During this period, the / CS signal, / CA
When the S signal and the / WE signal are set to the low level and the / RAS signal is set to the high level, the high level is output as the test mode determination output 12, so that the NAND circuit 114 outputs the low level and the connection switching circuit Output 13
Is supplied with a power supply voltage VDD. Connection switching circuit output 1
3 is connected to a substrate terminal commonly connected to all memory cells. Therefore, according to the principle described in the first embodiment of the semiconductor memory test method of the present invention, high-level data can be written to all memories at once during the period t1.

Next, in the period t2, the test mode is released. In this period, the / CS signal, the / RAS signal, the / CAS signal, and the / WE signal are all at the low level, and the A0 signal is at the low level. At this time, a low level is output as the test mode determination output 12. Again, the / CS signal, / RAS signal, / CAS signal and /
The low level of the test mode determination output 12 is maintained unless all the WE signals are set to low level and reset.

If the test mode judgment output 12 is at a low level, the NAND circuit 114 is fixed at a high level output, so that the connection switching circuit output 13 is the substrate voltage VBB.
Is output, and the mode becomes a normal use mode. That is, as shown in the period t3, the / CS signal, / CAS signal and / W signal
Even when the E signal is set to the low level and the / RAS signal is set to the high level, the test mode determination output 12 is at the low level, so that the connection switching circuit output 13 outputs the substrate voltage VBB.

Note that the test was conducted with the board terminal 3
7 has a pad provided so as to be applied from the outside to the inside of the memory chip, the semiconductor memory of the first and second embodiments can be tested in a wafer state without providing a dedicated circuit inside the memory chip. The method can be performed. However, after the memory chip is sealed in the package, it is impossible to apply a voltage to the substrate terminal directly from the outside, so that the semiconductor memory test methods of the first and second embodiments cannot be performed. . In the semiconductor memory according to the embodiment of the present invention, even after the memory chip is sealed in the package, the first memory is supplied by an external input signal.
The method for testing a semiconductor memory according to the embodiment can be implemented.

According to the semiconductor memory test method of the first embodiment, since the pn junction diode 39 formed in each memory cell is forward-biased, high data can be written to all memory cells at once. Thus, the test time can be reduced. After writing the high data, a negative voltage is applied to the p-type well layer 28 in order to perform an operation such as the next reading.
Is reverse biased, so the capacitor (storage capacitance)
35 charges do not flow out.

According to the semiconductor memory test method of the second embodiment, since the pn junction diode 39 formed in each memory cell causes a breakdown phenomenon, low data can be written to all memory cells at once. Thus, the test time can be reduced. Further, in the semiconductor memory according to the embodiment of the present invention, a connection switching circuit 11 that can switch connection between the substrate voltage VBB and the power supply voltage VDD and a test mode determination circuit 10 that determines a test mode are mounted on the substrate terminal inside the memory chip. Therefore, even in the test after the memory chip is sealed in the package, the test method for the semiconductor memory of the first embodiment can be performed, and the test time can be reduced.

[0047]

According to the semiconductor memory test method of the present invention, by applying a power supply voltage to the p-type well layer of each memory cell, high data is collectively stored in the storage capacitors of all memory cells. Writing can be performed, and the test time can be reduced. According to the semiconductor memory test method of the present invention, by applying a predetermined negative voltage to the p-type well layer of each memory cell, low data is collectively written to the storage capacitors of all memory cells. The test time can be shortened.

According to the semiconductor memory of the third aspect of the present invention, since the connection switching circuit capable of switching the connection between the substrate voltage and the power supply voltage and the test mode determination circuit for determining the test mode are added, the memory chip is sealed in the package. Even in the test after stopping, high data can be collectively written to the storage capacitors of all the memory cells, and the test time can be reduced.

[Brief description of the drawings]

FIG. 1A is a sectional view showing a configuration of a memory cell of a semiconductor memory (DRAM) to be tested in the present invention;
FIG. 2B is an equivalent circuit diagram of FIG.

FIG. 2 is a time sequence diagram illustrating a test method of the semiconductor memory according to the first embodiment of the present invention.

FIG. 3 is an applied voltage-current characteristic diagram of a pn diode according to a semiconductor memory test method according to a second embodiment of the present invention.

FIG. 4 is a time sequence diagram illustrating a test method of a semiconductor memory according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory according to an embodiment of the present invention.

FIG. 6 is a circuit diagram showing a specific configuration of a connection switching circuit and a test mode determination circuit in FIG.

FIG. 7 is a time sequence chart showing an operation of the semiconductor memory according to the embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration of a conventional semiconductor memory.

[Explanation of symbols]

Reference Signs List 1 memory cell array 2 memory cell 3 word line 4 bit line 5 row address selection circuit 6 sense amplifier 7 column address selection circuit 8 input / output line 9 substrate voltage generation circuit 10 test mode determination circuit 11 connection switching circuit 12 test mode determination output 13 connection Switching circuit output 20 n ⁺ -type impurity diffusion layer 21 bit line 22 gate electrode 23 n ⁺ -type impurity diffusion layer 24 storage electrode 25 dielectric film 26 plate electrode 27 p ⁺ -type impurity diffusion layer 28 p-type well layer 29 n ⁺ -type impurity Diffusion layer 30 n-type substrate 31 field oxide film 32 bit line 33 word line 34 storage electrode terminal 35 capacitor 36 plate terminal 37 substrate terminal 38 diode 39 diode 40 n-type MOS transistor 101-104 CMOS inverter 105 NAND circuit 106 clocked Converter 107 CMOS inverter 108 latch circuits 111 to 113 CMOS inverter 114 NAND circuit 115 p-type MOS transistor 116 n-type MOS transistor

Claims (4)

[Claims] A pair of n-type impurity diffusion layers provided in a p-type well layer;
An n-type MOS transistor having a gate electrode provided on a mold well layer; and a storage capacitor having a storage electrode, a dielectric film, and a plate electrode provided on one of the n-type impurity diffusion layers of the n-type MOS transistor. A test method of a semiconductor memory for testing a semiconductor memory having a large number of memory cells, wherein a power supply voltage is applied to the p-type well layer to test the semiconductor memory, After biasing the pn junction diode formed from the p-type well layer in the forward direction and writing high data to the storage capacitors of the plurality of memory cells collectively, applying a negative voltage to the p-type well layer A method for testing a semiconductor memory, comprising: 2. A semiconductor device comprising: a pair of n-type impurity diffusion layers provided in a p-type well layer;
An n-type MOS transistor having a gate electrode provided on a mold well layer; and a storage capacitor having a storage electrode, a dielectric film, and a plate electrode provided on one of the n-type impurity diffusion layers of the n-type MOS transistor. A semiconductor memory test method for testing a semiconductor memory having a large number of memory cells, the method comprising: applying a predetermined negative voltage to the p-type well layer during the test of the semiconductor memory; After the pn junction diode formed from the layer and the p-type well layer is broken down and the low data is collectively written to the storage capacitor for the plurality of memory cells, the predetermined negative voltage is applied to the p-type well layer. A test method for a semiconductor memory, wherein a test is performed by applying a smaller negative voltage than the above. 3. A p-type well layer provided with a pair of n-type impurity diffusion layers, and the p-type well layer between the pair of n-type impurity diffusion layers.
An n-type MOS transistor having a gate electrode provided on a mold well layer; and a storage capacitor having a storage electrode, a dielectric film, and a plate electrode provided on one of the n-type impurity diffusion layers of the n-type MOS transistor. A large number of memory cells, a substrate voltage generation circuit that generates a predetermined negative voltage as a substrate voltage, a test mode determination circuit that determines a test mode based on an externally input signal, an output result of the test mode determination circuit, A semiconductor memory, comprising: a connection switching circuit that switches and applies one of a positive power supply voltage and an output voltage of the substrate voltage generation circuit to the p-type well layer in response to an external input signal. 4. The test mode determination circuit receives an inverted chip select signal, an inverted row address strobe signal, an inverted column address strobe signal, an inverted write enable signal, and an address signal as input signals, and receives the inverted chip select signal as an input. First CMO
S inverter, a second CMOS inverter receiving the inverted row address strobe signal, and a third CMOS inverter receiving the inverted column address strobe signal.
S inverter, a fourth CMOS inverter to which the inverted write enable signal is input, and the first CMO
A first NAND circuit to which an output signal of an S inverter, an output signal of the second CMOS inverter, an output signal of the third CMOS inverter, and an output signal of the fourth CMOS inverter are input; A fifth CMOS inverter which receives an output signal of the NAND circuit of FIG.
The address signal is input, the output signal of the fifth CMOS inverter is input as a positive clock, and the first NAN is input.
A clocked inverter that receives the output signal of the D circuit as an inverted clock input, and a latch circuit that connects the seventh and eighth CMOS inverters in a loop and holds the output signal of the clocked inverter. A ninth input circuit that receives the inverted chip select signal, the inverted row address strobe signal, the inverted column address strobe signal, the inverted write enable signal, and the output signal of the latch circuit as input signals, and receives the inverted chip select signal as input; CMO
An S inverter, a tenth CMOS inverter receiving the inverted column address strobe signal, and an eleventh CMOS receiving the inverted write enable signal.
An inverter, an output signal of the ninth CMOS inverter, an output signal of the tenth CMOS inverter, an output signal of the eleventh CMOS inverter, an output signal of the latch circuit, and an inverted row address strobe signal; A second NAND circuit, and the gate
, A power supply voltage is applied to the source, a p-type MOS transistor having a drain connected to the p-type well layer, and an output signal of the second NAND circuit is applied to the gate. 4. The semiconductor memory according to claim 3, further comprising an n-type MOS transistor having a source applied with a predetermined substrate voltage as a negative voltage and a drain connected to said p-type well layer.