JPH11306755A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a high-speed semiconductor storage by reducing the number of the elements of a column bank selection switch, layout area, and the load capacity of a column bank selection signal in an I/O line selection system. SOLUTION: In a system that is composed of a DRAM core that is a direct RAM bus specifications 64M.DRAM, is divided into a plurality of banks, and at the same time consists of a memory array where a plurality of the banks can be activated, and an interface logic circuit, can select two sense amplifiers SA0 and 1 (SA2 and 3) by one row selection signal line YS0 (YS1), and connects the sense amplifiers SA0-SA3 to two-system I/O lines IO0 and IO1 by one-system column bank selection signal line CBS, row selection switches SY0 and SY2 and SY1 and SY3 are commonly connected to column bank selection switches SC0 and SC1, respectively.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device technology, and more particularly, to a memory space divided into a plurality of banks.
The present invention relates to a technology effective when applied to a semiconductor memory device suitable for an input / output line selection method such as a Rambus (Rambus, USA) specification DRAM in which a plurality of banks can be activated simultaneously.

[0002]

2. Description of the Related Art As a technique studied by the present inventor, a DRAM as an example of a semiconductor memory device has a configuration in which a memory space is divided into a plurality of banks in order to cope with recent high performance of a memory system. Techniques that employ a method such as activation are known. For example,
In a direct rambus DRAM, the memory space is divided into 16 banks, and 4 banks can be activated at the same time.

However, read and write operations cannot be performed on two or more banks at the same time, and only one bank can be targeted. The bank for reading and writing is a column bank, and a signal for distinguishing this column bank from other activation banks is a column bank selection signal.
When performing read and write operations for a specific address selected by the column bank selection signal and the column selection signal, the selection switches of the addresses selected by both selection signals must be turned on at the same time.

[0004] Such a Rambus-specified DRAM is greatly different from, for example, a normal DRAM, a synchronous DRAM, and the like, in that the bus width is not increased, but on the contrary, the system hardware configuration is reduced as much as possible, and the hardware configuration of the system is made compact to increase the throughput. I did it. Since there is no dedicated address bus, they are used as request packets when accessed.
For example, it is necessary to send the data to the chip via the data bus and the control bus over three clock cycles. Therefore, the first access becomes slow.

Further, in order to stably control input / output of high-speed data, a PLL circuit is mounted on a chip to synchronize a circuit in the chip with an external clock. A sense amplifier in the memory array is used as a cache memory, and a circuit for determining whether the X address corresponding to the data stored therein matches that in the request packet is incorporated. Match (Ack) or mismatch (Nac)
k) The signal is returned to the memory controller prior to the data transfer.

[0006] As a technique relating to such a semiconductor memory device such as a Rambus DRAM, for example, 1
"Advanced Electronics I-9 Ultra LSI Memory" P34 published by Baifukan Co., Ltd. on November 5, 994.
4-P348, "Nikkei Electronics January 26 Issue", P139 issued by Nikkei BP on January 26, 1998
To P152 and the like.

[0007]

By the way, ordinary DR
In the AM, one memory array is activated on one column selection signal line. Therefore, the column selection switch does not require a column bank selection signal. When a plurality of banks are activated simultaneously on a signal line, it is necessary to connect a switch for a column selection signal and a switch for a column bank selection signal in series, so that the number of elements in a sense amplifier increases and the chip size increases. It is possible.

Accordingly, an object of the present invention is to provide a Rambus specification D
Provided is a semiconductor memory device capable of realizing high-speed operation by reducing the number of elements of a column bank selection switch in an input / output line selection method of a RAM or the like to reduce a layout area and a load capacity of a column bank selection signal. Is what you do.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0010]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, the semiconductor memory device of the present invention is applied to an input / output line selection system, and is controlled by a column bank selection signal for distinguishing between a column bank for reading and writing and another activation bank. In a configuration in which data read and write operations are performed for a specific address selected by a column bank selection switch and a column selection switch controlled by a column selection signal, the column bank selection switch is connected to a plurality of column selection switches. On the other hand, it is configured to be common.

In this configuration, the column bank selection switch is commonly connected to column selection switches controlled by different column selection signals, and when the column bank selection signal is a single system, the column bank selection signal is Are connected to different input / output lines, respectively, and in the case of a plurality of systems, the column bank selection switches controlled by the respective column bank selection signals are connected to the same input / output line. Things. Particularly, the present invention is applied to a DRAM having a Rambus specification.

Therefore, according to the semiconductor memory device, the number of elements of the column bank selection switch can be reduced, and the layout area can be reduced. In addition, the speed can be increased by reducing the load capacity of the column bank selection signal. As a result, it is possible to reduce the power consumption, chip size, speed, and noise of the product. This is because the number of elements of the column bank selection switch can be reduced.

Particularly, the present invention is effective for a DRAM having a direct rambus specification, and is applied to a DRAM adopting a configuration in which a memory space is divided into a plurality of banks and employing a method of simultaneously activating the memory, and an ASIC memory incorporating the same. can do.

[0015]

Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, the same members are denoted by the same reference numerals, and the description thereof will not be repeated.

(Embodiment 1) FIG. 1 is a schematic block diagram showing a semiconductor memory device according to Embodiment 1 of the present invention.
Is a configuration diagram showing a memory cell structure in the semiconductor memory device of the present embodiment, FIG. 3 is a schematic diagram showing a memory bank, FIG. 4 is a circuit diagram showing connections between sense amplifiers and input / output lines, and FIG. FIG. 6 is a circuit diagram showing the connection between the sense amplifier and the input / output lines of the comparative example corresponding to FIG. 4 of the embodiment, and FIG. 6 is a circuit diagram showing the sense amplifier.

First, a schematic configuration of the semiconductor memory device according to the present embodiment will be described with reference to FIG.

The semiconductor memory device of the present embodiment is, for example, a 64M DRAM of a direct rambus specification, is divided into a plurality of banks, and a plurality of banks can be activated at the same time. DRAM core including X address circuit 2, Y address circuit & input / output buffer 3, peripheral circuit 4, etc., clock circuit & control circuit 5, register 6, counter 7, status generator 8, and high speed interface 9
And an interface logic circuit consisting of
It is formed on one semiconductor chip by a well-known semiconductor manufacturing technique.

In this DRAM of the direct rambus specification, an X address packet for chip select, bank selection and X address designation is issued before data reading and writing are started. After the X access time, a Y address packet specifying a Y address or a command is issued. For example, if the command specified by the Y address packet is a read operation, data is sent to the memory bus after the Y access time. The X address packet stores three types of information, and specifies a chip, a bank, and an X address, respectively. The Y address packet is used to specify a chip, a bank, and a Y address.
Further, operations such as reading, writing, and precharging are specified by the operation code.

In the memory cell structure of the DRAM of the direct rambus specification, for example, as shown in FIG. 2, a memory array 1 is divided into banks BANK0 to BANK15.
A shared sense amplifier system is adopted in which adjacent banks BANK0 to BANK15 share a sense amplifier SA. Each bank BANK0-BANK15
Is supplied with the X address extracted from the packet and the precharge signal, and the X address extracted from the packet is also input to the sense amplifier SA. The sense amplifier SA is connected to a multiplexer for transmission to the data bus, and to a demultiplexer and a write buffer for input from the data bus.

For example, in this memory cell structure,
The sense amplifier S for the 155th row of the bank BANK5
Assuming that a command to be read to A is issued, a DRAM of 64 Mbit direct rambus specification stores 512 columns of 128-bit data per row. When a command is received, 128 bits are divided into 64 bits, and each is sent to the sense amplifier SA connected to the banks BANK4 and BANK6. In the case of the bank BANK5, 64 × 64 bits are sent to the sense amplifier SA sharing the bank BANK4, and the remaining 64 × 64 bits are sent to the sense amplifier SA sharing the bank BANK6. Then, each is read from the sense amplifier SA. After that, the data specified by the Y address packet is transferred to the input / output buffer, and a data packet of 18 bytes is created.

In the DRAM configured as described above, for example, as shown in FIG. 3, the banks BANK0 to BANK1 each having 16 memory spaces, as shown in FIG.
5, four banks BANK1 and BAN simultaneously
K7, BANK12 and BANK15 can be activated. However, since the read and write operations can be performed on only one bank, the column bank BANK7 for reading and writing is selected by a column bank selection signal (signal line CBS), and the other activation banks BANK1, BANK12, and BANK15 are selected. Be distinguished. Read and write operations are performed on a specific address selected by the column bank selection signal and the column selection signal (signal line YS).

In this read and write operation, the connection between the sense amplifier SA and the input / output line IO is established by, for example, one column selection signal line YS0 or two column selection signal lines YS1 as shown in FIG. , S
A1 or the sense amplifiers SA2 and SA3 can be selected, and the sense amplifiers SA0 to SA3 are connected to the two input / output lines IO0 and IO by one column bank selection signal line CBS.
The system is connected to O1. Sense amplifiers SA0 to SA connected to respective bit lines BL0 to BL3
Reference numeral 3 denotes column selection switches SY0 to SY3 controlled by column selection signal lines YS0 and YS1, and a column bank selection switch SC controlled by a column bank selection signal line CBS.
0, SC1 via input / output lines IO0, IO1, and column bank selection switches SC0, SC1 are commonly used for column selection switches SY0 to SY3. These bit lines BL0-BL3, input / output lines IO0, IO
O1 is a true / bar complementary signal line pair.

That is, in the configuration including the sense amplifiers SA0 to SA3, the column selection switches SY0 to SY4, and the column bank selection switches SC0 and SC1, the column selection switch SY0 and the column selection switch SY2 are commonly connected to the column bank selection switch SC0. , The column selection switch SY1 and the column selection switch SY3 are commonly connected to the column bank selection switch SC1. For example, when column selection signal line YS0 is selected, sense amplifier SA0 and sense amplifier SA1 are connected to column selection switch SY, respectively.
0 and a column bank selection switch SC0, and a column selection switch SY1 and a column bank selection switch SC1 are connected to the input / output lines IO0 and IO1, respectively.
When the column selection signal line YS1 is selected, the sense amplifiers SA2 and SA3 are respectively connected to the column selection switch SY2 and the column bank selection switch SC0, and the column selection switch SY3 and the column bank selection switch SC1.
Are connected to the input / output line IO0 and the input / output line IO1, respectively.

The connection system shown in FIG. 4 is different from the embodiment in which the column bank selection switches SC0 to SC3 shown in FIG. 5 are not shared as a comparative example of the present embodiment, for example, the column selection switch SY and the column bank selection switch. SC
Can be reduced from 16 to 12 MOS transistors, and a reduction of 12/16 = 3/4 is possible. Further, the number of MOS transistors connected to the column bank selection signal line CBS is reduced from eight to four, which is halved, and high speed and low power can be realized.

The sense amplifier SA is, for example, shown in FIG.
The shared sense amplifier method is adopted as shown in
Adjacent memory cells share a sense amplifier SA. In this method, the shared sense amplifier separation signal line SHR * on the selected memory cell side is set to the internal boosted power supply voltage VPP and the bit lines BL * T (true), BL * B
(Bar) to the sense amplifier SA, and the shared sense amplifier separation signal line S on the non-selected memory cell side.
HR * is set to VSS, and the bit lines BL * T and BL * B are separated from the sense amplifier SA.

In FIG. 6, a sense amplifier SA includes a first isolation circuit including cut NMOS transistors TN1 and TN2, and a CMO including PMOS transistors TP1 and TP2 and NMOS transistors TN3 and TN4.
The circuit includes an S amplifier circuit, a precharge circuit including NMOS transistors TN5 to TN7, and a second separation circuit including cut NMOS transistors TN8 and TN9. The first and second separation circuits are cut NMOS transistors TN1, TN2, TN8, T by shared sense amplifier separation signal lines SHRL and SHRR, respectively.
N9 is gate-controlled, and connects the sense amplifier SA to one of the memory cells. The high-side and low-side sense amplifier drive lines CSP and CSN are connected to the CMOS amplifier circuit. The precharge circuit is gate-controlled by a bit line precharge signal line PCB and supplies a bit line precharge voltage HVC.

Next, the operation of the present embodiment will be described with reference to FIGS. 3 and 4 regarding the connection between the sense amplifier SA and the input / output line IO in the read and write operations.

In the read and write operations, for example, of the activated banks shown in FIG. 3, the column bank selection signal line CBS is activated to activate the column bank BAN.
Select K7. At the same time, this column bank BANK7
Is activated to select the sense amplifier SA0 of the bit line BL0 and the sense amplifier SA1 of the bit line BL1 shown in FIG.

One sense amplifier SA0 is connected to an input / output line IO0 via a column selection switch SY0 and a column bank selection switch SC0. The other sense amplifier SA
1 is connected to the input / output line IO1 via the column selection switch SY1 and the column bank selection switch SC1. As a result, the bit lines BL0 and BL1 of the selected memory cell in the column bank are connected to the input / output lines IO0 and IO1, and data can be read from and written to the memory cell.

For example, at the time of reading, bit lines BL0 and BL1 are read from the memory cells of the selected column bank.
Are read and sensed by the sense amplifiers SA0 and SA1, and input / output lines IO0 and IO0 are output via the column selection switch SY0 and the column bank selection switch SC0 and the column selection switch SY1 and the column bank selection switch SC1, respectively. It can be read to IO1. Similarly, at the time of writing, data from the input / output lines IO0 and IO1 can be written to the memory cells.

Therefore, according to the semiconductor memory device of the present embodiment, the column selection switch SY0 and the column selection switch SY2
Is connected to the column bank selection switch SC0, the column selection switch SY1 and the column selection switch SY3 are commonly connected to the column bank selection switch SC1, and the column bank selection switches SC0 and SC1 are shared.
Since the number of elements of the column bank selection switch SC can be reduced, the layout area can be reduced.
In addition, since the number of column bank selection switches SC connected to the column bank selection signal line CBS is reduced, the load capacity of the column bank selection signal is reduced, so that access can be speeded up.

(Embodiment 2) FIG. 7 is a circuit diagram showing a connection between a sense amplifier and input / output lines in a semiconductor memory device according to Embodiment 2 of the present invention, and FIG.
FIG. 9 is a circuit diagram showing a connection between a sense amplifier and an input / output line of a comparative example corresponding to FIG.

The semiconductor memory device of the present embodiment has a direct RAM bus specification of 64 M · D, as in the first embodiment.
A RAM, a memory array 1, an X address system circuit 2,
A DRAM core including a Y address circuit & input / output buffer 3, a peripheral circuit 4, and the like, and an interface logic circuit including a clock circuit & control circuit 5, a register 6, a counter 7, a status generator 8, a high-speed interface 9, and the like. The second embodiment is different from the first embodiment in that the present embodiment is applied to a connection example of one input / output line instead of two input / output lines.

That is, in the present embodiment, the connection between the sense amplifier SA and the input / output line IO is made by connecting two sense amplifiers with one column selection signal line YS0 or one column selection signal line YS1, as shown in FIG. SA0, SA1 or sense amplifiers SA2, SA3 can be selected, and sense amplifiers SA0-SA3 are connected to one input / output line IO0 by two column bank selection signal lines CBS0, CBS1. Select signal line CB
S0 and a column bank selection signal line CBS1 are divided into two systems, a column bank selection switch SC0 controlled by one column bank selection signal line CBS0, and a column bank selection switch SC1 controlled by the other column bank selection signal line CBS1. Through each of the input / output lines IO0
It is connected to the.

For example, a column bank selection signal line CSB
0, when the column selection signal line YS0 is selected, only the sense amplifier SA0 is connected to the input / output line IO0 via the column selection switch SY0 and the column bank selection switch SC0. When the column selection signal line YS1 is selected, only the sense amplifier SA2 is connected to the input / output line IO0 via the column selection switch SY2 and the column bank selection switch SC0. Similarly, when the column bank selection signal line CSB1 and the column selection signal line YS0 are selected, the sense amplifier SA
1 is connected to the input / output line IO0 via the column selection switch SY1 and the column bank selection switch SC1, and when the column selection signal line YS1 is selected, the sense amplifier SA3
Only the column selection switch SY3 and the column bank selection switch SC1 are connected to the input / output line IO0.

The connection system shown in FIG. 7 is different from the embodiment shown in FIG. 8 in which the column bank selection switches SC0 to SC3 are not shared with each other. The number of transistors can be reduced from eight to four, and the number of column selection signal lines YS can be reduced from four to two. Further, since the number of MOS transistors connected to the column bank selection signal line CBS can be reduced, high speed and low power can be achieved.

Therefore, according to the semiconductor memory device of the present embodiment, the column bank selection signal line CBS0 and the column bank selection signal line CBS1 for one input / output line IO0.
The column is connected to the input / output line IO0 via a commonly connected column bank selection switch SC0 and a column bank selection switch SC1 controlled by the respective column bank selection signal lines CBS0 and CBS1. Since the number of column selection signal lines YS can be reduced in addition to the number of elements of the bank selection switch SC, the layout area can be reduced. In addition, since the number of column bank selection switches SC connected to the column bank selection signal line CBS is reduced, the load capacity of the column bank selection signal is reduced, so that access can be speeded up.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the embodiment, and various modifications may be made without departing from the gist of the invention. It goes without saying that it is possible.

For example, in the above-described embodiment, a description has been given of an example of a direct RAM bus specification 64M DRAM in which the memory space is divided into 16 banks. However, the present invention is not limited to this. It is also widely applicable to DRAMs, such as Rambus specification DRAMs, which have a tendency toward 256 Mbits, and have a tendency to increase the capacity, and the effect of the present invention can be further enhanced by adopting such a configuration of multiple banks and large capacity. It gets bigger and bigger.

In addition to the direct RAM bus specification DRAM, the memory space is divided into a plurality of banks.
The present invention can also be applied to a DRAM adopting a technique such as activation at the same time, and an ASIC memory incorporating the DRAM.

[0042]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1) Since the column bank selection switch is shared by a plurality of column selection switches, the number of elements of the column bank selection switch can be reduced, so that the layout area can be reduced. Become.

(2) According to (1), the load capacity of the column bank selection signal can be reduced by reducing the number of selection switches connected to the column bank selection signal line. It becomes possible to plan.

(3) When there are a plurality of column bank selection signals, the number of column selection signal lines can be reduced in addition to the number of column bank selection switches, so that the layout area can be further reduced. Become.

(4) According to the above (1) to (3), the memory space is divided into a plurality of banks, and a plurality of banks can be activated at the same time. It is possible to realize a reduction in size, an increase in access speed, and a reduction in power consumption and noise.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram showing a memory cell structure in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 3 is a schematic diagram showing a memory bank in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 4 is a circuit diagram showing connections between sense amplifiers and input / output lines in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 5 is a circuit diagram showing connections between sense amplifiers and input / output lines of a comparative example corresponding to FIG. 4 of the first embodiment of the present invention;

FIG. 6 is a circuit diagram showing a sense amplifier in the semiconductor memory device according to the first embodiment of the present invention;

FIG. 7 is a circuit diagram showing connections between sense amplifiers and input / output lines in a semiconductor memory device according to a second embodiment of the present invention;

FIG. 8 is a circuit diagram showing connections between sense amplifiers and input / output lines of a comparative example corresponding to FIG. 7 of the second embodiment of the present invention;

[Explanation of symbols]

1 Memory Array 2 X Address Circuit 3 Y Address Circuit & I / O Buffer 4 Peripheral Circuit 5 Clock Circuit & Control Circuit 6 Register 7 Counter 8 Status Generator 9 High Speed Interface BANK Bank SA Sense Amplifier CBS Column Bank Select Signal Line YS Column Select Signal line IO I / O line BL Bit line SY Column select switch SC Column bank select switch TN NMOS transistor TP PMOS transistor SHRL, SHRR Shared sense amplifier separation signal line CSP, CSN Sense amplifier drive line PCB Bit line precharge signal line

Claims (5)

[Claims] 1. The memory space is divided into a plurality of banks,
A semiconductor memory device in which a plurality of banks can be activated at the same time. The semiconductor memory device has a column bank selection signal for distinguishing between a column bank for reading and writing and another activation bank, and is controlled by the column bank selection signal. A column bank selection switch, and a column selection switch controlled by a column selection signal, for performing data read and write operations for a specific address selected by the column bank selection switch. A semiconductor memory device shared by a selection switch. 2. The semiconductor memory device according to claim 1, wherein said column bank selection switches controlled by said column bank selection signals are commonly connected to column selection switches controlled by different column selection signals. A semiconductor memory device characterized in that: 3. The semiconductor memory device according to claim 2, wherein said column bank selection signal comprises one system, and a plurality of column bank selection switches controlled by said column bank selection signal are respectively connected to different input / output lines. A semiconductor memory device which is connected. 4. The semiconductor memory device according to claim 2, wherein said column bank selection signal comprises a plurality of systems, and column bank selection switches controlled by each column bank selection signal are connected to the same input / output line. A semiconductor memory device characterized in that: 5. The semiconductor memory device according to claim 1, wherein said semiconductor memory device is a Rambus DRAM.