JPH11306029A - Device, method and medium for interruption - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an interruption processing device, its method and its medium which can improve a processing speed. SOLUTION: A history of interruption instructions by an input 32 for having interruption processing executed is stored in a storage part 28 of an interruption means 26. Based on the stored history, the interruption means 26 predicts an interruption occurrence timing of the interruption processing from the next time onward. Based on this predicted generation timing, the interruption means 26 has a transfer demand generation part 30 demand transfer of an interruption processing program to a cache memory 20 from a main storage means. Receiving this demand, a cache means 18 has the demanded interruption processing program transferred to the cache memory 20 and has a processing means 12 execute it. As the interruption processing program is made to transfer in the interruption predicted based on the history, it is possible to reduce a processing time of a header part spent for transfer as in the case of transferring it to the cache means 18 at the time of an occurrence of the interruption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an interrupt processing apparatus, method, and medium, and more particularly, to an interrupt processing apparatus, method, and medium for performing interrupt processing during execution of main processing.

[0002]

2. Description of the Related Art In recent years, central processing units (hereinafter referred to as C) have been installed in vehicles.
And an electronic control unit (hereinafter, referred to as an ECU) including a memory device.
The CU controls an electronic control device mounted on the vehicle.

[0003] As is well known, the processing speed of a CPU is RA
It is faster than the processing speed of general memory devices including M and the like. For this reason, the processing speed of the CPU is limited by the processing speed of the memory device. Therefore, recently, a technique of increasing the processing speed by providing a memory having a small capacity but having a high processing speed known as a cache device between the CPU and the memory device has been put to practical use.

In a cache device, when data is transferred, the CP
Although the processing speed is buffered by the memory provided between the U and the memory device, access to the memory device is performed by an instruction from the CPU, and as a result, the processing time increases. Therefore, as is known in the data prefetching method, it is known to predict the next instruction to be executed, prefetch the predicted instruction or required data, or prefetch the instruction or data at a fixed address. ing.

However, since the prefetching is a fixed prefetching of a branch instruction or a fixed address, the prefetching accuracy is low. Therefore, there is known a look-ahead control device that stores, as a history, the address of the next access prediction for an access request and refers to the history to pre-read the data at the address of the access prediction for the access information (Japanese Patent Laid-Open No. 6-16).
No. 8119).

[0006]

SUMMARY OF THE INVENTION However, CPU
In the process according to, an interrupt process is usually performed, but the interrupt process cannot be predicted. Therefore, in the prefetch control device, when an interrupt process occurs, in the interrupt process, the difference between the processing speed of the CPU and the processing speed of the memory device directly affects the overall processing speed.

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt processing apparatus, method and medium capable of improving the processing speed in consideration of the above fact.

[0008]

In order to achieve the above object, according to the present invention, there is provided an interrupt processing apparatus comprising: a main processing program describing a main processing comprising instructions and data;
Main storage means for storing an interrupt processing program describing an interrupt processing consisting of an instruction and data for interrupting and performing other processing during execution of the processing, and processing means for executing a main processing or an interrupt processing based on the instruction and data A cache means for reading and storing the requested interrupt processing program, executing the stored interrupt processing program in the processing means, and storing an input history for executing the interrupt processing occurring during the main processing. And interrupt means for predicting the timing of occurrence of interrupt processing based on the stored history and requesting execution of processing for reading an interrupt processing program based on the predicted occurrence timing.

According to a second aspect of the present invention, in the interrupt processing apparatus according to the first aspect, the cache means causes the stored interrupt processing program to be resident when the request is within a predetermined time interval. It is characterized by having resident means.

According to a third aspect of the present invention, there is provided a main processing program in which a main processing including instructions and data is described, and an interrupt processing in which interrupt processing including instructions and data for interrupting and performing other processing during execution of the processing are described. An interrupt processing method for performing interrupt processing during execution of main processing by a computer programmed by a program,
A process of storing an input history for executing an interrupt process occurring during the main process, predicting an interrupt process occurrence timing based on the stored history, and reading an interrupt process program based on the predicted occurrence timing It is characterized by including an interruption step for requesting execution, and a cache step for reading and storing the requested interrupt processing program, and for executing the stored interrupt processing program.

According to a fourth aspect of the present invention, there is provided a recording medium recording an interruption processing program for causing an interruption processing during execution of a main processing program in which a main processing consisting of instructions and data is described by a computer, Storing an input history for executing the processing and predicting the occurrence timing of the interrupt processing based on the stored history, and requesting a processing execution to read an interrupt processing program based on the predicted occurrence timing; The requested interrupt processing program is read and stored, and the stored interrupt processing program is executed.

FIG. 1 is a block diagram showing the principle of the present invention. As shown in FIG. 1, the interrupt processing apparatus 10 of the present invention
Is constituted by a microcomputer including a processing unit 12 such as a CPU and a main storage unit 14 such as a RAM & ROM, and each is connected by a bus 38 so that commands and data can be exchanged. The cache means 18 and the interrupt means 26 are connected to the bus 38.
Note that the main storage device 14 stores a main processing program and an interrupt processing program 16. The cache unit 18 includes a cache memory 20 for temporarily storing at least a part of the program and a main storage unit 14.
From the cache memory 20 to the cache memory 20. Further, the interrupt means 26 is provided with a storage unit 28 of the interrupt occurrence history.
And a transfer request generating unit 30. It is assumed that the interruption is made by the input from the input 32.

During the main processing by the main processing program, the interrupt processing is executed by the interrupt instruction by the input 32 for executing the interrupt processing. The input for executing the interrupt processing generated during the main processing is performed. The history of 32 is stored in the storage unit 28 of the interrupt unit 26. Based on the stored history, the interrupt unit 26 predicts an interrupt generation timing from the next time of the interrupt processing. Based on the predicted occurrence timing, the interrupt unit 26 requests the transfer request generation unit 30 to execute the process of reading the interrupt processing program from the main storage unit, that is, transfer. In response to this request, the cache unit 18 reads and stores the requested interrupt processing program. That is, the interrupt processing program 16 stored in the main storage unit 14 is transferred to the cache memory 20. At the same time, the stored interrupt processing program is executed by the processing unit 12. The processing unit 12 executes an interrupt process based on the instruction and the data. As described above, the interrupt occurrence timing from the next time of the interrupt processing is predicted based on the stored history, and at the predicted timing, the interrupt processing program is transferred from the main storage means to the cache means, and the processing shifts to the execution of the interrupt processing. The processing time of the header portion required for the transfer can be reduced as in the case where the data is transferred to the cache unit at the time when the interrupt occurs.

When the interrupt processing program is transferred from the main storage means 14 to the cache memory 20 of the cache means 18, when the same interrupt processing is performed in a short time, the processing load increases if the transfer is performed every time. I do. Therefore, a resident means 24 for resident storing the stored interrupt processing program when the request is within a predetermined time interval is provided in the cache control unit 22 of the cache means 18, as described in claim 2. Let it.
In this way, even when the same interrupt processing is performed in a short time, the processing is not transferred every time, but resides resident, so that the processing load can be reduced.

The interrupt processing performed during the execution of the main processing can be executed by an interrupt processing method according to the following steps. More specifically, as described in claim 3, a main processing program describing a main process consisting of instructions and data, and an interrupt process consisting of an instruction and data for interrupting and executing other processes during execution of the process are described. An interrupt processing method for performing interrupt processing during execution of main processing by a computer programmed by an interrupt processing program, wherein an input history for executing an interrupt processing occurring during the main processing is stored and stored in the stored history. An interrupt process for requesting execution of a process of reading an interrupt processing program based on the predicted occurrence timing, reading and storing the requested interrupt processing program, and storing the stored interrupt. And a cache step for executing the processing program. And wherein the door.

The interrupt processing for interrupting and executing during the execution of the main processing executed by the main processing program can be stored in a recording medium having the interrupt processing program recorded thereon. Specifically, a recording medium recording an interrupt processing program for performing an interrupt processing during execution of a main processing program in which a main processing including instructions and data is described by a computer, wherein an input for executing the interrupt processing is provided. Of the interrupt processing is predicted based on the stored history, and a request is made to request execution of a processing to read the interrupt processing program based on the predicted occurrence timing. Read and store, and execute the stored interrupt processing program.

That is, a floppy disk unit (FDU) 34 into which a floppy disk 36 as a recording medium can be inserted and removed can be connected to the bus 38. This F
The processing program may be executed from the floppy disk 36 by making the DU 34 readable and writable to the floppy disk 36. That is, the processing program may be recorded on the floppy disk 36 in advance without storing the processing program in the main storage unit 14, and the processing program recorded on the floppy disk 36 may be executed via the FDU 34. It may be stored (installed) in the storage unit 14. Further, a large-capacity storage device (not shown) such as a hard disk device may be connected, and the processing program recorded on the floppy disk 36 may be stored (installed) in the large-capacity storage device (not shown) and executed. .
As a recording medium, there is an optical disk such as a CD-ROM and a magneto-optical disk such as an MD and an MO. When these are used, instead of the FDU 24 or further,
Any device such as a D-ROM device, an MD device, and an MO device may be used.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In the present embodiment, the present invention is applied to processing in an engine control ECU (electronic control device).

As shown in FIG. 2, the engine control device 40 of the present embodiment includes an engine control ECU 42. The engine control ECU 42 includes a microcomputer 44 and a waveform shaping circuit 64. The microcomputer 44 uses C
PU 46, RAM 48 for temporarily storing variables and the like, flash memory 50 such as E ² PROM for storing processing routines, high-speed operation cache memory 52 for storing at least a part of routines, and cache for controlling cache memory 52 The control unit includes a control unit 54, an interrupt control unit 56, an input capture 60 for generating and outputting an input signal for executing an interrupt process from an input signal, and a timer 62. These elements are connected by a bus 58 so that data and commands can be exchanged. Note that an engine rotation sensor 66 is connected to the input capture 60 via a waveform shaping circuit 64.

A floppy disk unit (FDU) 34 into which a floppy disk 36 can be inserted and withdrawn can be connected to the microcomputer 44 of the engine control ECU 42. As described above, by accessing the floppy disk 36 using the FDU 34, The processing may be executed from the floppy disk 36. Also, FD
The present invention is not limited to the U34 and the floppy disk 36, but includes a large-capacity magnetic disk (for example, a hard disk), an optical disk such as a CD-ROM, and a magneto-optical disk such as an MD or MO. Or even hard disk drive,
Any device such as a CD-ROM device, an MD device, and an MO device may be used.

As shown in FIG. 3, the flash memory 48
Functions as a main storage device, a main routine (main processing program) in which main processing (main processing) of the engine control ECU 42 is described by instructions and data, and an interrupt including instructions and data for interrupting the main processing and performing other processing. A plurality of interrupt routines (interrupt processing programs) describing processing are stored.

Next, the operation of the present embodiment will be described. When power is applied to the engine control device 40, the CPU 46
Executes the main processing according to the main routine shown in FIG. That is, the main processing is executed in step 100 until the power is turned off (until a positive determination is made in step 102).

During execution of the main processing, an interrupt processing is executed by a signal from the engine rotation sensor 66.
That is, the signal from the engine rotation sensor 66 is shaped by the waveform shaping circuit 64, and the input capture 60 generates and outputs an interrupt signal for executing an interrupt process. This interrupt signal corresponds to the signal Int in FIG.
In the example of FIG. 8, the interrupt signals are shown in chronological order, the current interrupt signal is Int _n , the next interrupt signal is Int _{n + 1} ,
The previous interrupt signal is Int _n-1 , the previous previous interrupt signal is In
Indicated by t _n-2 . When this interrupt signal is input, interrupt processing is executed according to the interrupt routine shown in FIG. That is, an interrupt process is performed in step 104. It should be noted that this step 104 includes designating a corresponding interrupt process from a plurality of interrupt processes. In the present embodiment, the engine rotation sensor 66
Interrupt processing based on the output of

FIG. 6 shows the processing executed in the interrupt control unit 56. When an interrupt is instructed, an affirmative determination is made in step 110 of FIG.
An interrupt occurrence history is stored. The interrupt occurrence history is the time at which the interrupt occurred, and the current time of the timer 62 is read and accumulated to store the interrupt occurrence history. For this reason, the interrupt control unit 56 has a storage area corresponding to the storage unit 28 in FIG. 1 for storing an interrupt occurrence history. In the next step 114, the cycle T is calculated. The period T is a time until the current interrupt from the previous interrupt, this is the period T _n. That is,
The cycle _Tn is calculated with reference to the stored interrupt occurrence history.
The other periods are the previous period T _n-1 and the next period T
_{n + 1} ,... to be obtained. Note that the previously calculated cycle may be stored.

In the next step 116, the transmission time Tx of the transfer request for requesting the transfer of the interrupt processing routine from the flash memory 50 to the cache memory 52 is stored in a register (not shown) in the interrupt control unit 56 (may be the RAM 48). Determine whether it is set. If it has been reset, the result in step 116 is negative, and in the next step 118, it is determined whether or not the cycle _Tn has periodicity. This determination is made the current period T _n, the periodicity Yes when within time difference predetermined by comparing the period T _n-1 of at least the last. If the determination in step 118 is affirmative, in the next step 120, the transmission time Tx (= Tn-α) of the transfer request is calculated, and in the next step 1
At 22, the transmission time Tx is set.

The transmission time Tx of the transfer request is a transfer start time for transferring the interrupt processing routine from the flash memory 50 to the cache memory 52 before the next interrupt instruction. Has been at least shorter. This time α
The advance obtained in advance by experiment or calculation, by subtracting the time α from the cycle T _n, outgoing time transfer request Tx
Is calculated. The time required for the transfer may be measured in this routine, and a time longer than the measured time may be set as the time α.

In the next step 124, a transfer request is output to the cache control unit 54, and the next step 138
Resets the counter C and starts time measurement for outputting a transfer request. That is, the counter C is a time measurement counter that works with the timer 62.

Step 124 is the transfer request generation unit 3 in FIG.
It corresponds to 0. In response to the output of the transfer request, the cache control unit 54 transfers an interrupt processing routine from the flash memory 50 to the cache memory 52 as described later.

If the transmission time Tx has been set and the result in step 116 is affirmative, the routine proceeds to step 126, where it is determined whether or not there is periodicity. If there is no periodicity, the determination is negative and the routine proceeds to step 128. In step 128, the transmission time Tx is reset, and in the next step 132, a transfer request is output to the cache control unit 54.

On the other hand, when an interrupt is not instructed, a negative determination is made in step 110 of FIG.
34, the counter C indicates the transmission request transmission time T
It is determined whether or not it matches x. If they do not match, the result in step 134 is NO, and the routine proceeds to step 138. On the other hand, when C = Tx, the result in step 134 is affirmative, and in the next step 136, the cache control unit 54
Outputs a transfer request to.

As described above, in the case of an interrupt having periodicity, it is predicted that an interrupt process will be instructed, and a transfer request is issued to the cache control unit 54 before the interrupt process is instructed. The processing is performed so that the transfer of the interrupt processing routine is completed before the processing is instructed. Therefore, when the interrupt processing is instructed, the interrupt processing routine has been transferred to the cache memory 52, so that the processing can be started immediately, and it is not necessary to provide a header part by the transfer.

The cache control unit 54 executes the processing routine shown in FIG. First, in step 140,
It is determined whether or not a transfer request has been made. If there is no transfer request, the determination in step 140 is negative, and this routine ends.
On the other hand, when a transfer request is made, the result in step 140 is affirmative, and in the next step 142, it is determined whether or not the refresh of the cache memory 52 is prohibited. Although the contents of the cache memory 52 can be cleared by refreshing, a state in which clearing of the contents of the cache memory 52 by refreshing is prohibited is referred to as a state in which refreshing is prohibited. In addition,
The state in which the clearing of the contents of the cache memory 52 is prohibited is equivalent to making the program resident because the contents in the memory are stored as it is.

When the refresh is prohibited, the result in step 142 is affirmative, and the process proceeds to step 14
Proceed to 6. On the other hand, if the refresh is not prohibited, the result in step 142 is negative, and the process proceeds to the next step 144, where the interrupt processing program is read from the flash memory 50 and transferred to the cache memory 52.

In the next step 146, it is determined whether or not Tn-α <β. The determination in step 146 is for determining whether to suppress the process of repeating the transfer within a short time. That is, the cycle is short, and it is useless to transfer the same interrupt processing routine every short cycle. For this reason, if the transmission time Tx of the transfer request is shorter than the predetermined time β, the transfer time can be reduced and the transfer load can be reduced by making the interrupt processing routine resident in the cache memory without performing the transfer. be able to.

Therefore, if Tn-α <β, the result in step 146 is affirmative, and the process proceeds to step 148 to make the interrupt processing routine resident in the cache memory, where the cache memory 52 is set to the state in which refresh is prohibited. . On the other hand, if Tn-α ≧ β, the determination in step 146 is negative, and it is unnecessary to make the interrupt processing routine resident in the cache memory. To release.

As described above, when the transmission time Tx of the transfer request is short, the transfer request can be resident in the cache memory without transferring the interrupt processing routine.
The transfer time can be reduced, and the transfer load can be reduced.

FIG. 8 shows the transfer of the interrupt processing routine from the flash memory 50 to the cache memory 52 by a block 70 (meshed line), and the interrupt processing of the CPU 46 in accordance with the transferred interrupt processing routine is shown by a block 72 (shaded line). Part).

If the interrupt processing of the previous and previous interrupt signal Int _n-2 shown in FIG. 8 is the first time, there is no interrupt before, so the interrupt processing routine is not transferred to the cache memory 52. Therefore, the previous and previous interrupt signals Int
After the interrupt processing routine is transferred from the flash memory 50 to the cache memory 52 at the time of occurrence of the interrupt due to _n-2, according to the transferred interrupt processing routine,
The CPU 46 performs an interrupt process. Further, in the previous interrupt processing of the interrupt signal Int _n−1 , since the interrupt processing has no periodicity, the processing is performed in the same manner as in the previous interrupt processing.

In the interrupt processing of the current interrupt signal Int _n shown in FIG. 8, since the cycle T _n-1 by the previous interrupt and the current cycle T _n have periodicity, the cache memory 52
, An interrupt processing routine is transferred, and the transmission request transmission time Tx (= T _n -α) is set. Thus, when the next interrupt instruction of the interrupt signal Int _{n + 1} is issued, the transfer of the interrupt processing routine is completed. Therefore, in the next interrupt by the interrupt signal Int _{n + 1} , there is no transfer time, and the interrupt process can be executed immediately after the interrupt signal Int _{n + 1} .

FIG. 9 shows, as an image, a comparison result between the conventional interrupt processing device and the interrupt processing device of the present embodiment when a periodic interrupt is made.

A signal from the engine rotation sensor 66 (FIG. 9)
Input capture 60
Signal Int (time t1, t2, t
According to (3, t4), the interrupt processing routine is conventionally transferred from the flash memory 50 to the cache memory 52 (block 70), and the interrupt processing routine stored in the cache memory 52 is executed (block 72). For this reason, the transfer time induces a time delay as a header portion.
On the other hand, in the present embodiment, a periodic interrupt is predicted from the interrupt occurrence history, and the transmission time Tx of the transfer request is output in a time shorter than the cycle T. Therefore, at the time of the interrupt signal Int, the transfer of the interrupt processing routine from the flash memory 50 to the cache memory 52 has been completed. Thereby, in the present embodiment, at the time of the interrupt signal Int,
The interrupt processing routine stored in the cache memory 52 can be immediately executed (block 72), and no time delay occurs.

When the transmission time Tx of the transfer request is short, the cache memory 52 is set in the refresh-inhibited state, so that the transfer of the interrupt processing routine from the flash memory 50 to the cache memory 52 can be omitted. (Gaze line part) becomes unnecessary. This can further reduce the processing load.

[0043]

As described above, according to the first aspect of the present invention, the interrupt occurrence timing from the next interrupt processing is predicted based on the stored history, and the interrupt processing program is mainly executed at the predicted timing. Since the transfer is performed from the storage unit to the cache unit and the process shifts to the execution of the interrupt processing, the processing time of the header portion required for the transfer can be reduced as in the case where the transfer is performed to the cache unit when an interrupt occurs. .

According to the second aspect of the present invention, when the request is within a predetermined time interval, the stored interrupt processing program can be resident and stored in the cache means by the resident means. Even if the interrupt processing is performed in a short period of time, there is an effect that the processing load can be reduced because it is resident without being transferred each time.

[Brief description of the drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a block diagram illustrating a schematic configuration of an engine control device according to the present embodiment.

FIG. 3 is an explanatory diagram for explaining the inside of a flash memory;

FIG. 4 is a flowchart illustrating a flow of a main process.

FIG. 5 is a flowchart illustrating a flow of an interrupt process.

FIG. 6 is a flowchart illustrating a flow of processing of an interrupt control unit.

FIG. 7 is a flowchart illustrating a flow of processing of a cache control unit.

FIG. 8 is an image diagram showing, in chronological order, transfer and processing of an interrupt processing routine in the interrupt processing apparatus of the present embodiment.

FIG. 9 is an image diagram showing a comparison result between the related art and the present embodiment when a periodic interruption is performed.

[Description of Signs] 10 interrupt processing device 12 processing means 14 main storage means 18 cache means 26 interrupt means

Claims (4)

[Claims] 1. A main memory for storing a main processing program describing a main processing composed of instructions and data, and an interrupt processing program describing an interrupt processing composed of instructions and data for interrupting and performing other processing during execution of the processing. Means for executing main processing or interrupt processing based on instructions and data; cache means for reading and storing a requested interrupt processing program, and causing the processing means to execute the stored interrupt processing program; A process of storing an input history for executing an interrupt process occurring during the main process, predicting an interrupt process occurrence timing based on the stored history, and reading an interrupt process program based on the predicted occurrence timing. Interrupt processing means for requesting . 2. The interrupt processing according to claim 1, wherein said cache means has a resident means for resident storing said stored interrupt processing program when said request is within a predetermined time interval. apparatus. 3. A computer programmed with a main processing program describing a main processing consisting of instructions and data, and an interrupt processing program describing an interrupt processing consisting of instructions and data for interrupting and performing other processing during execution of the processing. An interrupt processing method for performing an interrupt process during execution of a main process, comprising storing an input history for executing an interrupt process occurring during the main process, and predicting an occurrence timing of the interrupt process based on the stored history. And an interrupt step of requesting execution of a process of reading an interrupt processing program based on the predicted occurrence timing, a cache step of reading and storing the requested interrupt processing program, and executing the stored interrupt processing program, Interrupt characterized by including Processing method. 4. A recording medium recording an interrupt processing program for causing an interrupt processing during execution of a main processing program in which a main processing consisting of instructions and data is described by a computer, wherein an input for executing the interrupt processing is provided. Of the interrupt processing is predicted based on the stored history, and a request is made to request execution of a processing to read the interrupt processing program based on the predicted occurrence timing. A recording medium on which an interrupt processing program is read and stored, and the stored interrupt processing program is executed.