JPH11304889A - Test pattern generating device for semiconductor integrated circuit, and test pattern generating method for the semiconductor integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate a test pattern effective for a stable test of a semiconductor integrated circuit, especially a semiconductor integrated circuit output buffer characteristics test or input buffer characteristics test. SOLUTION: This semiconductor integrated circuit test pattern generating device obtains a combination pattern, comprising a test pattern of which output signal consists of a logic 0 or a logic 1 from combination patterns generated by a combination pattern generating part 10 by a combination pattern obtaining part 11. In the obtained combination pattern, the test pattern is deleted, or execution order is changed in such a way that an output simultaneous change number satisfies a specified allowable output change number for generating the test pattern, in which the output simultaneous change number in a semiconductor integrated circuit, is restricted by a combination pattern determination part 13.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for generating a test pattern for testing a semiconductor integrated circuit and a method for generating a test pattern for a semiconductor integrated circuit. In particular, the present invention relates to an apparatus and a method for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit in which the execution order of test patterns can be changed.

[0002]

2. Description of the Related Art As a conventional technique, Japanese Patent Laid-Open Publication No.
7 discloses an input data generation method. JP-A-2-90077 is an invention for generating input data while suppressing the number of simultaneous changes of output signals of a semiconductor integrated circuit. FIG.
Fig. 1 shows an input data generation procedure in the related art. First,
As the first step (100), it is assumed that all possible faults occur in an LSI (semiconductor integrated circuit). As a second step (101), one fault is selected from all the faults assumed in the first step (100). As a third step (102), input data is generated for the fault selected in the second step. The fourth step (10
As 4), the input data generated in the third step (102) is stored in the memory. The first to fourth steps are repeated to create input data for all the faults assumed in the first step, and then, as a fifth step (105), for all the generated input data, prohibition on the number of simultaneous changes in output Tick condition. Sixth
Step (106) and seventh step (107)
When the prohibition condition is satisfied, the fourth step (104)
To rearrange the input data stored in the memory. If all the prohibition conditions are satisfied for the rearranged input data, the process ends.

[0003]

As described above, in the prior art, input data is rearranged to generate input data in which the number of simultaneous changes in output is suppressed. However, in the input buffer characteristic test and the output buffer characteristic test, it is necessary that input signals and output signals of all the semiconductor integrated circuits toggle between logic 0 and logic 1. Since only the description of the input data generation that suppresses the above is described, there is a problem that the characteristic test of the input buffer and the output buffer cannot be performed.

In a test of a semiconductor integrated circuit, if a large number of output signals of the semiconductor integrated circuit simultaneously change, the semiconductor integrated circuit may malfunction due to an electrical factor of ground bounce. This causes a problem that a stable test cannot be performed.

Further, a test for evaluating the input characteristics and output characteristics of a semiconductor integrated circuit requires more time than a function test and a test for detecting a failure. If the test time is long, there is a problem that it is reflected in the manufacturing cost of the semiconductor integrated circuit.

The present invention has been made to solve this problem, and has the following objects. An object of the present invention is to generate a test pattern in which the number of simultaneous changes in output signals of a semiconductor integrated circuit is suppressed. In particular, in order to achieve the above object, a semiconductor integrated circuit is provided with a test facilitation circuit capable of changing the execution order of test patterns. In addition, when the test pattern is deleted to suppress the number of simultaneous changes in output, the final failure detection rate is calculated efficiently, and when the failure detection rate does not reach the target value, the test for undetected failures is performed. It is intended to generate patterns. Another object is to create a combination of test patterns having a small number of cycles, that is, a small number of test patterns.

[0007]

According to the present invention, there is provided an apparatus for generating a test pattern for a semiconductor integrated circuit, comprising: a test pattern for performing a test on a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of the test pattern; In the test pattern generation device for a semiconductor integrated circuit to be generated,
It is characterized by comprising the following elements. (A) a first test pattern generation unit that generates at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as test patterns for testing the semiconductor integrated circuit, and (b) a failure simulation. Executing the test pattern generated by the first test pattern generation unit, and detecting whether the detected fault can be detected by executing the test pattern generated by the first test pattern generation unit. A failure detection unit that stores the detected failure and the result of the determination as failure information; and (c) performs an output expectation value generated by the first test pattern generation unit in accordance with the test order. Compare the expected output value of the test pattern with the expected output value of the next test pattern, and count the number of changes in the expected output value. (D) determining a fault that can be detected only in a test pattern in which the number of changes in the expected output value counted by the change number counting section exceeds a predetermined allowable number of output changes; A failure information updating unit that updates the failure information stored in the failure detecting unit so that the failed failure becomes an undetectable failure; (e)
A failure detection rate is obtained from the failure information updated by the failure information updating unit, and a test pattern is determined for a failure that cannot be detected in the failure information so that the failure detection rate satisfies the specified failure detection rate. A second test pattern generation unit to be generated, (f) a change in the expected output value of the test pattern generated by the second test pattern generation unit and an expected output value of the test pattern generated by the first test pattern generation unit Compare the expected output value of the test pattern to be executed first and the expected output value of the test pattern to be executed next for the expected output value of the test pattern including the test pattern whose number satisfies the predetermined allowable output change number. And the number of changes in the expected output value is counted, so that the counted number of changes in the expected output value does not exceed a predetermined allowable output change number. The third test pattern generating unit for changing the execution order of test patterns to suit above.

A test pattern generating apparatus for a semiconductor integrated circuit according to the present invention generates a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of test patterns. The circuit test pattern generation device is characterized by including the following elements. (A) generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit;
A combination pattern generation unit configured to generate a combination pattern including one or more test patterns by combining the generated test patterns; (b) a combination pattern generated by the combination pattern generation unit;
A combination pattern acquisition unit for acquiring a combination pattern composed of a test pattern whose output expected value is either logic 0 or logic 1; and (c) a test pattern for the combination pattern acquired by the combination pattern acquisition unit. (D) a change number counting unit that compares the expected output value of the test pattern performed first and the expected output value of the test pattern performed next according to the test order and counts the number of changes in the output expected value; A combination pattern determining unit for acquiring a combination pattern composed of test patterns in which the number of changes in the expected output value counted by the above does not exceed a predetermined allowable number of output changes.

[0009] The combination pattern determination section may include:
A combination pattern having a small number of test patterns constituting the combination pattern is preferentially acquired.

Further, the test pattern generating apparatus for a semiconductor integrated circuit further includes a step of determining whether the input data of the test pattern constituting the combination pattern is logic 0 or logic 1 based on the combination pattern acquired by the combination pattern acquisition section. A combination pattern narrowing-down unit that obtains a combination pattern composed of test patterns that are the same as described above. The number-of-changes counting unit searches for the combination pattern obtained by the combination pattern narrowing-down unit in accordance with the test order of the test pattern. The expected output value of the test pattern to be executed next is compared with the expected output value of the test pattern to be executed next, and the number of changes in the expected output value is counted.

Further, the semiconductor integrated circuit includes at least one of a scan circuit and a boundary scan circuit as a test facilitating circuit in which the execution order of the test pattern can be changed.

[0012] A test pattern generating apparatus for a semiconductor integrated circuit according to the present invention includes the following elements. (A) a test pattern generator for generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as test patterns for testing the semiconductor integrated circuit; (b) the test pattern generator A group specifying unit that specifies a group of test patterns for applying a test pattern to the semiconductor integrated circuit under the same control from the generated test pattern; and (c) a test for the test pattern specified by the group specifying unit. A change count unit for comparing the expected output value of the test pattern to be performed first and the expected output value of the test pattern to be performed next in accordance with the test order of the pattern, and counting the number of changes in the expected output value; The number of changes in the expected output value counted by the So as not to exceed the number, do one of the deletion of at least testing order changes and test patterns, execution order determination unit which determines the execution order of the test pattern.

Further, the test pattern generation unit includes a combination pattern generation unit that generates a combination pattern composed of one or more test patterns by combining the generated test patterns. A combination pattern acquisition unit configured to acquire, from the test pattern designated by the group designation unit, a combination pattern constituted by a test pattern whose output expected value is one of logic 0 and logic 1, The change count part is
For the combination pattern acquired by the combination pattern acquisition unit, the expected output value of the test pattern to be performed first is compared with the expected output value of the next test pattern according to the test order of the test pattern, and the number of changes in the expected output value is determined. It is characterized by counting.

Further, the method for generating a test pattern for a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of the test pattern. A method of generating a test pattern for a circuit includes the following steps. (A) a first test pattern generation step of generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as test patterns for testing the semiconductor integrated circuit, and (b) a failure simulation. Executing the test pattern generated in the first test pattern generating step, and detecting whether the detected fault is detectable by executing the test pattern generated in the first test pattern generating step. hand,
A failure detection step of storing the detected failure and the result of the determination as failure information; and (c) a test to be performed first on the output expected value generated in the first test pattern generation step in the test order. A change number counting step of comparing the expected output value of the pattern with the expected output value of the test pattern to be performed next, and counting the number of changes in the expected output value; A fault that can be detected only in a test pattern in which the number of changes exceeds a predetermined allowable output change number is determined, and the fault information stored in the fault detection step is such that the determined fault becomes an undetectable fault. (E) a failure detection rate is determined from the failure information updated in the failure information updating step, and a failure detection rate defined by the failure detection rate is determined. So as to satisfy the rate, the second test pattern generating step of generating a test pattern for fault undetectable is failure among the failure information, (f)
A test pattern in which the number of changes in the expected output value satisfies a predetermined allowable output change number among the test patterns generated in the second test pattern generation step and the test patterns generated in the first test pattern generation step. With respect to the expected output value of the test pattern, the output expected value of the test pattern to be executed first is compared with the expected output value of the test pattern to be executed next, and the number of changes in the expected output value is counted. A third test pattern generating step of changing the execution order of the combined test patterns so that the number of changes in the expected output value does not exceed a predetermined allowable number of changes in output.

Further, the method for generating a test pattern for a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of test patterns. A method of generating a test pattern for a circuit includes the following steps. (A) generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit;
A combination pattern generating step of generating a combination pattern composed of one or more test patterns by combining the generated test patterns; (b) the output expected value is set to logic 0 and logic 0 from the combination pattern generated by the combination pattern generation step; A combination pattern acquisition step of acquiring a combination pattern constituted by any one of the test patterns, and (c) a combination of the test patterns to be performed first in the test pattern test order for the combination patterns acquired in the combination pattern acquisition step. A change number counting step of comparing the output expected value with the output expected value of the test pattern to be performed next and counting the number of changes in the output expected value; (d) the number of changes in the output expected value counted in the above change number counting step But,
A combination pattern determination step of acquiring a combination pattern composed of test patterns that do not exceed a predetermined allowable number of output changes.

Further, the test pattern generation method for a semiconductor integrated circuit further includes a step of determining whether the input data of the test pattern constituting the combination pattern is logic 0 or logic 1 based on the combination pattern acquired in the combination pattern acquisition step. A combination pattern narrowing-down step of acquiring a combination pattern constituted by test patterns that are:
For the combination pattern obtained in the above combination pattern narrowing step, the output expected value of the test pattern to be performed first is compared with the output expected value of the next test pattern according to the test order of the test pattern, and the number of changes in the output expected value is calculated. Counting step.

Further, a method for generating a test pattern for a semiconductor integrated circuit according to the present invention includes the following steps. (A) a test pattern generating step of generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit, and (b) the test pattern generating step. A group designation step of designating a group of test patterns to which a test pattern is applied to the semiconductor integrated circuit from the generated test pattern by the same control; (c) a test order of the test patterns designated by the group designation step Comparing the expected output value of the first test pattern with the expected output value of the next test pattern, and counting the number of changes in the expected output value. Output change exceeds the specified allowable output change. Oddly, it does one of the deletion of at least testing order changes and test patterns, execution order determination step of determining the execution order of test patterns.

Further, the test pattern generating step includes:
The method for generating a test pattern for a semiconductor integrated circuit further includes a combination pattern generation step of generating a combination pattern composed of one or more test patterns by combining the generated test patterns. A combination pattern acquisition step of acquiring, from the pattern, a combination pattern formed by a test pattern in which the output expected value is one of logic 0 and logic 1, and the number-of-changes counting step is performed by the combination pattern acquisition step. For the obtained combination pattern, the output expected value of the test pattern to be performed first and the output expected value of the next test pattern to be performed are compared in accordance with the test order of the test pattern, and the number of changes in the output expected value is counted. I do.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A test pattern generation device for a semiconductor integrated circuit and a test pattern generation method for a semiconductor integrated circuit according to the present invention will be described below.
A test pattern generation apparatus and a test pattern generation method for a semiconductor integrated circuit according to the present invention provide a test for failure detection and a characteristic test using at least one of a scan circuit and a boundary scan circuit as a test facilitation circuit for a semiconductor integrated circuit. An apparatus and method for generating a pattern. First, a test pattern that can detect a single stuck-at fault existing only on a signal path of a semiconductor integrated circuit is defined as an ATPG (ATPG is an Automatic T
abbreviation of est Pattern Generation,
A program for automatically generating a test pattern for detecting a failure of a semiconductor integrated circuit). For the ATPG algorithm, for example,
Watanabe Makoto: Compilation "Super LSI Design" Planning Center Co., Ltd .:
Published (1983) 198-207.

The test pattern generated here includes a phase in which a test pattern is applied from an input signal of the semiconductor integrated circuit, a phase in which the test pattern is serially scanned by a scan circuit or a boundary scan circuit, and a test result based on an output signal of the semiconductor integrated circuit. Is a test pattern that is divided into phases for observing the above, and these three phases are repeated. One trial is completed in one phase,
In the next phase, the results of the previous run have no effect. Therefore, even if you change the order in which test patterns are executed,
The test and the characteristic test for fault detection have no problem.

Next, a change in the generated test pattern output signal (hereinafter, in the first to sixth embodiments, the expected value of the output signal is simply referred to as an output signal) is used to change the test pattern in the next test. By comparing with the output, the number of changes in the output signal is counted, and the allowable number of simultaneous output changes determined from the characteristics of the semiconductor integrated circuit, the characteristics of the package that seals the semiconductor integrated circuit, and the test environment of the semiconductor integrated circuit. Is searched for all test patterns. By changing the order of the test patterns so that the number of simultaneous changes of the output signal satisfies the allowable value, or deleting the test signals in the portion of the test pattern that exceeds the allowable value, Generate a test pattern with a reduced number of changes.

FIG. 1 is a flow chart for explaining the above-described method for generating a test pattern for a semiconductor integrated circuit. FIG. 2 and FIG. 3 are diagrams showing specific examples of the test patterns generated by the procedure shown in FIG.

First, an initial pattern is generated by an ATPG algorithm for a scan circuit or a boundary scan circuit which is a test facilitation circuit of a semiconductor integrated circuit (SPG).
100).

The test pattern generated by the ATPG algorithm includes a phase for applying values from all input signals of the semiconductor integrated circuit, a phase for serially shifting the test pattern to a scan circuit or a boundary scan circuit, Is a test pattern that is divided into phases for observing the expected value with the output signal of the above, and these three phases are repeated. There is a characteristic that the test can be performed without any problem even if the order of the repetitive patterns is changed. The present invention takes advantage of this feature in testing scan circuits and boundary scan circuits.

Next, focusing on the change in the expected value of the output signal of the semiconductor integrated circuit in the initial pattern, the number of output signals that change for each test pattern is counted (S10).
1) Yes.

Finally, all the parts exceeding the allowable number of simultaneous output changes determined from the characteristics of the semiconductor integrated circuit, the characteristics of the package for sealing the semiconductor integrated circuit, the test environment of the semiconductor integrated circuit, etc. Search for a pattern. When a large number of outputs of the semiconductor integrated circuit change at the same time, ground bounce may occur. For this reason,
Noise is added to the measurement signal and the input signal of the semiconductor integrated circuit itself, and a stable test cannot be performed. The "acceptable" value of the number of simultaneous changes in the output includes the output buffer capacity, the test environment of the semiconductor integrated circuit, the output pin and the DUT (Device U).
A person estimates the value from experience based on the inductance component attached to the card. As a result of the search, for the test patterns exceeding the allowable value, the order of the test patterns is changed so that the number of simultaneous changes of the output satisfies the allowable value, or the test pattern is deleted (S102). A test pattern in which the number of simultaneous changes is suppressed is formed.

FIG. 2 shows the expected value of the output signal of the initial test pattern generated by using the ATPG algorithm and the number of simultaneous changes (SSO). When the number of changes in the output signal is counted, the pattern identification ID No. No. 1 from the test pattern No. 1 The number of simultaneous changes in output between the two test patterns is nine. No. 2 to No. 2 The number of simultaneous output changes during 3 is 15. No. 3 to N
o. The number of simultaneous changes in the output during 4 is 8. Assuming that the allowable value of the output of the semiconductor integrated circuit is 11 from the characteristics of the semiconductor integrated circuit, the characteristics of the package for sealing the semiconductor integrated circuit, the test environment of the semiconductor integrated circuit, etc., N
o. 2 to No. 2 The number of simultaneous changes 15 in the output between 3 exceeds the allowable value. When a test of the semiconductor integrated circuit is performed using this test pattern, the number of the output exceeding the allowable value of the number of simultaneous changes in output is no. 2 to No. 2 There is a possibility that a ground bounce occurs between the three and a stable test cannot be performed.

Therefore, the order of the test patterns was changed based on the flowchart shown in FIG. FIG. 3 shows an example. The test pattern order is No. 1-> No. 3
-> No. 4 → No. By changing to 2, the maximum number of simultaneous changes is No. 1 to No. It becomes 10 between 3 and becomes the allowable value 11 or less. By applying the algorithm of FIG. 1, the number of simultaneous changes in output can be reduced, and a stable test can be performed.

Embodiment 2 In the second embodiment, when a test pattern is deleted to suppress the number of simultaneous changes in output in the first embodiment, a semiconductor integrated circuit that generates a test pattern so that the failure detection rate satisfies a specified failure detection rate The test pattern generation device and test pattern generation method will be described below.

First, using the deleted test pattern,
A failure simulation is performed to find a detectable failure. The fault detection rate is obtained from the detectable faults obtained above and the faults detectable in the initial test pattern. The obtained failure detection rate is not an accurate failure detection rate, but is the worst value when the test pattern is deleted. If the failure detection rate does not reach the target failure detection rate, test patterns are generated for failures that can be detected with the deleted test pattern and failures that cannot be detected with the initial test pattern, and a new test pattern is generated. obtain. This new test pattern is inserted into the test pattern exceeding the allowable value deleted in the first embodiment from the initial test pattern so that the number of simultaneous changes in the output falls within the allowable value.
As a result, the number of simultaneous changes in the output signal can be suppressed, and a test pattern with a target failure detection rate can be generated.

FIG. 4 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the second embodiment. FIG.
9 is a flowchart for explaining a test pattern generation method for a semiconductor integrated circuit according to the second embodiment. FIG.
FIG. 4 is a diagram for explaining a relationship between a total failure and an undetected failure.

The following is a description of the drawings. In FIG. 4, reference numeral 1 denotes a first test pattern generation unit, which generates an initial test pattern for a scan circuit or a boundary scan circuit, which is a test facilitation circuit of a semiconductor integrated circuit, using an ATPG algorithm. . S2 in FIG.
The initial pattern generation process of 00 is executed by the first test pattern generation unit 1. 2 is a failure detection unit,
A fault simulation is performed to detect a fault that may occur in the semiconductor integrated circuit. Then, it is determined whether or not the detected failure can be detected based on the initial test pattern. The result of the determined failure is stored in the failure information storage unit 3 as failure information. The process of generating the failure dictionary in S200 of FIG.
Reference numeral 4 denotes a change number counting unit, which counts how many output signals change in each test pattern in an initial test pattern by focusing on a change in an expected value of an output signal of the semiconductor integrated circuit. I do. The process of counting the number of simultaneous changes in the output in S201 of FIG. Reference numeral 5 denotes a failure information updating unit that detects a failure that can be detected only by a test pattern in which the number of simultaneous changes in output counted by the number-of-changes counting unit 4 exceeds an allowable number of output changes. Then, the failure information stored in the failure information storage unit 3 is updated based on the detected result. The process of updating the failure information in S203 of FIG. 5 is executed by the failure information updating unit 5. Reference numeral 6 denotes a second test pattern generation unit that calculates a failure detection rate based on the failure information stored in the failure information storage unit. Then, a test pattern is generated for a fault for which a fault cannot be detected so that the calculated fault detection rate satisfies the specified fault detection rate. The test pattern generation processing of S204 in FIG. 5 is executed by the second test pattern generation unit 6. Reference numeral 7 denotes a third test pattern generation unit, which determines the execution order based on the test patterns generated by the second test pattern generation unit 6 and the test patterns generated by the first test pattern generation unit 1. . At this time,
A test pattern in which the number of simultaneous output changes counted by the change number counting section 4 exceeds an allowable number of output changes is excluded from the test patterns generated by the first test pattern generation section 1. Further, the execution order of the test patterns is determined so that the number of simultaneous output changes does not exceed a predetermined allowable number of output changes. The process of inserting a test pattern at a position that satisfies the output simultaneous change number in S205 in FIG.
This is executed by the third test pattern generator 7.

A method of generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. S20 in FIG.
0 is a first test pattern generation step and a failure detection step. The processing from S200 to S202 is almost the same as the processing from S100 to S102 in FIG. 1 of the first embodiment. In S200, an initial test pattern is generated, and a fault simulation is performed by the fault detection unit 2 to generate fault information. The total failure 20 in FIG.
This is a fault that can occur in the semiconductor integrated circuit, and the fault 22 detected in FIG. 6 is a fault that can be detected by the first test pattern generator 1. In S200, the total fault 20, the detected fault, and the undetected fault 21 are obtained as fault information. S2
In step 02, test patterns that do not satisfy the number of simultaneous changes in output are deleted. After the test pattern is deleted, in the fault information updating step, a fault simulation is performed by the fault information updating unit 5 to obtain a fault (23 in FIG. 6) detectable by the deleted test pattern. And S200
6 and the fault 23 detected by the deleted pattern in FIG.
Then, the fault information stored in the fault information storage unit 3 is updated (S203). The difference determined in S203 is
A predetermined test pattern is deleted from the initial pattern (S20
2) Not all of the faults detected in the test pattern after the test. That is, some of the faults (23 in FIG. 5) that can be detected by the deleted test pattern may be detected by a test pattern other than the deleted test pattern, and are stored in the fault information storage unit 3. The updated failure information is a failure that can be detected at least by the remaining test patterns obtained by deleting test patterns that do not satisfy the number of simultaneous changes in output from the test patterns generated by the first test pattern generation unit 1.

Next, the second test pattern generation section 6 executes a second test pattern generation step (S204). In the second test pattern generation step, first, a failure detection rate is calculated based on the failure information stored in the failure information storage unit 3. The fault detection rate is calculated from the ratio of the total fault 20 in FIG. 6 to the detected fault excluding the fault 23 detected by the test pattern deleted from the detected fault 22. And
When the calculated failure detection rate does not satisfy the prescribed failure detection rate, the failure information stored in the failure information storage unit 3 includes:
A test pattern is generated for a fault for which fault detection is not possible. Failures that cannot be detected include failures 21 detected in FIG. 6 and failures 2 detected in the deleted test pattern.
3 and 3.

Finally, the test pattern in which the number of simultaneous changes in output exceeds the allowable number of changes in output in S202 is deleted, and the test pattern generated in S204, which is the second test pattern generation step, is deleted. To determine the execution order of the test patterns. At this time, a test pattern is inserted at a position where the number of simultaneous changes in output satisfies the allowable value (S205).

By applying this algorithm to test pattern generation, it is possible to generate a test pattern capable of suppressing the number of simultaneous changes and performing a stable test with a high fault detection rate.

Embodiment 3 In the third embodiment, a test pattern generation device and a test pattern generation method for a semiconductor integrated circuit on which a scan circuit or a boundary scan circuit for generating a test pattern for evaluating the output buffer characteristics of the semiconductor integrated circuit will be described.

In the test pattern generation method for detecting a failure or testing a characteristic of a semiconductor integrated circuit using a scan circuit and a boundary scan circuit as a test facilitating circuit of the semiconductor integrated circuit described in the third embodiment, first, Generate a test pattern for Next, an output value of the generated test pattern is searched, and a test pattern in which all output signals of the semiconductor integrated circuit become logic 0 and logic 1 is extracted. At this time, a test pattern that minimizes the number of test patterns is extracted. As a result, a test pattern for evaluating the output buffer characteristics of the semiconductor integrated circuit can be generated.

FIG. 7 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit according to the third embodiment. FIG.
11 is a flowchart of a test pattern generation method for a semiconductor integrated circuit according to the third embodiment. 9 and 10
FIG. 9 is a diagram showing a specific example of a test pattern generated by the procedure shown in FIG. Hereinafter, a test pattern generation device and a test pattern generation method for a semiconductor integrated circuit according to the third embodiment will be described with reference to FIGS.

In FIG. 7, reference numeral 10 denotes a combination pattern generation unit, which generates a combination pattern by combining a plurality of test patterns created in the process of FIG. 1S100 of the first embodiment. The initial pattern generation processing of S300 in FIG. 8 is executed by the combination pattern generation unit 10. Reference numeral 11 denotes a combination pattern acquisition unit, which acquires a combination pattern composed of a test pattern whose output expected value is one of logic 0 and logic 1 from the combination pattern generated by the combination pattern generation unit 10. The test pattern shown in FIG. 9 has an expected output value of either logic 0 or logic 1, but the expected output value may include “X” indicating an indefinite value in addition to logic 0 and logic 1. is there. S301 in FIG.
Is performed by the combination pattern acquisition unit 11. Reference numeral 12 denotes a change number counting unit which counts the expected output value of the test pattern constituting the combination pattern acquired by the combination pattern acquisition unit 11 in the same manner as the change number counting unit 4 of FIG. I do. The process of counting the number of simultaneous changes in the output in S302 of FIG. 13
Is a combination pattern determination unit that acquires a combination pattern composed of a test pattern in which the number of changes in the expected output value counted by the change number counting unit 12 satisfies a predetermined allowable number of output changes. At this time,
By changing the execution order of the test patterns, the change number of the expected output value may satisfy a predetermined allowable change number of the output. Further, a test pattern in which the number of changes in the expected output value does not satisfy the predetermined allowable number of changes in output may be deleted from the combination pattern.
In the third embodiment, the combination pattern determination unit 1
No. 3 acquires a combination pattern by giving priority to a combination pattern in which the number of test patterns constituting the combination pattern is small. The change processing of the order in S303 and the end determination of the processing in S304 in FIG. 8 are executed by the combination pattern determination unit 13.

A method for generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. S3 in FIG.
The process of 00 is a combination pattern generation step. S
The process of 300 is substantially the same as the process of S100 of FIG. 1 of the first embodiment. In S300, a combination pattern is generated by combining a plurality of the generated test patterns. Next, in the combination pattern acquisition step of S301, a combination of test patterns in which all output signals are logic 0 and logic 1 is acquired from the combination pattern created in S300. Then, among the combination patterns acquired in S301, the combination pattern having the smaller number of test patterns constituting the combination pattern is preferentially used in S3 described later.
02 to S304 are performed. S302 to S30
The processing of No. 4 is performed for all the combination patterns acquired in S301 (S305). First, the number of simultaneous changes in the output signal of the test pattern is counted in the number-of-changes counting step of S302, and the number of simultaneous changes in the output counted in S302 satisfies a predetermined allowable value in the combination pattern determining step of S303. , The execution order of the test patterns is changed, or the test patterns are deleted. If all the test patterns constituting the combination pattern have the number of simultaneous output changes satisfying the predetermined allowable value, the execution order is not changed or the test pattern is not deleted. If the number of simultaneous changes does not satisfy the allowable value in the process of S303 (S304), the process of searching for a combination pattern that satisfies the allowable value is repeated from the process of S302.

The algorithm of FIG. 8 will be described with reference to FIGS. 9 and 10. FIG. 9 shows an initial test pattern obtained by ATPG in S300. It is assumed that the number of simultaneous changes in the output is 15, which exceeds the allowable value 11 of the number of simultaneous changes in the output. In the test pattern shown in FIG. 9, all output signals are changed to logic 0 and logic 1. Then, it is assumed that the number of test patterns constituting the combination pattern is the minimum. Therefore, if the processing from S302 to S304 in FIG. 8 is applied to this pattern, the test pattern shown in FIG. 10 can be finally obtained. FIG.
Is 3 and the number of simultaneous changes in the output is 9 at the maximum, which satisfies the allowable value 11 or less.

By using the algorithm shown in FIG. 8, a test pattern for a characteristic test of an output buffer of a semiconductor integrated circuit in which the number of simultaneous changes in output is suppressed by a test pattern having a short cycle number, ie, a small test pattern number, can be generated. . As a result, a more stable test can be performed in a shorter time than a test using an initial test pattern.

Embodiment 4 FIG. Fourth Embodiment In a fourth embodiment, a test pattern generation device and a test pattern generation method for a semiconductor integrated circuit to which a boundary scan circuit is applied will be described.

First, an initial test pattern is generated.
Next, the input value of the generated test pattern is searched to extract a test pattern in which all input signals of the semiconductor integrated circuit become logic 0 and logic 1. At this time, a test pattern that minimizes the number of test patterns is extracted. The boundary scan circuit latches the value set in the input signal by the boundary scan register, and the value is scanned and output by the serial output of the boundary scan circuit. Therefore, the input of the semiconductor integrated circuit is performed using the test pattern extracted by the above-described method. The threshold voltage of the buffer can be measured.

As described above, when the boundary scan circuit is used, the data set in the input signal is latched in the boundary scan register, and the data appears on the serial output of the boundary scan circuit. It is possible to measure properties.

FIG. 11 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the fourth embodiment. FIG.
FIG. 2 is a flowchart for explaining a test pattern generation method for a semiconductor integrated circuit according to the fourth embodiment. FIG.
FIGS. 3 and 14 are diagrams showing specific examples of test patterns generated by the procedure shown in FIG. The figures will be described below.

In FIG. 11, the combination pattern generation unit 10 and the combination pattern acquisition unit 11 perform the same operations as the combination pattern generation unit 10 and the combination pattern acquisition unit 11 of the third embodiment shown in FIG. Numeral 14 denotes a combination pattern narrowing-down unit, in which the input data of the test pattern constituting the combination pattern acquired by the combination pattern acquisition unit 11 is composed of a test pattern which is either logical 0 or logical 1. Get a pattern. The search processing of S402 in FIG. 12 is executed by the combination pattern narrowing unit 14. The change number counting unit 12 operates in the same manner as the change number counting unit 12 of the third embodiment, but counts the number of simultaneous output changes of the test patterns constituting the combination pattern acquired by the combination pattern narrowing unit 14. . The combination pattern determination unit 13 performs the same operation as the combination pattern determination unit 13 of the third embodiment.

A method for generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. The processes in S400, S401, and S406 in FIG. 12 are the same as the processes in S300, S301, and S305 in FIG. The processing of S402 and S407 is a combination pattern narrowing-down step. For the combination pattern acquired in the processing of S402, the input data of the test pattern forming the combination pattern is a logical 0
And a combination pattern composed of a test pattern that is one of logic 1 and logic 1. The process of S402 is performed on all the combination patterns acquired in S401 (S407). The process in S403 is performed in S4
02 is performed on the combination pattern acquired in step S02. S
The processing of 404 and the processing of S405 are the same as the processing of S303 and S304 in FIG. 8 of the third embodiment. As described above, for the test pattern after searching for the combination in which all the output signals have the logic 0 and the logic 1, all the input data (the input data may be referred to as the input signal) is further processed in S402. Search for a combination that results in a logical 0 and a logical 1. By adding the processing of S402 to FIG. 8 of the third embodiment, a test pattern for input buffer characteristic test of a semiconductor integrated circuit with a small number of test patterns and a reduced number of simultaneous changes in output signals can be created. Can be.

FIG. 13 shows an initial test pattern generated by using the ATPG in S400 of FIG. 12. The number of simultaneous changes in the output exceeds 15 and the allowable value 11 of the number of simultaneous changes in the output. Therefore, it cannot be used as it is as a test pattern for the characteristic test of the input buffer. FIG. 14 shows the result of applying the processing shown in FIG. 12 to the test pattern shown in FIG. In FIG. 14, the number of simultaneous changes in the output is 9 at the maximum, which satisfies the allowable value 11. Furthermore, the number of test patterns is 3,
The number of test patterns is small. As described above, the test pattern for the input buffer characteristic test of the semiconductor integrated circuit is formed by the test pattern generation apparatus for the semiconductor integrated circuit having the configuration shown in FIG. 11 and the test pattern generation method for the semiconductor integrated circuit having the procedure shown in FIG. As a result, the number of test patterns is smaller than that of a test using an initial test pattern, and a more stable test can be performed.

Embodiment 5 FIG. In the fifth embodiment, by performing the same control during the test pattern, a portion that does not affect the operation of the semiconductor integrated circuit even if the test execution order is changed is specified. For example, data transfer on the data bus between the arithmetic circuit and the memory corresponds to this. A test pattern generation apparatus for a semiconductor integrated circuit, which generates a test pattern such that the number of simultaneous changes of an output signal falls within a predetermined allowable number of simultaneous changes by changing the execution order for the test pattern of the specified portion. And a test pattern generation method for a semiconductor integrated circuit will be described.

FIG. 15 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the fifth embodiment. FIG. 16 is a flowchart illustrating a test pattern generation method for a semiconductor integrated circuit according to the fifth embodiment. Hereinafter, the drawings will be described.

In FIG. 15, reference numeral 30 denotes a test pattern generator, which performs the same operation as the first test pattern generator 1 of FIG. 4 of the second embodiment. S503 in FIG.
The test pattern generation process of the test pattern generation unit 3
Performed by 0. 31 is a group designation part,
From the test patterns generated by the test pattern generation unit 30, a group of test patterns for applying the test patterns to the semiconductor integrated circuit under the same control is specified. The process of designating the portion to which the repetitive test pattern is applied in S500 of FIG. Numeral 32 denotes a change number counting unit, which counts the number of simultaneous output changes for the group specified by the group specifying unit 31, similarly to the change number counting unit 4 in FIG. 4 of the second embodiment. The counting process of S501 in FIG. 16 is executed by the change number counting unit 32.
Reference numeral 33 denotes an execution order determination unit, and the number-of-changes counting unit 32
The test pattern execution order is changed so that the number of simultaneous output changes counted by the above satisfies the predetermined allowable output change number, or the test pattern exceeding the predetermined allowable output change number is deleted, and the test is performed. Determine the execution order of the patterns. The process of S502 in FIG. 16 is executed by the execution order determining unit 33.

Next, a method of generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. First, in the test pattern generation step, a test pattern is generated using the ATPG as in S100 of FIG. 1 of the first embodiment (S503). Next, in the group designation step, a portion to which the test pattern is repeatedly applied to the semiconductor integrated circuit under the same control is designated from among the test patterns generated in S503 (S500).
I do. The portion to which a test pattern is repeatedly applied corresponds to, for example, a process of repeatedly reading and writing data in a continuous memory area. Then, in the change number counting step, the number of simultaneous changes of the output signal is counted for the test pattern of the portion designated in S500 (S501). Finally, in the execution order determination step, the order of the test patterns in which the number of simultaneous changes in output counted in S501 exceeds the allowable value is changed or deleted to generate a test pattern in which the number of simultaneous changes in output is suppressed (S502). . Thus, by using the algorithm of FIG. 16, a more stable test can be performed than a test using an initial test pattern.

Embodiment 6 FIG. In the sixth embodiment, by performing the same control during the test pattern, a portion that does not affect the operation of the semiconductor integrated circuit even if the execution order of the test pattern is changed is specified. For example, data transfer on the data bus between the arithmetic circuit and the memory corresponds to this. Further, a test pattern in which all output signals of the semiconductor integrated circuit change to logic 0 and logic 1 is extracted. At that time, the number of test patterns is minimized. This allows
A test pattern generation device for a semiconductor integrated circuit and a test pattern generation method for a semiconductor integrated circuit that can generate a test pattern for an output buffer characteristic test will be described.

FIG. 17 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the sixth embodiment. FIG. 18 is a flowchart illustrating a test pattern generation method for a semiconductor integrated circuit according to the sixth embodiment. Hereinafter, the drawings will be described.

In FIG. 17, the test pattern generator 3
0 and the group designation unit 31 are the same as those in FIG.
Perform the same operation as the test pattern generation unit 30 and the group designation unit 31. However, the test pattern generation unit 30 includes a combination pattern generation unit 30a, and the combination pattern generation unit 30a
Generates a combined test pattern by combining a plurality of test patterns generated by the. The test pattern generation processing of S605 in FIG. 18 is executed by the test pattern generation unit 30 and the combination pattern generation unit 30a. The process of designating the part to which the repetitive test pattern is applied in S600 of FIG. 18 is executed by the group designation unit 31. Reference numeral 34 denotes a combination pattern acquisition unit that performs the same operation as that of the combination pattern acquisition unit 11 in FIG. 7 of the third embodiment. The search processing of S601 in FIG. 18 is executed by the combination pattern acquisition unit 34. 35 is
A change count unit, and a combination pattern acquisition unit 3
The number of simultaneous changes in the output of the test pattern constituting the combination pattern obtained in step 4 is counted by the same operation as the change number counting unit 12 in FIG. 7 of the third embodiment. The counting process of S602 in FIG. 18 is executed by the change number counting unit 35. An execution order determination unit 33 changes the execution order of the test patterns so that the number of simultaneous output changes counted by the change number counting unit 35 does not exceed a predetermined allowable output change number. The processes of S603 and S604 in FIG. 18 are executed by the execution order determining unit 33.

A test pattern generation method for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. First, S
A test pattern is generated in a test pattern generation step 605, and a combination test pattern is generated by combining a plurality of the generated test patterns in a combination pattern generation step. Next, in the group designation step of S600, a portion to which the test pattern is repeatedly applied is designated by the same control in the test pattern. Such a portion corresponds to, for example, a process of repeatedly reading or writing data in a continuous memory area. Then, in the combination pattern acquisition step of S601, a combination of test patterns in which all output signals are logic 0 and logic 1 is searched for the portion to be repeatedly applied specified in S600. From the test patterns of the retrieved combinations, those having a smaller number of test patterns are preferentially executed from S602 to S
Step 604 is performed. In the number-of-changes counting step of S602, the number of simultaneous changes in the output signal of the test pattern is counted, and in the execution order determination step of S603, the order of the test patterns equal to or more than the allowable number of simultaneous changes in output is changed.
If the number of simultaneous changes in output does not satisfy the allowable value due to this change (S604), the process of counting the number of simultaneous changes in output is performed with another combination of test patterns, and the above-described steps from S602 are performed so as to search for a test pattern satisfying the allowable value. The processing of S604 is repeatedly performed.

By the algorithm shown in FIG. 18, a test pattern having a short cycle number, that is, a test pattern having a small number of test patterns and a test pattern for testing the characteristics of an output buffer of a semiconductor integrated circuit in which the number of simultaneous changes in output is suppressed is generated. Thus, a more stable test can be performed in a shorter time than a test using an initial test pattern.

[0060]

As described above, the semiconductor integrated circuit test pattern generating apparatus and the semiconductor integrated circuit test pattern generating method of the present invention generate a test pattern in which the number of simultaneous changes in the output signal of the semiconductor integrated circuit is suppressed. This makes it possible to generate a test pattern in which a malfunction of the semiconductor integrated circuit due to an electrical factor of ground bounce does not occur at the time of testing the semiconductor integrated circuit. In addition, when testing a semiconductor integrated circuit, it is not necessary to add a special test circuit to the semiconductor integrated circuit in addition to a scan circuit and a boundary scan circuit which are conventional test facilitating circuits. There is an effect that does not occur. Further, in generating a test pattern for detecting a failure in a semiconductor integrated circuit, the number of simultaneous changes in output signals can be suppressed, and a test pattern that satisfies a prescribed failure detection rate can be generated.

Further, the number of simultaneous changes of the output signal of the semiconductor integrated circuit can be suppressed, and the minimum period for the characteristic test of the output buffer, that is, a test pattern with a small number of test patterns can be generated.

Further, there is an effect that a test pattern for measuring the threshold voltage of the input buffer can be generated.

Further, for example, when a test of a process of repeatedly reading or writing data in a continuous memory area is performed on a semiconductor integrated circuit, a portion for repeatedly applying a test pattern to the semiconductor integrated circuit under the same control is used. Since the designation can be made, the test pattern can be easily generated, and a test for a specific operation of the semiconductor integrated circuit can be surely performed.

Further, for example, when a test of a process of repeatedly reading and writing data in a continuous memory area is performed on a semiconductor integrated circuit, a portion for repeatedly applying a test pattern to the semiconductor integrated circuit under the same control is used. It is possible to generate a test pattern for the characteristic test of the output buffer of the semiconductor integrated circuit in which the number of simultaneous changes can be suppressed by the test pattern having a small number of test patterns. Therefore, there is an effect that a characteristic test of the output buffer of the semiconductor integrated circuit can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an example of test pattern generation in which the number of simultaneous changes in the output of a semiconductor integrated circuit on which a scan circuit or a boundary scan circuit according to a first embodiment is mounted is suppressed;

FIG. 2 is a view for explaining one example of test pattern generation in which the number of simultaneous changes in the output of a semiconductor integrated circuit mounted with a scan circuit or a boundary scan circuit according to the first embodiment is suppressed.

FIG. 3 is a diagram for explaining an example of test pattern generation in which the number of simultaneous changes in the output of the semiconductor integrated circuit on which the scan circuit or the boundary scan circuit according to the first embodiment is mounted is suppressed;

FIG. 4 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit on which a scan circuit or a boundary scan circuit according to a second embodiment is mounted.

FIG. 5 is a view for explaining one example of test pattern generation in which the number of simultaneous changes of a semiconductor integrated circuit mounted with a scan circuit or a boundary scan circuit according to the second embodiment is suppressed and a failure detection rate is taken into account; The flowchart figure.

FIG. 6 is a view for explaining one example of test pattern generation in which the number of simultaneous changes of a semiconductor integrated circuit mounted with a scan circuit or a boundary scan circuit according to the second embodiment is suppressed and a failure detection rate is taken into account; The figure which shows the classification of a failure.

FIG. 7 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit on which a scan circuit and a boundary scan circuit according to a third embodiment are mounted.

FIG. 8 is a view for explaining an example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the scan circuit and the boundary scan circuit according to the third embodiment are mounted is suppressed; FIG.

FIG. 9 is a view for explaining an example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the scan circuit and the boundary scan circuit according to the third embodiment are mounted is suppressed; .

FIG. 10 is a diagram illustrating one example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of a semiconductor integrated circuit on which a scan circuit and a boundary scan circuit according to a third embodiment are mounted is suppressed; .

FIG. 11 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit on which a scan circuit and a boundary scan circuit according to a fourth embodiment are mounted.

FIG. 12 is a flowchart for explaining an example of test pattern generation for an input buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the boundary scan circuit according to the fourth embodiment is mounted is suppressed; .

FIG. 13 is a view for explaining an example of test pattern generation for an input buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the boundary scan circuit according to the fourth embodiment is mounted is suppressed;

FIG. 14 is a view for explaining an example of generation of a test pattern for an input buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the boundary scan circuit according to the fourth embodiment is mounted is suppressed;

FIG. 15 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit according to a fifth embodiment in which the number of simultaneous changes in the semiconductor integrated circuit is suppressed.

FIG. 16 is a flowchart for explaining one example of test pattern generation of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit according to the fifth embodiment is suppressed.

FIG. 17 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit according to the sixth embodiment is suppressed.

FIG. 18 is a flowchart for explaining an example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit according to the sixth embodiment is suppressed.

FIG. 19 is a flowchart for explaining a conventional technique for generating a test pattern in consideration of the number of simultaneous changes of a semiconductor integrated circuit.

[Explanation of symbols]

1 first test pattern generation unit, 2 failure detection unit, 3
Failure information storage section, 4 change count section, 5 failure information update section, 6 second test pattern generation section, 7 third test pattern generation section, 10 combination pattern generation section, 11 combination pattern acquisition section, 12 number of changes Counting section, 13 combination pattern determination section, 14 combination pattern narrowing section, 20 total failures, 21 undetected failures, 22 detected failures, 23 failures detected in deleted patterns, 30 test pattern generation section, 30a combination pattern generation section , 31 Group designation section, 32
Change number counting section, 33 execution order determination section, 34 combination pattern acquisition section, 35 change number counting section.

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[Procedure amendment]

[Submission date] March 12, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Full text

[Correction method] Change

[Correction contents]

[Document Name] Statement

Patent application title: Semiconductor integrated circuit test pattern generation apparatus and semiconductor integrated circuit test pattern generation method

[Claims]

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an apparatus for generating a test pattern for testing a semiconductor integrated circuit and a method for generating a test pattern for a semiconductor integrated circuit. In particular, the present invention relates to an apparatus and a method for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit in which the execution order of test patterns can be changed.

[0002]

2. Description of the Related Art As a conventional technique, Japanese Patent Laid-Open Publication No.
7 discloses an input data generation method. JP-A-2-90077 is an invention for generating input data while suppressing the number of simultaneous changes of output signals of a semiconductor integrated circuit. FIG.
Fig. 1 shows an input data generation procedure in the related art. First,
As the first step (100), it is assumed that all possible faults occur in an LSI (semiconductor integrated circuit). As a second step (101), one fault is selected from all the faults assumed in the first step (100). As a third step (102), input data is generated for the fault selected in the second step. The fourth step (10
As 4), the input data generated in the third step (102) is stored in the memory. The first to fourth steps are repeated to create input data for all the faults assumed in the first step, and then, as a fifth step (105), for all the generated input data, prohibition on the number of simultaneous changes in output Tick condition. Sixth
Step (106) and seventh step (107)
When the prohibition condition is satisfied, the fourth step (104)
To rearrange the input data stored in the memory. If all the prohibition conditions are satisfied for the rearranged input data, the process ends.

[0003]

As described above, in the prior art, input data is rearranged to generate input data in which the number of simultaneous changes in output is suppressed. However, in the input buffer characteristic test and the output buffer characteristic test, it is necessary that input signals and output signals of all the semiconductor integrated circuits toggle between logic 0 and logic 1. Since only the description of the input data generation that suppresses the above is described, there is a problem that the characteristic test of the input buffer and the output buffer cannot be performed.

In a test of a semiconductor integrated circuit, if a large number of output signals of the semiconductor integrated circuit simultaneously change, the semiconductor integrated circuit may malfunction due to an electrical factor of ground bounce. This causes a problem that a stable test cannot be performed.

Further, a test for evaluating the input characteristics and output characteristics of a semiconductor integrated circuit requires more time than a function test and a test for detecting a failure. If the test time is long, there is a problem that it is reflected in the manufacturing cost of the semiconductor integrated circuit.

The present invention has been made to solve this problem, and has the following objects. An object of the present invention is to generate a test pattern in which the number of simultaneous changes in output signals of a semiconductor integrated circuit is suppressed. In particular, in order to achieve the above object, a semiconductor integrated circuit is provided with a test facilitation circuit capable of changing the execution order of test patterns. In addition, when the test pattern is deleted to suppress the number of simultaneous changes in output, the final failure detection rate is calculated efficiently, and when the failure detection rate does not reach the target value, the test for undetected failures is performed. It is intended to generate patterns. Another object is to create a combination of test patterns having a small number of cycles, that is, a small number of test patterns.

[0007]

According to the present invention, there is provided an apparatus for generating a test pattern for a semiconductor integrated circuit, comprising: a test pattern for performing a test on a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of the test pattern; In the test pattern generation device for a semiconductor integrated circuit to be generated,
It is characterized by comprising the following elements. (A) a first test pattern generation unit that generates at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as test patterns for testing the semiconductor integrated circuit, and (b) a failure simulation. Executing the test pattern generated by the first test pattern generation unit, and detecting whether the detected fault can be detected by executing the test pattern generated by the first test pattern generation unit. A failure detection unit that stores the detected failure and the result of the determination as failure information; and (c) performs an output expectation value generated by the first test pattern generation unit in accordance with the test order. Compare the expected output value of the test pattern with the expected output value of the next test pattern, and count the number of changes in the expected output value. (D) determining a fault that can be detected only in a test pattern in which the number of changes in the expected output value counted by the change number counting section exceeds a predetermined allowable number of output changes; A failure information updating unit that updates the failure information stored in the failure detecting unit so that the failed failure becomes an undetectable failure; (e)
A failure detection rate is obtained from the failure information updated by the failure information updating unit, and a test pattern is determined for a failure that cannot be detected in the failure information so that the failure detection rate satisfies the specified failure detection rate. A second test pattern generation unit to be generated, (f) a change in the expected output value of the test pattern generated by the second test pattern generation unit and an expected output value of the test pattern generated by the first test pattern generation unit Compare the expected output value of the test pattern to be executed first and the expected output value of the test pattern to be executed next for the expected output value of the test pattern including the test pattern whose number satisfies the predetermined allowable output change number. And the number of changes in the expected output value is counted, so that the counted number of changes in the expected output value does not exceed a predetermined allowable output change number. The third test pattern generating unit for changing the execution order of test patterns to suit above.

Further, the semiconductor integrated circuit is characterized in that at least one of a scan circuit and a boundary scan circuit is provided as a test facilitation circuit in which the execution order of the test pattern can be changed.

A test pattern generation method for a semiconductor integrated circuit according to the present invention is a semiconductor integrated circuit for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of test patterns. A method of generating a test pattern for a circuit includes the following steps. (A) a first test pattern generation step of generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as test patterns for testing the semiconductor integrated circuit, and (b) a failure simulation. Executing the test pattern generated in the first test pattern generating step, and detecting whether the detected fault is detectable by executing the test pattern generated in the first test pattern generating step. hand,
A failure detection step of storing the detected failure and the result of the determination as failure information; and (c) a test to be performed first on the output expected value generated in the first test pattern generation step in the test order. A change number counting step of comparing the expected output value of the pattern with the expected output value of the test pattern to be performed next, and counting the number of changes in the expected output value; A fault that can be detected only in a test pattern in which the number of changes exceeds a predetermined allowable output change number is determined, and the fault information stored in the fault detection step is such that the determined fault becomes an undetectable fault. (E) a failure detection rate is determined from the failure information updated in the failure information updating step, and a failure detection rate defined by the failure detection rate is determined. So as to satisfy the rate, the second test pattern generating step of generating a test pattern for fault undetectable is failure among the failure information, (f)
A test pattern in which the number of changes in the expected output value satisfies a predetermined allowable output change number among the test patterns generated in the second test pattern generation step and the test patterns generated in the first test pattern generation step. With respect to the expected output value of the test pattern, the output expected value of the test pattern to be executed first is compared with the expected output value of the test pattern to be executed next, and the number of changes in the expected output value is counted. A third test pattern generating step of changing the execution order of the combined test patterns so that the number of changes in the expected output value does not exceed a predetermined allowable number of changes in output.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A test pattern generation device for a semiconductor integrated circuit and a test pattern generation method for a semiconductor integrated circuit according to the present invention will be described below.
A test pattern generation apparatus and a test pattern generation method for a semiconductor integrated circuit according to the present invention provide a test for failure detection and a characteristic test using at least one of a scan circuit and a boundary scan circuit as a test facilitation circuit for a semiconductor integrated circuit. An apparatus and method for generating a pattern. First, a test pattern that can detect a single stuck-at fault existing only on a signal path of a semiconductor integrated circuit is defined as an ATPG (ATPG is an Automatic T
abbreviation of est Pattern Generation,
A program for automatically generating a test pattern for detecting a failure of a semiconductor integrated circuit). For the ATPG algorithm, for example,
Watanabe Makoto: Compilation "Super LSI Design" Planning Center Co., Ltd .:
Published (1983) 198-207.

The test pattern generated here includes a phase in which a test pattern is applied from an input signal of the semiconductor integrated circuit, a phase in which the test pattern is serially scanned by a scan circuit or a boundary scan circuit, and a test result based on an output signal of the semiconductor integrated circuit. Is a test pattern that is divided into phases for observing the above, and these three phases are repeated. One trial is completed in one phase,
In the next phase, the results of the previous run have no effect. Therefore, even if you change the order in which test patterns are executed,
The test and the characteristic test for fault detection have no problem.

Next, a change in the generated test pattern output signal (hereinafter, in the first to sixth embodiments, the expected value of the output signal is simply referred to as the output signal) is used to change the test pattern in the next test. By comparing with the output, the number of changes in the output signal is counted, and the allowable number of simultaneous output changes determined from the characteristics of the semiconductor integrated circuit, the characteristics of the package that seals the semiconductor integrated circuit, and the test environment of the semiconductor integrated circuit. Is searched for all test patterns. By changing the order of the test patterns so that the number of simultaneous changes of the output signal satisfies the allowable value, or deleting the test signals in the portion of the test pattern that exceeds the allowable value, Generate a test pattern with a reduced number of changes.

FIG. 1 is a flow chart for explaining the above-described method for generating a test pattern for a semiconductor integrated circuit. FIG. 2 and FIG. 3 are diagrams showing specific examples of the test patterns generated by the procedure shown in FIG.

First, an initial pattern is generated by an ATPG algorithm for a scan circuit or a boundary scan circuit which is a test facilitation circuit of a semiconductor integrated circuit (SPG).
100).

The test pattern generated by the ATPG algorithm includes a phase for applying values from all input signals of the semiconductor integrated circuit, a phase for serially shifting the test pattern to a scan circuit or a boundary scan circuit, Is a test pattern that is divided into phases for observing the expected value with the output signal of the above, and these three phases are repeated. There is a characteristic that the test can be performed without any problem even if the order of the repetitive patterns is changed. The present invention takes advantage of this feature in testing scan circuits and boundary scan circuits.

Next, focusing on the change in the expected value of the output signal of the semiconductor integrated circuit in the initial pattern, the number of output signals that change for each test pattern is counted (S10).
1) Yes.

Finally, all the parts exceeding the allowable number of simultaneous output changes determined from the characteristics of the semiconductor integrated circuit, the characteristics of the package for sealing the semiconductor integrated circuit, the test environment of the semiconductor integrated circuit, etc. Search for a pattern. When a large number of outputs of the semiconductor integrated circuit change at the same time, ground bounce may occur. For this reason,
Noise is added to the measurement signal and the input signal of the semiconductor integrated circuit itself, and a stable test cannot be performed. The "acceptable" value of the number of simultaneous changes in the output includes the output buffer capacity, the test environment of the semiconductor integrated circuit, the output pin and the DUT (Device U).
A person estimates the value from experience based on the inductance component attached to the card. As a result of the search, for the test patterns exceeding the allowable value, the order of the test patterns is changed so that the number of simultaneous changes of the output satisfies the allowable value, or the test pattern is deleted (S102). A test pattern in which the number of simultaneous changes is suppressed is formed.

FIG. 2 shows the expected value and the number of simultaneous changes (SSO) of the output signal of the initial test pattern generated using the ATPG algorithm. When the number of changes in the output signal is counted, the pattern identification ID No. No. 1 from the test pattern No. 1 The number of simultaneous changes in output between the two test patterns is nine. No. 2 to No. 2 The number of simultaneous output changes during 3 is 15. No. 3 to N
o. The number of simultaneous changes in the output during 4 is 8. Assuming that the allowable value of the output of the semiconductor integrated circuit is 11 from the characteristics of the semiconductor integrated circuit, the characteristics of the package for sealing the semiconductor integrated circuit, the test environment of the semiconductor integrated circuit, etc., N
o. 2 to No. 2 The number of simultaneous changes 15 in the output between 3 exceeds the allowable value. When a test of the semiconductor integrated circuit is performed using this test pattern, the number of the output exceeding the allowable value of the number of simultaneous changes in output is no. 2 to No. 2 There is a possibility that a ground bounce occurs between the three and a stable test cannot be performed.

Therefore, the order of the test patterns was changed based on the flowchart shown in FIG. FIG. 3 shows an example. The test pattern order is No. 1-> No. 3
-> No. 4 → No. By changing to 2, the maximum number of simultaneous changes is No. 1 to No. It becomes 10 between 3 and becomes the allowable value 11 or less. By applying the algorithm of FIG. 1, the number of simultaneous changes in output can be reduced, and a stable test can be performed.

Embodiment 2 In the second embodiment, when a test pattern is deleted to suppress the number of simultaneous changes in output in the first embodiment, a semiconductor integrated circuit that generates a test pattern so that the failure detection rate satisfies a specified failure detection rate The test pattern generation device and test pattern generation method will be described below.

First, using the deleted test pattern,
A failure simulation is performed to find a detectable failure. The fault detection rate is obtained from the detectable faults obtained above and the faults detectable in the initial test pattern. The obtained failure detection rate is not an accurate failure detection rate, but is the worst value when the test pattern is deleted. If the failure detection rate does not reach the target failure detection rate, test patterns are generated for failures that can be detected with the deleted test pattern and failures that cannot be detected with the initial test pattern, and a new test pattern is generated. obtain. This new test pattern is inserted into the test pattern exceeding the allowable value deleted in the first embodiment from the initial test pattern so that the number of simultaneous changes in the output falls within the allowable value.
As a result, the number of simultaneous changes in the output signal can be suppressed, and a test pattern with a target failure detection rate can be generated.

FIG. 4 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the second embodiment. FIG.
9 is a flowchart for explaining a test pattern generation method for a semiconductor integrated circuit according to the second embodiment. FIG.
FIG. 4 is a diagram for explaining a relationship between a total failure and an undetected failure.

The following is a description of the drawings. In FIG. 4, reference numeral 1 denotes a first test pattern generation unit, which generates an initial test pattern for a scan circuit or a boundary scan circuit, which is a test facilitation circuit of a semiconductor integrated circuit, using an ATPG algorithm. . S2 in FIG.
The initial pattern generation process of 00 is executed by the first test pattern generation unit 1. 2 is a failure detection unit,
A fault simulation is performed to detect a fault that may occur in the semiconductor integrated circuit. Then, it is determined whether or not the detected failure can be detected based on the initial test pattern. The result of the determined failure is stored in the failure information storage unit 3 as failure information. The process of generating the failure dictionary in S200 of FIG.
Reference numeral 4 denotes a change number counting unit, which counts how many output signals change in each test pattern in an initial test pattern by focusing on a change in an expected value of an output signal of the semiconductor integrated circuit. I do. The process of counting the number of simultaneous changes in the output in S201 of FIG. Reference numeral 5 denotes a failure information updating unit that detects a failure that can be detected only by a test pattern in which the number of simultaneous changes in output counted by the number-of-changes counting unit 4 exceeds an allowable number of output changes. Then, the failure information stored in the failure information storage unit 3 is updated based on the detected result. The process of updating the failure information in S203 of FIG. 5 is executed by the failure information updating unit 5. Reference numeral 6 denotes a second test pattern generation unit that calculates a failure detection rate based on the failure information stored in the failure information storage unit. Then, a test pattern is generated for a fault for which a fault cannot be detected so that the calculated fault detection rate satisfies the specified fault detection rate. The test pattern generation processing of S204 in FIG. 5 is executed by the second test pattern generation unit 6. Reference numeral 7 denotes a third test pattern generation unit, which determines the execution order based on the test patterns generated by the second test pattern generation unit 6 and the test patterns generated by the first test pattern generation unit 1. . At this time,
A test pattern in which the number of simultaneous output changes counted by the change number counting section 4 exceeds an allowable number of output changes is excluded from the test patterns generated by the first test pattern generation section 1. Further, the execution order of the test patterns is determined so that the number of simultaneous output changes does not exceed a predetermined allowable number of output changes. The process of inserting a test pattern at a position that satisfies the output simultaneous change number in S205 in FIG.
This is executed by the third test pattern generator 7.

A method of generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. S20 in FIG.
0 is a first test pattern generation step and a failure detection step. The processing from S200 to S202 is almost the same as the processing from S100 to S102 in FIG. 1 of the first embodiment. In S200, an initial test pattern is generated, and a fault simulation is performed by the fault detection unit 2 to generate fault information. The total failure 20 in FIG.
This is a fault that can occur in the semiconductor integrated circuit, and the fault 22 detected in FIG. 6 is a fault that can be detected by the first test pattern generator 1. In S200, the total fault 20, the detected fault, and the undetected fault 21 are obtained as fault information. S2
In step 02, test patterns that do not satisfy the number of simultaneous changes in output are deleted. After the test pattern is deleted, in the fault information updating step, a fault simulation is performed by the fault information updating unit 5 to obtain a fault (23 in FIG. 6) detectable by the deleted test pattern. And S200
6 and the fault 23 detected by the deleted pattern in FIG.
Then, the fault information stored in the fault information storage unit 3 is updated (S203). The difference determined in S203 is
A predetermined test pattern is deleted from the initial pattern (S20
2) Not all of the faults detected in the test pattern after the test. That is, some of the faults (23 in FIG. 5) that can be detected by the deleted test pattern may be detected by a test pattern other than the deleted test pattern, and are stored in the fault information storage unit 3. The updated failure information is a failure that can be detected at least by the remaining test patterns obtained by deleting test patterns that do not satisfy the number of simultaneous changes in output from the test patterns generated by the first test pattern generation unit 1.

Next, a second test pattern generation step (S204) is executed by the second test pattern generation section 6. In the second test pattern generation step, first, a failure detection rate is calculated based on the failure information stored in the failure information storage unit 3. The fault detection rate is calculated from the ratio of the total fault 20 in FIG. 6 to the detected fault excluding the fault 23 detected by the test pattern deleted from the detected fault 22. And
When the calculated failure detection rate does not satisfy the prescribed failure detection rate, the failure information stored in the failure information storage unit 3 includes:
A test pattern is generated for a fault for which fault detection is not possible. Failures that cannot be detected include failures 21 detected in FIG. 6 and failures 2 detected in the deleted test pattern.
3 and 3.

Finally, the test pattern generated in S204, which is the second test pattern generation step, is compared with the test pattern in which the number of simultaneous changes in output exceeds the allowable number of output changes in S202. To determine the execution order of the test patterns. At this time, a test pattern is inserted at a position where the number of simultaneous changes in output satisfies the allowable value (S205).

By applying this algorithm to test pattern generation, it is possible to generate a test pattern capable of suppressing the number of simultaneous changes and performing a stable test with a high fault detection rate.

Embodiment 3 In the third embodiment, a test pattern generation device and a test pattern generation method for a semiconductor integrated circuit on which a scan circuit or a boundary scan circuit for generating a test pattern for evaluating the output buffer characteristics of the semiconductor integrated circuit will be described.

In a test pattern generation method for detecting a failure or testing a characteristic of a semiconductor integrated circuit using a scan circuit and a boundary scan circuit as a circuit for facilitating the test of the semiconductor integrated circuit described in the third embodiment, first, Generate a test pattern for Next, an output value of the generated test pattern is searched, and a test pattern in which all output signals of the semiconductor integrated circuit become logic 0 and logic 1 is extracted. At this time, a test pattern that minimizes the number of test patterns is extracted. As a result, a test pattern for evaluating the output buffer characteristics of the semiconductor integrated circuit can be generated.

FIG. 7 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit according to the third embodiment. FIG.
11 is a flowchart of a test pattern generation method for a semiconductor integrated circuit according to the third embodiment. 9 and 10
FIG. 9 is a diagram showing a specific example of a test pattern generated by the procedure shown in FIG. Hereinafter, a test pattern generation device and a test pattern generation method for a semiconductor integrated circuit according to the third embodiment will be described with reference to FIGS.

In FIG. 7, reference numeral 10 denotes a combination pattern generation unit, which generates a combination pattern by combining a plurality of test patterns created in the processing of FIG. 1S100 of the first embodiment. The initial pattern generation processing of S300 in FIG. 8 is executed by the combination pattern generation unit 10. Reference numeral 11 denotes a combination pattern acquisition unit, which acquires a combination pattern composed of a test pattern whose output expected value is one of logic 0 and logic 1 from the combination pattern generated by the combination pattern generation unit 10. The test pattern shown in FIG. 9 has an expected output value of either logic 0 or logic 1, but the expected output value may include “X” indicating an indefinite value in addition to logic 0 and logic 1. is there. S301 in FIG.
Is performed by the combination pattern acquisition unit 11. Reference numeral 12 denotes a change number counting unit which counts the expected output value of the test pattern constituting the combination pattern acquired by the combination pattern acquisition unit 11 in the same manner as the change number counting unit 4 of FIG. I do. The process of counting the number of simultaneous changes in the output in S302 of FIG. 13
Is a combination pattern determination unit that acquires a combination pattern composed of a test pattern in which the number of changes in the expected output value counted by the change number counting unit 12 satisfies a predetermined allowable number of output changes. At this time,
By changing the execution order of the test patterns, the change number of the expected output value may satisfy a predetermined allowable change number of the output. Further, a test pattern in which the number of changes in the expected output value does not satisfy the predetermined allowable number of changes in output may be deleted from the combination pattern.
In the third embodiment, the combination pattern determination unit 1
No. 3 acquires a combination pattern by giving priority to a combination pattern in which the number of test patterns constituting the combination pattern is small. The change processing of the order in S303 and the end determination of the processing in S304 in FIG. 8 are executed by the combination pattern determination unit 13.

A method of generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. S3 in FIG.
The process of 00 is a combination pattern generation step. S
The process of 300 is substantially the same as the process of S100 of FIG. 1 of the first embodiment. In S300, a combination pattern is generated by combining a plurality of the generated test patterns. Next, in the combination pattern acquisition step of S301, a combination of test patterns in which all output signals are logic 0 and logic 1 is acquired from the combination pattern created in S300. Then, among the combination patterns acquired in S301, the combination pattern having the smaller number of test patterns constituting the combination pattern is preferentially used in S3 described later.
02 to S304 are performed. S302 to S30
The processing of No. 4 is performed for all the combination patterns acquired in S301 (S305). First, the number of simultaneous changes in the output signal of the test pattern is counted in the number-of-changes counting step of S302, and the number of simultaneous changes in the output counted in S302 satisfies a predetermined allowable value in the combination pattern determining step of S303. , The execution order of the test patterns is changed, or the test patterns are deleted. If all the test patterns constituting the combination pattern have the number of simultaneous output changes satisfying the predetermined allowable value, the execution order is not changed or the test pattern is not deleted. If the number of simultaneous changes does not satisfy the allowable value in the process of S303 (S304), the process of searching for a combination pattern that satisfies the allowable value is repeated from the process of S302.

The algorithm of FIG. 8 will be described with reference to FIGS. 9 and 10. FIG. 9 shows an initial test pattern obtained by ATPG in S300. It is assumed that the number of simultaneous changes in the output is 15, which exceeds the allowable value 11 of the number of simultaneous changes in the output. In the test pattern shown in FIG. 9, all output signals are changed to logic 0 and logic 1. Then, it is assumed that the number of test patterns constituting the combination pattern is the minimum. Therefore, if the processing from S302 to S304 in FIG. 8 is applied to this pattern, the test pattern shown in FIG. 10 can be finally obtained. FIG.
Is 3 and the number of simultaneous changes in the output is 9 at the maximum, which satisfies the allowable value 11 or less.

By the algorithm of FIG. 8, a test pattern for a characteristic test of an output buffer of a semiconductor integrated circuit in which the number of simultaneous changes in output is suppressed by a test pattern having a short cycle number, that is, a small test pattern number can be generated. . As a result, a more stable test can be performed in a shorter time than a test using an initial test pattern.

Embodiment 4 FIG. Fourth Embodiment In a fourth embodiment, a test pattern generation device and a test pattern generation method for a semiconductor integrated circuit to which a boundary scan circuit is applied will be described.

First, an initial test pattern is generated.
Next, the input value of the generated test pattern is searched to extract a test pattern in which all input signals of the semiconductor integrated circuit become logic 0 and logic 1. At this time, a test pattern that minimizes the number of test patterns is extracted. The boundary scan circuit latches the value set in the input signal by the boundary scan register, and the value is scanned and output by the serial output of the boundary scan circuit. Therefore, the input of the semiconductor integrated circuit is performed using the test pattern extracted by the above-described method. The threshold voltage of the buffer can be measured.

As described above, when the boundary scan circuit is used, the data set in the input signal is latched in the boundary scan register, and the data appears in the serial output of the boundary scan circuit. It is possible to measure properties.

FIG. 11 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the fourth embodiment. FIG.
FIG. 2 is a flowchart for explaining a test pattern generation method for a semiconductor integrated circuit according to the fourth embodiment. FIG.
FIGS. 3 and 14 are diagrams showing specific examples of test patterns generated by the procedure shown in FIG. The figures will be described below.

In FIG. 11, the combination pattern generation unit 10 and the combination pattern acquisition unit 11 perform the same operations as the combination pattern generation unit 10 and the combination pattern acquisition unit 11 of the third embodiment shown in FIG. Numeral 14 denotes a combination pattern narrowing-down unit, in which the input data of the test pattern constituting the combination pattern acquired by the combination pattern acquisition unit 11 is composed of a test pattern which is either logical 0 or logical 1. Get a pattern. The search processing of S402 in FIG. 12 is executed by the combination pattern narrowing unit 14. The change number counting unit 12 operates in the same manner as the change number counting unit 12 of the third embodiment, but counts the number of simultaneous output changes of the test patterns constituting the combination pattern acquired by the combination pattern narrowing unit 14. . The combination pattern determination unit 13 performs the same operation as the combination pattern determination unit 13 of the third embodiment.

A method of generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. The processes in S400, S401, and S406 in FIG. 12 are the same as the processes in S300, S301, and S305 in FIG. The processing of S402 and S407 is a combination pattern narrowing-down step. For the combination pattern acquired in the processing of S402, the input data of the test pattern forming the combination pattern is a logical 0
And a combination pattern composed of a test pattern that is one of logic 1 and logic 1. The process of S402 is performed on all the combination patterns acquired in S401 (S407). The process in S403 is performed in S4
02 is performed on the combination pattern acquired in step S02. S
The processing of 404 and the processing of S405 are the same as the processing of S303 and S304 in FIG. 8 of the third embodiment. As described above, for the test pattern after searching for the combination in which all the output signals have the logic 0 and the logic 1, all the input data (the input data may be referred to as the input signal) is further processed in S402. Search for a combination that results in a logical 0 and a logical 1. By adding the processing of S402 to FIG. 8 of the third embodiment, a test pattern for input buffer characteristic test of a semiconductor integrated circuit with a small number of test patterns and a reduced number of simultaneous changes in output signals can be created. Can be.

FIG. 13 shows an initial test pattern generated by using the ATPG in S400 of FIG. 12. The number of simultaneous changes in the output exceeds 15 and the allowable value 11 of the number of simultaneous changes in the output. Therefore, it cannot be used as it is as a test pattern for the characteristic test of the input buffer. FIG. 14 shows the result of applying the processing shown in FIG. 12 to the test pattern shown in FIG. In FIG. 14, the number of simultaneous changes in the output is 9 at the maximum, which satisfies the allowable value 11. Furthermore, the number of test patterns is 3,
The number of test patterns is small. As described above, the test pattern for the input buffer characteristic test of the semiconductor integrated circuit is formed by the test pattern generation apparatus for the semiconductor integrated circuit having the configuration shown in FIG. 11 and the test pattern generation method for the semiconductor integrated circuit having the procedure shown in FIG. As a result, the number of test patterns is smaller than that of a test using an initial test pattern, and a more stable test can be performed.

Embodiment 5 FIG. In the fifth embodiment, by performing the same control during the test pattern, a portion that does not affect the operation of the semiconductor integrated circuit even if the test execution order is changed is specified. For example, data transfer on the data bus between the arithmetic circuit and the memory corresponds to this. A test pattern generation apparatus for a semiconductor integrated circuit, which generates a test pattern such that the number of simultaneous changes of an output signal falls within a predetermined allowable number of simultaneous changes by changing the execution order for the test pattern of the specified portion. And a test pattern generation method for a semiconductor integrated circuit will be described.

FIG. 15 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the fifth embodiment. FIG. 16 is a flowchart illustrating a test pattern generation method for a semiconductor integrated circuit according to the fifth embodiment. Hereinafter, the drawings will be described.

In FIG. 15, reference numeral 30 denotes a test pattern generator, which performs the same operation as that of the first test pattern generator 1 of the second embodiment shown in FIG. S503 in FIG.
The test pattern generation process of the test pattern generation unit 3
Performed by 0. 31 is a group designation part,
From the test patterns generated by the test pattern generation unit 30, a group of test patterns for applying the test patterns to the semiconductor integrated circuit under the same control is specified. The process of designating the portion to which the repetitive test pattern is applied in S500 of FIG. Numeral 32 denotes a change number counting unit, which counts the number of simultaneous output changes for the group specified by the group specifying unit 31, similarly to the change number counting unit 4 in FIG. 4 of the second embodiment. The counting process of S501 in FIG. 16 is executed by the change number counting unit 32.
Reference numeral 33 denotes an execution order determination unit, and the number-of-changes counting unit 32
The test pattern execution order is changed so that the number of simultaneous output changes counted by the above satisfies the predetermined allowable output change number, or the test pattern exceeding the predetermined allowable output change number is deleted, and the test is performed. Determine the execution order of the patterns. The process of S502 in FIG. 16 is executed by the execution order determining unit 33.

Next, a method of generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. First, in the test pattern generation step, a test pattern is generated using the ATPG as in S100 of FIG. 1 of the first embodiment (S503). Next, in the group designation step, a portion to which the test pattern is repeatedly applied to the semiconductor integrated circuit under the same control is designated from among the test patterns generated in S503 (S500).
I do. The portion to which a test pattern is repeatedly applied corresponds to, for example, a process of repeatedly reading and writing data in a continuous memory area. Then, in the change number counting step, the number of simultaneous changes of the output signal is counted for the test pattern of the portion designated in S500 (S501). Finally, in the execution order determination step, the order of the test patterns in which the number of simultaneous changes in output counted in S501 exceeds the allowable value is changed or deleted to generate a test pattern in which the number of simultaneous changes in output is suppressed (S502). . Thus, by using the algorithm of FIG. 16, a more stable test can be performed than a test using an initial test pattern.

As described above, according to the fifth embodiment, for example, when a test of a process of repeatedly reading and writing data in a continuous memory area is performed on a semiconductor integrated circuit, a test pattern is repeatedly performed under the same control. Since a portion to be applied to the semiconductor integrated circuit can be specified, a test pattern can be easily generated, and a test for a specific operation of the semiconductor integrated circuit can be reliably performed.

Embodiment 6 FIG. In the sixth embodiment, by performing the same control during the test pattern, a portion that does not affect the operation of the semiconductor integrated circuit even if the execution order of the test pattern is changed is specified. For example, data transfer on the data bus between the arithmetic circuit and the memory corresponds to this. Further, a test pattern in which all output signals of the semiconductor integrated circuit change to logic 0 and logic 1 is extracted. At that time, the number of test patterns is minimized. This allows
A test pattern generation device for a semiconductor integrated circuit and a test pattern generation method for a semiconductor integrated circuit that can generate a test pattern for an output buffer characteristic test will be described.

FIG. 17 is a diagram showing a configuration of a test pattern generation device for a semiconductor integrated circuit according to the sixth embodiment. FIG. 18 is a flowchart illustrating a test pattern generation method for a semiconductor integrated circuit according to the sixth embodiment. Hereinafter, the drawings will be described.

In FIG. 17, the test pattern generator 3
0 and the group designation unit 31 are the same as those in FIG.
Perform the same operation as the test pattern generation unit 30 and the group designation unit 31. However, the test pattern generation unit 30 includes a combination pattern generation unit 30a, and the combination pattern generation unit 30a
Generates a combined test pattern by combining a plurality of test patterns generated by the. The test pattern generation processing of S605 in FIG. 18 is executed by the test pattern generation unit 30 and the combination pattern generation unit 30a. The process of designating the part to which the repetitive test pattern is applied in S600 of FIG. 18 is executed by the group designation unit 31. Reference numeral 34 denotes a combination pattern acquisition unit that performs the same operation as that of the combination pattern acquisition unit 11 in FIG. 7 of the third embodiment. The search processing of S601 in FIG. 18 is executed by the combination pattern acquisition unit 34. 35 is
A change count unit, and a combination pattern acquisition unit 3
The number of simultaneous changes in the output of the test pattern constituting the combination pattern obtained in step 4 is counted by the same operation as the change number counting unit 12 in FIG. 7 of the third embodiment. The counting process of S602 in FIG. 18 is executed by the change number counting unit 35. An execution order determination unit 33 changes the execution order of the test patterns so that the number of simultaneous output changes counted by the change number counting unit 35 does not exceed a predetermined allowable output change number. The processes of S603 and S604 in FIG. 18 are executed by the execution order determining unit 33.

A method for generating a test pattern for a semiconductor integrated circuit will be described with reference to the flowchart of FIG. First, S
A test pattern is generated in a test pattern generation step 605, and a combination test pattern is generated by combining a plurality of the generated test patterns in a combination pattern generation step. Next, in the group designation step of S600, a portion to which the test pattern is repeatedly applied is designated by the same control in the test pattern. Such a portion corresponds to, for example, a process of repeatedly reading or writing data in a continuous memory area. Then, in the combination pattern acquisition step of S601, a combination of test patterns in which all output signals are logic 0 and logic 1 is searched for the portion to be repeatedly applied specified in S600. From the test patterns of the retrieved combinations, those having a smaller number of test patterns are preferentially executed from S602 to S
Step 604 is performed. In the number-of-changes counting step of S602, the number of simultaneous changes in the output signal of the test pattern is counted, and in the execution order determination step of S603, the order of the test patterns equal to or more than the allowable number of simultaneous changes in output is changed.
If the number of simultaneous changes in output does not satisfy the allowable value due to this change (S604), the process of counting the number of simultaneous changes in output is performed with another combination of test patterns, and the above-described steps from S602 are performed so as to search for a test pattern satisfying the allowable value. The processing of S604 is repeatedly performed.

Using the algorithm shown in FIG. 18, a test pattern having a short cycle number, that is, a test pattern having a small number of test patterns, is used to test the characteristics of the output buffer of the semiconductor integrated circuit in which the number of simultaneous changes in output is suppressed. Thus, a more stable test can be performed in a shorter time than a test using an initial test pattern.

As described above, according to the sixth embodiment, for example, when a test of a process of repeatedly reading and writing data in a continuous memory area is performed on a semiconductor integrated circuit, a test pattern is repeatedly performed under the same control. A portion to be applied to the semiconductor integrated circuit can be specified, and a test pattern for a characteristic test of an output buffer of the semiconductor integrated circuit can be generated in which the number of simultaneous output changes is suppressed by a test pattern having a small number of test patterns. Therefore, a characteristic test of the output buffer of the semiconductor integrated circuit can be performed in a short time.

[0053]

As described above, the semiconductor integrated circuit test pattern generating apparatus and the semiconductor integrated circuit test pattern generating method of the present invention generate a test pattern in which the number of simultaneous changes in the output signal of the semiconductor integrated circuit is suppressed. This makes it possible to generate a test pattern in which a malfunction of the semiconductor integrated circuit due to an electrical factor of ground bounce does not occur at the time of testing the semiconductor integrated circuit. In addition, when testing a semiconductor integrated circuit, it is not necessary to add a special test circuit to the semiconductor integrated circuit in addition to a scan circuit and a boundary scan circuit which are conventional test facilitating circuits. There is an effect that does not occur. Further, in generating a test pattern for detecting a failure in a semiconductor integrated circuit, the number of simultaneous changes in output signals can be suppressed, and a test pattern that satisfies a prescribed failure detection rate can be generated.

[Brief description of the drawings]

FIG. 1 is a flowchart illustrating an example of test pattern generation in which the number of simultaneous changes in the output of a semiconductor integrated circuit on which a scan circuit or a boundary scan circuit according to a first embodiment is mounted is suppressed;

FIG. 2 is a view for explaining one example of test pattern generation in which the number of simultaneous changes in the output of a semiconductor integrated circuit mounted with a scan circuit or a boundary scan circuit according to the first embodiment is suppressed.

FIG. 3 is a diagram for explaining an example of test pattern generation in which the number of simultaneous changes in the output of the semiconductor integrated circuit on which the scan circuit or the boundary scan circuit according to the first embodiment is mounted is suppressed;

FIG. 4 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit on which a scan circuit or a boundary scan circuit according to a second embodiment is mounted.

FIG. 5 is a view for explaining one example of test pattern generation in which the number of simultaneous changes of a semiconductor integrated circuit mounted with a scan circuit or a boundary scan circuit according to the second embodiment is suppressed and a failure detection rate is taken into account; The flowchart figure.

FIG. 6 is a view for explaining one example of test pattern generation in which the number of simultaneous changes of a semiconductor integrated circuit mounted with a scan circuit or a boundary scan circuit according to the second embodiment is suppressed and a failure detection rate is taken into account; The figure which shows the classification of a failure.

FIG. 7 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit on which a scan circuit and a boundary scan circuit according to a third embodiment are mounted.

FIG. 8 is a view for explaining an example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the scan circuit and the boundary scan circuit according to the third embodiment are mounted is suppressed; FIG.

FIG. 9 is a view for explaining an example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the scan circuit and the boundary scan circuit according to the third embodiment are mounted is suppressed; .

FIG. 10 is a diagram illustrating one example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of a semiconductor integrated circuit on which a scan circuit and a boundary scan circuit according to a third embodiment are mounted is suppressed; .

FIG. 11 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit on which a scan circuit and a boundary scan circuit according to a fourth embodiment are mounted.

FIG. 12 is a flowchart for explaining an example of test pattern generation for an input buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the boundary scan circuit according to the fourth embodiment is mounted is suppressed; .

FIG. 13 is a view for explaining an example of test pattern generation for an input buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the boundary scan circuit according to the fourth embodiment is mounted is suppressed;

FIG. 14 is a view for explaining an example of generation of a test pattern for an input buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit on which the boundary scan circuit according to the fourth embodiment is mounted is suppressed;

FIG. 15 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit according to a fifth embodiment in which the number of simultaneous changes in the semiconductor integrated circuit is suppressed.

FIG. 16 is a flowchart for explaining one example of test pattern generation of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit according to the fifth embodiment is suppressed.

FIG. 17 is a configuration diagram of a test pattern generation device for a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit according to the sixth embodiment is suppressed.

FIG. 18 is a flowchart for explaining an example of test pattern generation for an output buffer characteristic test of a semiconductor integrated circuit in which the number of simultaneous changes of the semiconductor integrated circuit according to the sixth embodiment is suppressed.

FIG. 19 is a flowchart for explaining a conventional technique for generating a test pattern in consideration of the number of simultaneous changes of a semiconductor integrated circuit.

[Description of Signs] 1 First test pattern generation unit, 2 Failure detection unit, 3
Failure information storage section, 4 change count section, 5 failure information update section, 6 second test pattern generation section, 7 third test pattern generation section, 10 combination pattern generation section, 11 combination pattern acquisition section, 12 number of changes Counting section, 13 combination pattern determination section, 14 combination pattern narrowing section, 20 total failures, 21 undetected failures, 22 detected failures, 23 failures detected in deleted patterns, 30 test pattern generation section, 30a combination pattern generation section , 31 Group designation section, 32
Change number counting section, 33 execution order determination section, 34 combination pattern acquisition section, 35 change number counting section.

Continued on the front page (72) Inventor Tatsuya Kimishima 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsui Electric Co., Ltd. (72) Inventor Kazuo Chiba 2-3-2 Marunouchi, Chiyoda-ku, Tokyo Mitsubishi Electric Co., Ltd. In company

Claims (12)

[Claims] An apparatus for generating a test pattern for testing a semiconductor integrated circuit having a test facilitating circuit capable of changing the execution order of the test pattern includes the following elements. (A) a first test pattern generator for generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit; (B) executing a fault simulation to detect a fault that may occur in the semiconductor integrated circuit and executing the test pattern generated by the first test pattern generating unit, Determine whether the detected fault is detectable and take the A failure detection unit that stores the determination result as failure information; and (c) an output expectation value of a test pattern to be performed first according to the test order and a next output expectation value generated by the first test pattern generation unit. A change count unit for comparing the output expected value of the test pattern to be performed and counting the change number of the output expected value; (d) the change count of the output expected value counted by the change count unit is a predetermined allowable value; A failure information updating unit that finds a failure that can be detected only in a test pattern that exceeds the number of output changes, and updates the failure information stored in the failure detection unit so that the obtained failure becomes an undetectable failure. , (E)
A failure detection rate is obtained from the failure information updated by the failure information updating unit, and a test pattern is determined for a failure that cannot be detected in the failure information so that the failure detection rate satisfies the specified failure detection rate. A second test pattern generation unit to be generated, (f) a change in the expected output value of the test pattern generated by the second test pattern generation unit and an expected output value of the test pattern generated by the first test pattern generation unit Compare the expected output value of the test pattern to be executed first and the expected output value of the test pattern to be executed next for the expected output value of the test pattern including the test pattern whose number satisfies the predetermined allowable output change number. And the number of changes in the expected output value is counted, so that the counted number of changes in the expected output value does not exceed a predetermined allowable output change number. The third test pattern generating unit for changing the execution order of test patterns to suit above. 2. A test pattern generation apparatus for a semiconductor integrated circuit, which generates a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of test patterns, includes the following elements. (A) generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit;
A combination pattern generation unit configured to generate a combination pattern including one or more test patterns by combining the generated test patterns; (b) a combination pattern generated by the combination pattern generation unit;
A combination pattern acquisition unit for acquiring a combination pattern composed of a test pattern whose output expected value is either logic 0 or logic 1; and (c) a test pattern for the combination pattern acquired by the combination pattern acquisition unit. (D) a change number counting unit that compares the expected output value of the test pattern performed first and the expected output value of the test pattern performed next according to the test order and counts the number of changes in the output expected value; A combination pattern determining unit for acquiring a combination pattern composed of test patterns in which the number of changes in the expected output value counted by the above does not exceed a predetermined allowable number of output changes. 3. The test pattern generation device for a semiconductor integrated circuit according to claim 2, wherein said combination pattern determination unit preferentially acquires a combination pattern having a small number of test patterns constituting said combination pattern. . 4. The test pattern generation device for a semiconductor integrated circuit further comprises: a combination of the combination pattern acquired by the combination pattern acquisition section, wherein input data of a test pattern constituting the combination pattern is one of logic 0 and logic 1. A combination pattern narrowing-down unit that obtains a combination pattern composed of test patterns that are the same. 4. The test pattern for a semiconductor integrated circuit according to claim 2, wherein an expected output value of the test pattern to be executed next is compared with an expected output value of the test pattern to be executed next, and the number of changes in the expected output value is counted. Generator. 5. The semiconductor integrated circuit according to claim 1, further comprising at least one of a scan circuit and a boundary scan circuit as a test facilitating circuit capable of changing an execution order of the test pattern.
A test pattern generation device for a semiconductor integrated circuit according to any one of the preceding claims. 6. A test pattern generation apparatus for a semiconductor integrated circuit, comprising the following elements: (a) a test pattern for testing the semiconductor integrated circuit, at least a test order, input data, and semiconductor integration with respect to the input data; A test pattern generation unit for generating an expected output value of the circuit; and (b) a group of test patterns for applying a test pattern to the semiconductor integrated circuit from the test pattern generated by the test pattern generation unit under the same control. (C) Compare the expected output value of the test pattern to be performed first with the expected output value of the next test pattern in accordance with the test order of the test patterns for the test pattern specified by the group specifying unit. Change number counting section for counting the number of changes in the output expected value, ( At least one of test order change and test pattern deletion is performed so that the number of changes in the expected output value counted by the number-of-changes counting unit does not exceed a predetermined allowable number of output changes. An execution order determining unit that determines an execution order. 7. The test pattern generation unit for a semiconductor integrated circuit, wherein the test pattern generation unit includes a combination pattern generation unit that generates a combination pattern including one or more test patterns by combining the generated test patterns. A combination pattern acquisition unit configured to acquire, from the test pattern designated by the group designation unit, a combination pattern constituted by a test pattern whose output expected value is one of logic 0 and logic 1, The change number counting unit compares the expected output value of the test pattern to be performed first and the expected output value of the next test pattern according to the test order of the test pattern, and outputs the combined pattern obtained by the above-described combination pattern obtaining unit. Counting the number of changes in expected value The test pattern generator of a semiconductor integrated circuit according to claim 6, wherein. 8. A test pattern generation method for a semiconductor integrated circuit for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of test patterns, the method comprising the following steps: (A) A first method for generating at least a test order, input data, and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit. (B) executing a fault simulation to detect a fault that may occur in the semiconductor integrated circuit, and executing the test pattern generated in the first test pattern generating step, Determine whether the detected failure is detectable,
A failure detection step of storing the detected failure and the result of the determination as failure information; and (c) a test to be performed first on the output expected value generated in the first test pattern generation step in the test order. A change number counting step of comparing the expected output value of the pattern with the expected output value of the test pattern to be performed next, and counting the number of changes in the expected output value; A fault that can be detected only in a test pattern in which the number of changes exceeds a predetermined allowable output change number is determined, and the fault information stored in the fault detection step is such that the determined fault becomes an undetectable fault. (E) a failure detection rate is determined from the failure information updated in the failure information updating step, and a failure detection rate defined by the failure detection rate is determined. So as to satisfy the rate, the second test pattern generating step of generating a test pattern for fault undetectable is failure among the failure information, (f)
A test pattern in which the number of changes in the expected output value satisfies a predetermined allowable output change number among the test patterns generated in the second test pattern generation step and the test patterns generated in the first test pattern generation step. With respect to the expected output value of the test pattern, the output expected value of the test pattern to be executed first is compared with the expected output value of the test pattern to be executed next, and the number of changes in the expected output value is counted. A third test pattern generating step of changing the execution order of the combined test patterns so that the number of changes in the expected output value does not exceed a predetermined allowable number of changes in output. 9. A test pattern generation method for a semiconductor integrated circuit for generating a test pattern for testing a semiconductor integrated circuit having a test facilitation circuit capable of changing the execution order of test patterns, the method comprising the following steps: (A) generating at least a test order, input data and an expected output value of the semiconductor integrated circuit with respect to the input data as a test pattern for testing the semiconductor integrated circuit,
A combination pattern generating step of generating a combination pattern composed of one or more test patterns by combining the generated test patterns; (b) the output expected value is set to logic 0 and logic 0 from the combination pattern generated by the combination pattern generation step; A combination pattern acquisition step of acquiring a combination pattern constituted by any one of the test patterns, and (c) a combination of the test patterns to be performed first in the test pattern test order for the combination patterns acquired in the combination pattern acquisition step. A change number counting step of comparing the output expected value with the output expected value of the test pattern to be performed next and counting the number of changes in the output expected value; (d) the number of changes in the output expected value counted in the above change number counting step But,
A combination pattern determination step of acquiring a combination pattern composed of test patterns that do not exceed a predetermined allowable number of output changes. 10. The method for generating a test pattern for a semiconductor integrated circuit, further comprising, based on the combination pattern acquired in the combination pattern acquisition step, input data of a test pattern constituting the combination pattern being one of logic 0 and logic 1 A combination pattern narrowing-down step of acquiring a combination pattern constituted by test patterns that are the same. 10. The test of a semiconductor integrated circuit according to claim 9, further comprising the step of comparing the expected output value of the test pattern to be performed next with the expected output value of the test pattern to be performed next and counting the number of changes in the expected output value. Pattern generation method. 11. A method for generating a test pattern for a semiconductor integrated circuit, comprising the following steps: (a) as a test pattern for testing the semiconductor integrated circuit, at least a test order, input data, and semiconductor integration with respect to the input data; A test pattern generation step of generating an expected output value of a circuit; and (b) a group of test patterns for applying a test pattern to the semiconductor integrated circuit from the test pattern generated in the test pattern generation step by the same control. (C) comparing the expected output value of the test pattern to be performed first with the expected output value of the next test pattern in accordance with the test order of the test pattern specified by the group designating step, and A change number counting step of counting the change number of the value, (d) the change At least one of the test order is changed and the test pattern is deleted so that the number of changes in the output expected value counted in the counting step does not exceed the predetermined allowable number of changes in output. An execution order determination step to be determined. 12. The test pattern generation step includes a combination pattern generation step of generating a combination pattern composed of one or more test patterns by combining the generated test patterns. A combination pattern acquisition step of acquiring, from the test pattern designated by the group designation step, a combination pattern composed of a test pattern whose output expected value is one of logic 0 and logic 1, The change number counting step is for the combination pattern acquired in the combination pattern acquisition step,
12. The semiconductor device according to claim 11, wherein an expected output value of a test pattern to be performed first is compared with an expected output value of a test pattern to be performed next according to the test order of the test patterns, and the number of changes in the expected output value is counted. A test pattern generation method for an integrated circuit.