JPH11297827A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To considerably reduce parasitic capacity generated between wirings, by forming the silica layer of silicon oxide hydroxide whose relative dielectric constant is smaller than that of a silicon oxide film on the upper part of a cavity having upper/lower ends corresponding to the thickness of the metal wiring. SOLUTION: A prescribed quantity of silica solution (silicon oxide hydroxide whose relative dielectric constant is smaller than a silicon oxide film) is previously stored in a storage liquid plate. A semiconductor substrate 101 is upset and it is supported by the base member and is lowered. Movement is stopped in a position where a part from a silicon oxide film 108 to the silicon oxide films 107 is immersed into silica solution. It is immersed into silica solution for prescribed time and the base member is pulled upward. Silica solution is held between the metal wirings by surface tension, and the upper opening part of a groove is covered by silica solution. When the semiconductor substrate 101 is baked in a state where it is vertically raised from silica solution, held silica solution is cured and a silica layer 109 is formed at the upper part of the groove between the silicon oxide films 107, and cavities 110 are formed by them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to hollowing out a region where electric lines of force are generated between wiring lines and forming a region where electric lines of electric force draws an arc into a silica layer having a small relative dielectric constant. Is formed to reduce the parasitic capacitance generated between the wirings.

[0002]

2. Description of the Related Art In recent years, with the increase in integration and miniaturization of semiconductor devices, a problem relating to a delay time determined by a product of a wiring resistance and a wiring capacitance of a metal wiring is increasing. As one of the methods for reducing the delay time, there is a method for reducing the relative dielectric constant between wirings. Examples of a semiconductor device in which the relative dielectric constant between wirings is small include, for example, Japanese Patent Application Laid-Open Nos. 9-172079 and 4-207055.
Japanese Unexamined Patent Publication (Kokai) No. H11-26095 is known.

First, a semiconductor device disclosed in Japanese Patent Application Laid-Open No. 9-172079 will be described with reference to FIG. This semiconductor device has an Al—Si—Cu film 405 as a plurality of metal wirings.
It has a silicon oxide film 407 formed therebetween, and a cavity 408 having upper and lower ends corresponding to the thickness of the Al-Si-Cu film 405 is formed in the silicon oxide film 407. In the semiconductor device having such a configuration, the electric lines of force generated between the wirings can be re-blocked to the maximum extent, and the dielectric constant between the wirings can be made uniform. Next, JP-A-4-
The semiconductor device of No. 207055 will be described with reference to FIG. In this semiconductor device, a parasitic capacitance between wirings is reduced by forming a cavity 507 between the first wirings 505 on which the sidewall insulating films 504 are formed.

[0004]

However, in the conventional semiconductor device shown in FIG.
07 is attached to the side wall of the wiring, so that the cavity 4 having a small relative dielectric constant is used.
There is a problem that there is a limit in widening the region of 08. Further, in the conventional semiconductor device shown in FIG. 8, since the silicon oxide film is used in the region where the lines of electric force draw an arc, there is a problem that the capacity cannot be reduced to the maximum.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and it is possible to reduce the parasitic capacitance generated between wirings as much as possible, and to solve the delay time caused by the capacitance between wirings of a semiconductor integrated circuit. An object of the present invention is to provide an apparatus and a method of manufacturing the same.

[0006]

In order to solve the delay time due to the capacitance between wirings of a semiconductor integrated circuit, the present inventor paid particular attention to the position through which the electric flux lines of the semiconductor device pass.
As shown in FIG. 6, a line of electric force 305 generated between wirings 303 formed on a semiconductor substrate 301 via a silicon oxide film 302 is drawn in an arc, and a relative dielectric constant of a region through which the line of electric force 305 passes is shown. It has been found that the delay time due to the capacitance between wirings of a semiconductor integrated circuit can be solved by reducing the parasitic capacitance generated between wirings by reducing the capacitance, and the present invention has been completed.

That is, the invention according to claim 1 is characterized in that a cavity having upper and lower ends corresponding to the thickness of a metal wiring is formed on a semiconductor substrate, and a silica layer is formed above the cavity. A semiconductor device is provided as a means for solving the above problem.
According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the silica layer is made of hydrogenated silicon oxide having a relative dielectric constant smaller than that of a silicon oxide film. And

According to a third aspect of the present invention, there is provided a semiconductor substrate having a metal wiring patterned using a silicon oxide film as a mask and having a groove between the metal wirings from the silicon oxide film side to the position of the silicon oxide film. A method for manufacturing a semiconductor device, characterized in that the method is immersed in a silica solution contained in a liquid storage dish, is provided as a means for solving the above problem. According to a fourth aspect of the present invention, after the semiconductor substrate is immersed in a silica solution, the semiconductor substrate is baked at 200 ° C. to 400 ° C. in a state where the semiconductor substrate is vertically lifted from the silica solution, and the opening of the groove is formed. A method for manufacturing a semiconductor device according to claim 3, wherein the silica solution held in the portion is cured.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of a semiconductor device and a method of manufacturing the same according to the present invention will be described below with reference to FIGS. FIG. 4 is a view showing one embodiment of the semiconductor device of the present invention. The method of manufacturing the semiconductor device of the embodiment of the present invention includes the following steps. First, as shown in FIG. 1, after a silicon oxide film 102 is formed on a flat surface of a semiconductor substrate 101, a Ti film 103, a TiN film 104, and an Al—Cu film are formed on the silicon oxide film 102 by a sputtering method or the like. 105, TiN
The film 106 is formed in order from the silicon oxide film 102 side.
Then, a thickness of 1 nm is formed on the TiN film 106 by a CVD method or the like.
A silicon oxide film 107 of about 2 μm is formed.

Next, after a photoresist is applied on the silicon oxide film 107, a pattern is formed by lithography. Next, the silicon oxide film 107, the TiN film 106, the Al—Cu film 105,
After the TiN film 104 and the Ti film 103 are etched to form a metal wiring (metal wiring 204 described later), the photoresist is removed, and then a silicon oxide film 108 is formed on these surfaces to a thickness of about 0.12 μm. When the film is formed as described above, a groove 110a is formed between the metal wirings.

Next, FIG.
The silica layer is formed as follows using a coating apparatus as shown in FIG. The coating apparatus in FIG. 5 includes a base 201 capable of vacuum-sucking the semiconductor substrate 101 and baking the semiconductor substrate 101, and a liquid storage tray 202 for storing the silica solution 203 and performing an immersion process. Is what it is. In order to form the silica layer using this coating apparatus, a fixed amount of the silica solution 203 is stored in advance in the liquid storage dish 202, and the semiconductor substrate 101 is turned upside down.
The semiconductor substrate 101 is supported by the base 201 such that the surface on the side of the silicon oxide film 108 faces downward (the direction of the liquid storage dish 202), and the base 201 is placed in the direction b (the direction of the liquid storage dish 202).
Go to Silicon oxide film 108 of semiconductor substrate 101
The movement in the direction b is stopped at the position where the silicon oxide film 107 is immersed in the silica solution, and the substrate 201 is immersed in the silica solution for a certain period of time. Moving. Here, the silica solution 203 is held between the metal wirings 204 by surface tension, and the upper opening of the groove 110a is covered with the silica solution 203. Here, the part immersed in the silica solution 203 is the silicon oxide film 10.
7 and a silicon oxide film 108 formed thereon. As the silica used for the silica solution 203, it is preferable to use silicon hydride or the like having a relative dielectric constant smaller than that of the silicon oxide film.

Then, the movement in the direction a is stopped at a position sufficiently distant from the silica solution 203, and the semiconductor substrate 101 is baked while being vertically lifted from the silica solution 203. Silica solution 203
Is hardened by the baking, and as shown in FIG. 2, the silica layer 1 is formed in the upper opening of the groove 110a between the silicon oxide films 107.
09 is formed, thereby forming the cavity 110. The temperature for baking the semiconductor substrate 101 is preferably in the range of about 200 ° C. to 400 ° C. In addition,
On the silicon oxide film 107, a silica layer 109 is formed, though slightly.

Next, as shown in FIG. 3, the silicon oxide film 108 and the silica layer 109 on the silicon oxide film 107 are removed by a known selective dry etching method or the like. Finally, as shown in FIG. 4, a silicon oxide film 111 which is an interlayer insulating film is formed, and a planarization technique such as CMP is performed. As a result, an interlayer insulating film having a lower dielectric constant than the conventional technique is formed. The intended semiconductor device is obtained. The semiconductor device thus obtained has a cavity 110 having upper and lower ends corresponding to the thickness of the metal wiring 204 formed on the semiconductor substrate 101, and a silica layer 109 formed on the cavity 110. Therefore, the region where the lines of electric force generated between the metal wirings 204 are the strongest is hollowed out, and the silica layer 109 having a small relative dielectric constant is disposed in the region where the lines of electric force draw an arc. It is possible to reduce the parasitic capacitance generated between them as much as possible, and it is possible to solve the delay time due to the capacitance between wirings of the semiconductor integrated circuit.

According to the method of manufacturing a semiconductor device of the embodiment, the semiconductor substrate 1 is immersed in the silica solution 203 put in the storage dish 202 from the silicon oxide film 107 side to the position of the silicon oxide film 107. This allows the silica solution 203 to be held in the opening of the groove 110a. Thereafter, the semiconductor substrate 1 is vertically lifted from the silica solution 203 and the semiconductor substrate 1 is kept at 200 ° C. to 40 ° C.
By baking at 0 ° C. to cure the silica solution 203 held in the opening of the groove 110a, the silica layer 109 is cured.
Can be formed, and the silica layer 109 forms a groove 110.
The upper opening of a may be closed to form a cavity 110.

[0015]

As described above, according to the semiconductor device of the present invention, a cavity having upper and lower ends corresponding to the thickness of a metal wiring is formed on a semiconductor substrate, and a silica layer is formed on the cavity. Therefore, the region where the lines of electric force generated between the metal lines are strongest is hollowed out, and the silica layer is disposed in the region where the lines of electric force draw an arc. The capacitance can be reduced closer to the maximum, and the delay time due to the capacitance between wirings of the semiconductor integrated circuit can be solved.

Further, according to the method of manufacturing a semiconductor device of the present invention, a semiconductor substrate having metal wirings patterned using a silicon oxide film as a mask and having a groove between these metal wirings is formed from the silicon oxide film side of the semiconductor substrate. By immersing the silica solution in the storage dish up to the position of the silicon oxide film, the silica solution can be held in the opening of the groove. Then, after immersing the semiconductor substrate in a silica solution, the semiconductor substrate is baked at 200 ° C. to 400 ° C. in a state where the semiconductor substrate is vertically lifted from the silica solution, and the silica held in the opening of the groove is baked. By curing the solution, a silica layer can be formed, and the opening of the groove can be closed by the silica layer to form a cavity.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view for explaining one embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 2 is a cross-sectional view for describing one embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 3 is a cross-sectional view for describing one embodiment of a method for manufacturing a semiconductor device of the present invention in the order of steps.

FIG. 4 is a cross-sectional view showing one embodiment of the semiconductor device of the present invention.

FIG. 5 is a view for explaining a coating apparatus for forming a silica layer of a semiconductor device of the present invention and a method for forming a silica layer using this apparatus.

FIG. 6 is a diagram illustrating lines of electric force generated between wirings of a semiconductor device.

FIG. 7 is a cross-sectional view illustrating an example of a conventional semiconductor device.

FIG. 8 is a cross-sectional view showing another example of a conventional semiconductor device.

[Explanation of symbols]

101: semiconductor substrate, 102: silicon oxide film, 103: Ti film, 104: TiN film, 10
5 ... Al-Cu film, 106 ... TiN film, 107
... silicon oxide film, 108 ... silicon oxide film,
109 silica layer, 110a groove, 110
・ Cavity, 111 ・ ・ ・ Silicon oxide film, 201 ・ ・ ・ Base, 202 ・ ・ ・ Storage dish, 203 ・ ・ ・ Silica solution, 2
04 ... wiring, 301 ... semiconductor substrate, 302 ...
-Silicon oxide film, 303 ... Wiring, 304 ... Silicon oxide film, 305 ... Electric force lines.

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[Procedure amendment]

[Submission date] February 22, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

That is, according to the first aspect of the present invention, a cavity having upper and lower ends corresponding to the thickness of a metal wiring is formed on a semiconductor substrate, and a silicon oxide film having a relative dielectric constant is formed above the cavity.
A semiconductor device characterized in that a smaller silica layer is formed is a means for solving the above problem. According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect, wherein the silica layer is made of hydrogenated silicon oxide having a relative dielectric constant smaller than that of a silicon oxide film. And

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction contents]

[0015]

As described above, according to the semiconductor device of the present invention, a cavity having upper and lower ends corresponding to the thickness of metal wiring is formed on a semiconductor substrate, and a relative dielectric constant is formed above the cavity.
Is formed with a silica layer smaller than the silicon oxide film , the strongest region of the electric lines of force generated between the metal wirings is hollowed out, and the silica layer is placed in the region where the lines of electric lines draw an arc. As a result, the parasitic capacitance generated between the wirings can be reduced as much as possible, and the delay time due to the capacitance between the wirings of the semiconductor integrated circuit can be solved. ────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] June 7, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0007

[Correction method] Change

[Correction contents]

That is, according to the first aspect of the present invention, a cavity having upper and lower ends corresponding to the thickness of a metal wiring is formed on a semiconductor substrate, and a silica layer is formed above the cavity.
The silica layer has a relative dielectric constant smaller than that of the silicon oxide film.
A semiconductor device characterized by being made of a hydrogenated silicon oxide is a means for solving the above problem.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0008

[Correction method] Change

[Correction contents]

According to a second aspect of the present invention, a semiconductor substrate having a metal wiring patterned by using a silicon oxide film as a mask and having a groove between the metal wirings is moved from the silicon oxide film side to the position of the silicon oxide film. A method for manufacturing a semiconductor device, characterized in that the method is immersed in a silica solution contained in a liquid storage dish, is provided as a means for solving the above problem. According to a third aspect of the present invention, after the semiconductor substrate is immersed in a silica solution, the semiconductor substrate is baked at 200 ° C. to 400 ° C. while the semiconductor substrate is vertically lifted from the silica solution, and the opening of the groove is formed. A method for manufacturing a semiconductor device according to claim 2 , wherein the silica solution held in the portion is cured.

Claims (4)

[Claims] 1. A semiconductor device, wherein a cavity having upper and lower ends corresponding to the thickness of metal wiring is formed on a semiconductor substrate, and a silica layer is formed on the cavity. 2. The semiconductor device according to claim 1, wherein said silica layer is made of hydrogenated silicon oxide having a relative dielectric constant smaller than that of a silicon oxide film. 3. A semiconductor substrate having metal wirings patterned with a silicon oxide film as a mask and having a groove between the metal wirings is placed in a liquid storage dish from the silicon oxide film side to the position of the silicon oxide film. A method for manufacturing a semiconductor device, characterized by immersing the semiconductor device in a silica solution. 4. After the semiconductor substrate is immersed in a silica solution, the semiconductor substrate is baked at 200 ° C. to 400 ° C. in a state of being vertically lifted from the silica solution and held in the opening of the groove. 4. The method for manufacturing a semiconductor device according to claim 3, wherein the prepared silica solution is cured.