JPH11297098A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory enabling the detection of a short circuit between internal word lines by applying an external voltage to pads. SOLUTION: All word lines WL1, WL2, WLk in the semiconductor memory are divided in a plurality of groups and the ends of the word lines are wired to pads P1, P2 through transistors TR1, TR2, TRk provided at the ends of all the word lines. At test, specified voltage is applied to the pads, a current flowing between the pads is measured to detect the short circuit between the word lines.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device in which a wiring end of a word line or a bit line is led to a pad so that a defective portion can be confirmed during a test.

[0002]

2. Description of the Related Art In semiconductors, especially in memory ICs, various test methods at the time of manufacturing have been devised and used by utilizing the regularity of the structure. FIG. 2 shows a semiconductor device disclosed in JP-A-8-167299. FIG. 2 shows a peripheral circuit of a driver for a word line of a memory IC, where reference numerals 2-7, 2-8, 2-9, 2
-10 is an address decoder, 20 and 30 are mode setting circuits, 21 and 31 are pads, 7A and 7B are memory cell arrays, wl1, wl2, rwl1, and rwl2.
Indicates a word line.

Here, in a circuit having a structure in which a plurality of word lines are simultaneously selected, when a specific word line wl1 in the memory cell array 7A is short-circuited to the ground potential, another memory cell array 7B which is simultaneously selected is selected. In order not to affect the word line wl2, a voltage is applied to the pad 21, the address decoder 2-7 is forcibly disabled, and the memory cell array 7A is masked. This is to avoid the influence of wl1 and to perform a test on the memory cell array 7B.

[0004]

In manufacturing a semiconductor device such as a memory IC, in order to improve the yield, it is necessary to specify a defective portion and analyze the defective portion, and feed back the result to a production process. . For that purpose, it is necessary to find out a defective part and investigate its cause in a short time and accurately. In the above example of the conventional device, by using the circuit shown in FIG. 2, it is possible to know which word line of which memory cell array has an abnormality.

However, in an actual test, if an attempt is made to identify an abnormal portion, an appropriate voltage is applied to all pads of the memory IC to be tested at an appropriate timing, and then an emission microscope and a liquid crystal analyzer are used. It is necessary to perform a detailed analysis by using the method described above, which is not always easy. Further, in the above-described conventional example, it is impossible to confirm the transition of the steady occurrence of the electrical short using the mass-produced product. The present invention has been made in view of such circumstances, and when a test is performed on a semiconductor memory device, a short-circuit between wirings inside the semiconductor memory device is applied for a short time by applying an external voltage to a small number of pads. It is an object of the present invention to provide a semiconductor memory device which can be detected by the method.

[0006]

According to the first aspect of the present invention,
All the word lines are classified into a plurality of groups, and each word line is connected to one pad assigned to each group after passing through a switch at the end of each line. This is a semiconductor memory device. According to a second aspect of the present invention, all the bit lines are classified into a plurality of groups, and each of the bit lines is connected to one pad assigned to each of the groups after passing through a switch at the end of each wiring. A semiconductor memory device characterized by being connected. According to a third aspect of the present invention, in the semiconductor memory device of the first or second aspect, the switch is realized by a transistor.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor memory device according to one embodiment of the present invention will be described with reference to the drawings. FIG.
FIG. 2 is a diagram showing a part of a circuit of a memory IC which is a semiconductor storage device according to an embodiment of the present invention, and has a structure in which word lines are grouped and connected to pads as shown in FIG. This is an example. Here, symbols P1, P
Reference numeral 2 denotes a pad of the memory IC, which is used during a test. Symbols WL1, WL2, and WLk are word lines of the memory IC, and are connected to gate terminals of respective memory cells in the memory IC. Reference numerals TR1, TR2, and TRk denote switching transistors at the time of a test. Each of the word lines WL1, WL2, and WLk has a terminal at the end thereof.
The transistors TR1, TR2, TRk are connected respectively.

The transistors TR1, TR2, TRk
Of the word lines WL1, WL2,
WLk is connected to or disconnected from pads P1 and P2. During normal operation of the memory IC, the transistors TR1, TR2, TRk are turned off, and the word line WL is turned off.
1, WL2 and WLk are electrically disconnected from the pads P1 and P2. When the memory IC is tested, the transistors TR1, TR2, and TRk are turned on, and the word lines WL1, WL2, and WLk are electrically connected to the pads P1 and P2.

The correspondence between the word lines and the pads is assigned so that any adjacent word lines are not connected to the same pad. In the present embodiment, since two pads P1 and P2 are used as test pads, adjacent word lines are alternately assigned to one of the pads P1 and P2. The symbol GL represents the transistor T
This is a gate line commonly connected to the gate terminals of R1, TR2, and TRk, and the transistors TR1, TR2, and TRk are simultaneously turned on or off depending on the potential applied thereto.

Next, the memory I which is the semiconductor memory device
The operation during the test of C will be described. First, when testing the memory IC, a high potential is applied to the gate line GL in FIG. 1 to turn on all the transistors TR1, TR2, and TRk. Thereafter, as an example, a voltage of 3 V is applied to the pad P1 connected to the word line WL1, and a voltage of 0 V is applied to the pad P1 connected to the word line WL2. If there is a short part somewhere between the word lines WL1 and WL2, a closed path is formed between the pad P1 and the pad P2 through the short part, and the pad P1 is connected to the pad P2. Electric current flows. As a result, it is confirmed that there is a short circuit between the word lines, and a defective portion can be confirmed.

In the above-described embodiment, the short circuit between the word lines is detected by using two test pads P1 and P2. However, N test pads (N ≧ 3) are used.
It is also possible to use In this case, by dividing the word lines of the semiconductor memory device to be tested into N-1 groups, it is possible to specify a short-circuited portion in any one of them, and to further analyze the cause of the defect. Therefore, it is possible to shorten the test time and increase the efficiency.

Further, in the above-described embodiment, a dedicated pad is prepared as a test pad. However, by using a selector circuit or the like, input to the pad is switched between a test and a normal operation, and the pad is switched. It is also possible to use them both. As a result, an increase in the number of pads can be prevented, and short-circuit detection of a word line can be performed without affecting the number of input / output pins of the semiconductor.

In the above description, the end of the word line is connected to the pad via the switching transistor in order to detect a short circuit between the word lines. However, the bit lines are divided into a plurality of groups in exactly the same manner. Then, the terminal of each bit line can be connected to a pad via a switching transistor. As a result, a short circuit between bit lines can be detected by applying an appropriate voltage to the pad from the outside in the same manner as described above.

[0014]

As described above, according to the semiconductor memory device of the present invention, by applying a voltage to a small number of pads from the outside during testing, a short circuit between wirings inside the semiconductor memory device can be prevented. Detection can be performed in a short time.

[Brief description of the drawings]

FIG. 1 is an internal circuit diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 P1, P2 ... Pad TR1, TR2, TRk ... Transistor WL1, WL2, WLk ... Word line GL ... Gate wiring wl1, wl2, rwl1, rwl2 ... Word line 7A, 7B ... Memory cell array 2-7, 2-8, 2- 9, 2-10: Address decoder 21, 31: Pad 20, 30: Mode setting circuit

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[Procedure amendment]

[Submission date] March 12, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction contents]

[0006]

According to the first aspect of the present invention,
All the word lines are classified into a plurality of groups, each word line described above after through the switch at the end of each line, in a semiconductor memory device that will be connected to one pad assigned for each of the groups, Each of the above
Out of multiple pads to which
Select one of them, and apply high potential to one pad and
Give a low potential to the pad and flow between these two pads
By measuring the current, it is connected to the two pads.
Feature to detect the presence or absence of an electrical short between word lines
This is a semiconductor storage device. According to a second aspect of the present invention, all the bit lines are classified into a plurality of groups, and each of the bit lines is connected to one pad assigned to each of the groups after passing through a switch at the end of each wiring. in the semiconductor memory device that will be connected, each
Any two of the pads to which the bit lines are connected
Select a pad, apply high potential to one pad, and
A low potential is applied to the other pad, and a current flows between the two pads.
By measuring the current flowing through the two pads,
Detecting the presence or absence of an electrical short between successive bit lines
A semiconductor memory device characterized by the following. According to a third aspect of the present invention, in the semiconductor memory device according to the first or second aspect, the switch of each word line has its gate terminal connected.
It is characterized by being realized by transistors connected in common .

Claims (3)

[Claims] 1. All word lines are classified into a plurality of groups, and each of the word lines is connected to one pad assigned to each of the groups after passing through a switch at the end of each line. A semiconductor memory device characterized by the above-mentioned. 2. All the bit lines are classified into a plurality of groups, and each of the bit lines is connected to one pad assigned to each of the groups after passing through a switch at the end of each wiring. A semiconductor memory device characterized by the above-mentioned. 3. The semiconductor memory device according to claim 1, wherein said switch is realized by a transistor.