JPH11297077A - Method of judging over-erase of memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To judge the over-erase of a flash memory at a high reliability so enough that the judge result of the over-erase judgment of the memory at room temp. holds when using at high temp. SOLUTION: The judging method sets the control gate voltage of each word line 300 to 0.5 V slightly higher than 0 V at non-select time on the occasion of the over-erase judgement of flash memory cells 1, 2, 3,... at room temp. whereby the leak current flowing on a drain line 100 slightly increases and a margin of the leak quantity can be taken for the temp. esp. high temp. If, in this condition, the leak current flowing on the drain line 100 exceeds a reference, it judges that an over-erased cell exists and this judgement holds when used at a high temp. and such wrong judgement can be eliminated that it would judges that an over-erased cell does not exist at room temp. but appears when used at a high temp.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a single memory having a flash memory for performing batch or block erasing, or a microcomputer or AS.
The present invention relates to a method for judging excessive erasure of a flash memory used in a flash memory mixed logic circuit such as an IC (Application Specific IC).

[0002]

2. Description of the Related Art Conventionally, a flash memory, particularly a flash memory having a NOR cell structure, has an overerasing characteristic. Flash memory is electrically erased like EEPROM (generally using the tunnel phenomenon)
Is a possible memory. That is, to erase the data written in the flash memory cell, a high voltage for erasing is applied to the source, and the control gate (hereinafter the same as the word line) is set to the ground level or a potential lower than that. As a result, a large potential difference is applied between the source and the gate of the flash memory, and electrons in the floating gate become currents due to a tunnel phenomenon via the insulating film and are drawn toward the source, thereby erasing stored data.

[0003] However, when this electric erasure is performed excessively, electrons are excessively extracted from the floating gate, the threshold voltage of the memory keeps decreasing, and finally the floating gate is positively charged and becomes a depleted cell.

That is, the potential of the control gate of the flash memory is not selected, that is, the control gate voltage =
Even when the state becomes 0 (V), the memory is in a state where the off-leak continues to flow.

FIG. 2 shows this state, and the uppermost flash memory cell (sometimes simply referred to as a memory cell) 11 has become a depleted cell due to excessive erasure. As a result, like the memory cell 12 to which data is written (ie, off-cell), the word lines 300,
That is, when the voltage of the control gate is set to VDD and the data is read from the memory cell 12, even if the word line 300 of the top memory cell 11, that is, the control gate is at the non-selection voltage of 0V, Since a leak current (hereinafter, sometimes simply referred to as a leak) generated between the drain and the source of the memory cell 11 is loaded on a drain line (hereinafter, the same as a bit line) 100, normal data is read from the original read memory cell 12. Cannot be read.

[0006] When the above phenomenon is severe,
When a high voltage is applied to the drain line 100, for example, when data is written to another memory cell 13, the leakage of the over-erased memory cell 11 causes
The drain voltage does not rise to the write level, and writing to the memory cell 13 becomes impossible.

Therefore, in the case of the above-mentioned flash memory (including logic embedded), conventionally, the data in the memory is not erased at once, but is weakly erased as intelligent erasing → all memory cell reading → blank (no data) judgment cycle. Is repeated so that the erasure is stopped at an appropriate place.

However, even if the above algorithm is used, the memory cells which are most likely to be erased by the time the erased memory cells pass the erase determination level and are completely erased due to variations in the characteristics of the flash memory cells of the product. There are many cases where excessive erasure occurs.

For this reason, at the time of a shipping test, it is necessary to determine whether or not excessive erasure occurs. In addition, depending on the product, the characteristics of excessive erasure may change due to the write / erase cycle after shipment, and most products having a large memory capacity have a “self-converging mode”.

Here, the self-convergence means that after the normal erase routine, it is automatically determined whether or not excessive erasure has occurred. If excessive erasure has occurred, the memory whose threshold voltage has become low is determined. This is a relief algorithm (built-in circuit) that suppresses excessive erasure by applying a weak gate stress to the cell and raising the threshold voltage.

At the time of shipment or when the device has a function of self-convergence, both devices usually have an over-erasure detection function. In this conventional function, as shown in FIG.
By setting the voltage of the word line 300 of 1, 12, 13,..., That is, the voltage of the control gate to 0 V, which is not selected, it is checked whether or not the memory cells 11, 12, 13,. Done. That is,
If none of the memory cells is excessively erased, the drain line (bit line) 100 is determined to be in an off state because the voltage of the control gate is unselected 0V. If there is even one, a leak occurs in the bit line where the memory cell is present, and the bit line is not normally determined to be in the off state, and excessive erasure is detected.

[0012]

As described above, since the phenomenon of excessive erasure occurs in the conventional flash memory, as a countermeasure, there is the technique of the above-described excessive erasure determination method. However, this conventional over-erasure determination method does not consider the over-erasure determination level based on the temperature difference, and causes the following disadvantages.

That is, in the conventional over-erase determination method, each word line 300 of the memory cells 11, 12, 13,.
That is, it is determined whether or not there is a leak between the drain and the source of each memory cell when the voltage of the control gate is 0V. The control gate voltage of 0 V is the same as the voltage of the word line 300 of the unselected cell at the time of normal reading or writing is 0 V,
Therefore, even if the word line 300 is in a non-selected state, it is determined whether or not the leak amount allows normal reading.

However, even if the above determination is made after the erasure of the memory cell at normal temperature and it can be determined that excessive erasure has not occurred, the word line 300 of the non-selected memory cell is also kept at 0 V even at the time of high-temperature reading. (Control gate voltage is 0 V), and the amount of leakage of each of the memory cells 11, 12, 13,... At room temperature and at high temperature is different, and the amount of leakage at high temperature tends to increase. For this reason, even if the leakage current is determined to be less than the reference value at normal temperature in the excessive erasure determination as described above, and the excess erasure is not performed, the leakage current increases at a high temperature, exceeds the reference value, and indicates that there is excessive erasure. May be determined.

That is, if the determination is only made when the control gate voltage of the memory cells 11, 12, 13,... Is set to 0 V, the difference in the amount of leakage when the temperature is different (particularly at a high temperature) is not taken into account. Erroneous determination may occur. In the worst case, there is a problem that even if a memory cell is determined to be erased at room temperature and not to be over-erased, it cannot be read when used at a high temperature, and may be over-erased. Was.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to determine whether an excessive erasure of a flash memory is performed at a normal temperature and the result of the determination is valid even when the flash memory is used at a high temperature. An object of the present invention is to provide a method for judging excessive erasure of a memory with high reliability.

[0017]

In order to achieve the above object, a first aspect of the present invention has a feature that a floating gate, a control gate, a source, and a drain are provided. In the flash memory that stores the data, when determining the excessive erasure of the memory caused by the emission of electrons being too large, a voltage higher than a non-selected control gate voltage is applied as the control gate voltage, and The purpose of the present invention is to determine the excessive erasure of the memory based on the magnitude of the leak current between the sources.

According to the first aspect of the invention, when a voltage slightly higher than the zero volt is applied as the control gate voltage at the time of the determination of the excessive erasure, the leakage between the drain and the source of the flash memory becomes higher than at the time of the zero volt. The current increases. On the other hand, when the control gate voltage is set to zero volt and the ambient temperature is increased, the leak current increases. Therefore, when the over-erasing is determined at room temperature, if the control gate voltage is slightly higher than the zero volt, for example, 0.5 volts, the control gate voltage is set to zero volt and the over-erasing is determined at a high temperature. Is performed, the same effect is obtained. In this case, the flash memory determined to have excessive erasure has the same determination even at a high temperature. Therefore, when the flash memory determined to have no excessive erasure in the determination of excessive erasure at room temperature is used at a high temperature, it does not become an over-erased flash memory and does not cause any trouble.

A feature of the second invention resides in that a voltage applied to the control gate is changed according to an ambient temperature at the time of determining the over-erasing.

According to the second aspect of the invention, the voltage applied to the control gate is changed according to the ambient temperature at the time of determining the excessive erasure. At the time of high temperature determination, the control gate voltage is set to 0 volt and an appropriate margin is set for the ambient temperature, so that the most reliable determination result can be obtained. For example, when the control gate voltage is set to 0.5 volt at the time of determining the high temperature, it may be determined that the flash memory that is not overerased even at high temperature or room temperature is overerased, and an erroneous determination occurs.

A feature of the third invention is that it has a floating gate, a control gate, a source and a drain,
In a flash memory which stores data by injecting and emitting electrons into and from the floating gate, excessive erasure of the memory caused by excessive emission of electrons is determined by the magnitude of leakage current between the drain and source. In this case, the detection sensitivity for the presence of excessive erasure is improved.

According to the third aspect of the invention, when the detection sensitivity for the presence of the excessive erasure is increased at the time of the determination of the excessive erasure at normal temperature, the excess erasure can be performed with less leakage current between the drain and source of the flash memory than usual. It will be determined that there is. This takes into account the increase in leakage current between the drain and source when the flash memory is used at a high temperature.Thus, it is determined that there is no excessive erasure at room temperature due to the increase in the leakage current. It can be prevented from being determined. Therefore, when the flash memory determined to have no excessive erasure in the determination of excessive erasure at room temperature is used at a high temperature, it does not become an over-erased flash memory and does not cause any trouble.

A feature of the fourth invention resides in that the reference current for judging the magnitude of the leak current is made lower than that at the time of normal reading in order to enhance the detection sensitivity.

A fifth feature of the invention resides in that the detection sensitivity for the presence of excessive erasure is changed depending on the ambient temperature at the time of determining the excessive erasure.

According to the fifth aspect, the detection sensitivity is changed according to the ambient temperature at the time of the determination of the excessive erasure, for example, the detection sensitivity is increased at the time of the determination of the normal temperature,
When determining a high temperature, the detection sensitivity is set as a standard, and an appropriate margin is set for the ambient temperature, so that the most reliable determination result can be obtained. For example, if the detection sensitivity is increased even when determining the high temperature, the flash memory that is not overerased even at high temperature or room temperature may be determined to be overerased, and an erroneous determination occurs.

[0026]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of a flash memory circuit for explaining a method for judging excessive memory erasure of the present invention. A plurality of electrically rewritable flash memory cells (sometimes simply referred to as memory cells) 1, 2, 3,... Are connected in parallel to a drain line (bit line) 100 and a source line 200. The sense amplifier 4 that amplifies a read signal and determines a write value is connected to the drain line 100. The control gate of each memory cell is connected to the word line 300.

Next, the operation of this embodiment will be described. For example, data is written into the flash memory cell 1 by applying VDD to the word line 300 of the memory cell 1, ie, the control gate, and applying a high voltage to the drain line 100. In addition, VDD is applied to the gate of the flash memory cell 1 to transfer the data from the flash memory cell 1 to the drain line 100.
Read through.

Thereafter, the flash memory cells 1, 2,.
When erasing the stored data of the flash memory cells 1, 2,... At a time, a high voltage for erasing is applied to the source line 200 and the word lines 10 of the flash memory cells 1, 2, 3,.
When the control gate is set to a voltage equal to or lower than the ground level, a large potential difference is applied between the source and the gate of each memory cell, and electrons in the floating gate of each memory cell flow through the insulating film to generate a current due to a tunnel phenomenon. Are pulled out to the source side, thereby erasing the data stored in the memory cells 1, 2, 3,...

Next, a description will be given of a method of judging excessive erasure of the present embodiment when erasing of the flash memory cells 1, 2, 3,. When determining excessive erasure, each word line 300 of the flash memory cells 1, 2, 3,...
That is, each control gate voltage is set to about 0.5V. The level to which this voltage is set cannot be unconditionally determined because it depends on the off-leak characteristic (temperature characteristic) of the memory cell to be used. Set to several volts.

Thereafter, the magnitude of the leakage current of the drain line 100 is checked via the sense amplifier 4. If the leakage current is larger than the reference value, it is determined that there is an overerased flash memory cell. If it is smaller, it is determined that there is no such item.

By the way, in the present embodiment, the over-erasing judgment which is performed at room temperature by applying 0 V to the control gate of each memory cell in the related art is performed by applying 0.5 V to the control gate of each memory cell.
Since a voltage higher than V is applied, the leakage current between the drain and the source of each memory cell tends to increase. In other words, this is similar to the case where the control gate voltage of each memory cell is set to 0 V and the overerasing is determined at a high temperature.

Further, this means that while the unselected word line 300 at the time of reading, that is, the control gate voltage becomes 0 V, at the time of judging excessive erasure, the control gate voltage is set to a margin for the temperature of the leak current amount. This means that the judgment is made at a higher voltage. Therefore, if the over-erasure is determined at a control gate voltage higher by 0.5 V, if the over-erasure determination determines that there is no excessive erasure at room temperature, it can be said that there is no over-erasure at high temperature.

According to the present embodiment, the voltage of the control gate of the flash memory cell 1, 2, 3,... At the time of judging excessive erasure at room temperature is 0 V which is the control gate voltage of the non-selected memory cell at the time of reading. Than 0. Performed at a voltage several volts higher, the flash memory cells 1, 2,
By taking a margin with respect to the temperature (high temperature) of the amount of leakage current between the drain and the source of 3,..., The determination that there is no excessive erasure in the excessive erasure determination at room temperature is the same as the determination that there is no excessive erasure in the high temperature excess erasure determination. Thus, it is possible to perform the reliable overerasure determination at room temperature, which is valid even when the memory cell is used at a high temperature.

When the over-erasure determination is performed at a high temperature,
It is appropriate that the control gate voltage of the memory cell is 0V. That is, there is an appropriate control gate voltage depending on the ambient temperature of the over-erasure determination, and by setting an appropriate control gate voltage, an appropriate temperature margin corresponding to the ambient temperature at the time of the determination is obtained, and The determination result of the excessive erasure determination is secured in a wide temperature range including the ambient temperature at the time of the erasure determination.

Next, a description will be given of a second embodiment of the method for judging excessive erasure of a flash memory according to the present invention. However,
Since the configuration of the flash memory circuit is the same as that of the first embodiment shown in FIG. 1, it will be described below with reference to FIG.

In this embodiment, the control gate voltage of the flash memory cells 1, 2, 3,... At the time of judging excessive erasure at room temperature is set to 0 V, which is the same as that at the time of non-selection. The sensitivity of the sense amplifier 4 at the time of measurement is set higher than before by taking a margin for the amount of leak current with respect to the temperature, so that the leak current measured by the sense amplifier 4 easily clears the reference value and is smaller than before. It is determined that there is an excessively erased flash memory cell even with the amount of leak current. Thereby, the present embodiment also
There is an effect similar to that of the first embodiment.

The same effect can be obtained even if the sensitivity of the sense amplifier 4 is set to the same level as before, and the reference for determining the magnitude of the leak current is set low. Further, the degree of increasing the sensitivity of the sense amplifier 4 cannot be determined unconditionally because it depends on the off-leak characteristic (temperature characteristic) of the memory cell to be used. There is an appropriate sensitivity value of the sense amplifier 4 taken.

[0038]

As described above in detail, according to the method for judging excessive memory erasure of the present invention, the control gate voltage is set to be higher or the detection sensitivity for the existence of excessive erasure is increased when judging excessive memory erasure. By setting, it is possible to make the determination result when the over-erasing determination of the flash memory is performed at normal temperature valid even at the time of use at high temperature, and to improve the reliability of the determination result.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a flash memory for explaining a memory over-erasure determination method of the present invention.

FIG. 2 is a flash memory circuit diagram illustrating a case where excessive erasure occurs in a flash memory cell.

FIG. 3 is a flash memory circuit diagram illustrating a conventional memory over-erase determination method for determining the presence or absence of an over-erased flash memory cell.

[Explanation of symbols]

 1, 2, 3 Flash memory cell 4 Sense amplifier 100 Drain line (bit line) 200 Source line 300 Word line (control gate line)

Claims (5)

[Claims] 1. A flash memory having a floating gate, a control gate, a source, and a drain and storing data by injecting or emitting electrons into or from the floating gate. When determining excessive erasure of the memory, as the control gate voltage, multiply a voltage higher than the unselected control gate voltage,
A method for judging excessive erasure of a memory according to the magnitude of the leakage current between the drain and the source, the method comprising: 2. The method according to claim 1, wherein a voltage applied to the control gate is changed according to an ambient temperature at the time of determining the excessive erasure. 3. A flash memory having a floating gate, a control gate, a source, and a drain and storing data by injecting and emitting electrons into and from the floating gate, wherein the memory is generated when the emission of the electrons is too large. A method of judging excessive erasure of a memory, wherein the detection sensitivity of the presence of excessive erasure is enhanced when judging the excessive erasure by the magnitude of the leak current between the drain and the source. 4. The method according to claim 3, wherein a reference current for judging the magnitude of the leak current is set lower than that in a normal read operation to increase the detection sensitivity. 5. The method according to claim 3, wherein the detection sensitivity for the presence of excessive erasure is changed according to the ambient temperature at the time of determining the excessive erasure.