JPH11297068A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of times of a refresh operation by an internal clock while the normal operation of a dynamic random-access memory(DRAM) is being generated. SOLUTION: In a semiconductor storage device, a memory cell region is divided into a region 1 far from sense amplifiers SA1 to SAn and a region 2 close to the sense amplifiers SA1 to SAn, and the refresh cycle of a memory cell in the region 2 is set to be longer than that of the region 1 in a refresh operation by an internal clock. Thereby, the number of times of a refresh operation which is performed within a set time becomes smaller than that in a conventional circuit, and it is possible to obtain an effect to reduce a power-supply noise or to reduce a power consumption.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device,
In particular, it relates to a dynamic random access memory (hereinafter, referred to as DRAM).

[0002]

2. Description of the Related Art In general, a DRAM needs to perform a periodic rewrite operation of stored data, that is, a refresh operation, in order to keep retaining data stored in a memory cell.

FIG. 7 shows a simplified diagram of a peripheral portion of a memory cell in a conventional DRAM. 7, reference numerals 701 to 708 denote memory cells; 723, an internal address counter circuit;
4 is a decoder circuit, 725 is a clock signal generation circuit, and W is
L1 to WLm are word lines, BL1, / BL1 to BLn,
/ BLn is a bit line pair, and SA1 to SAn are sense amplifiers.

In FIG. 7, Φ denotes a clock signal for determining a refresh interval when a refresh operation is controlled by an internal clock such as a self-refresh in a DRAM, for example, after a certain memory cell is refreshed once. The interval until the next refresh is performed (hereinafter referred to as a refresh cycle) is set to be T1. Φ is the clock signal generation circuit 7
25. Clock signal generation circuit 725
11 is shown in FIG. In FIG. 11, reference numeral 1101 denotes an inverter; 1102, a NAND gate; 1103, an even-numbered-stage inverter; and REF, a control signal which becomes H at the time of refreshing by an internal clock. As can be seen from FIG. 11, Φ is a clock signal when the control signal REF is H, and is always L when REF is L.

The internal address counter circuit 723 generates signals A0 to Ax according to the clock signal Φ, and is composed of a flip-flop or the like. Here, A0 to A
x is an address signal for controlling the selection of a word line;
0 to Ax is decoded by the decoder circuit 724, and one of the word lines WL1 to WLm is selected (A0 to Ax
The number of combinations of the states is m). FIG. 8 shows the configuration of the internal address counter circuit 723. FF in FIG.
0 to FFx are flip-flops having a function of inverting the state of the output each time the input changes from H to L (the circuit operation of FIG. 8 is shown in FIG. 9).

The refresh operation in the circuit of FIG. 7 will be described with reference to the timing chart of FIG. When the control signal REF changes from L to H, Φ becomes a clock signal, the internal address counter circuit 723 generates address signals A0 to Ax according to the clock signal Φ, and the decoder circuit 724 generates the address signals A0 to Ax. Decodes one word line WLi of WL1 to WLm
(I = 1 to m) is selected (the word line becomes H at the time of selection). One row of memory cells connected to the selected word line WLi is connected to the connected bit line (BL1 to BLn or / BL).
1 / BLn), and discharges the stored data as charges. The discharged charges are amplified by the sense amplifiers SA1 to SAn, and the amplified charges are transferred to the bit line pair BL1, / BL
1 to BLn and / BLn, and are again input to each memory cell as storage data. When the memory cells in one row are refreshed in this manner, the decoder circuit 7
24 selects the next word line WL (i + 1), and the same operation is repeated thereafter. Thus, word lines are successively selected, and when the control signal REF becomes L, Φ becomes L and the refresh is completed.

[0007]

As described above,
Since the refresh operation is an operation of amplifying storage data read from a memory cell to a bit line pair and writing the data back into the memory cell, a charge / discharge operation of the bit line pair is involved in the process of amplifying the storage data. . Since this charge / discharge operation is performed almost simultaneously on each bit line pair to which the selected memory cell is connected, the current flowing through the entire chip by the charge / discharge operation (hereinafter, referred to as charge / discharge current) is instantaneously increased. The current becomes a factor that adversely affects circuit operation such as generation of power supply noise. Therefore, reducing the number of refreshes leads to lower power consumption and more stable circuit operation.

However, a series of refresh operations must be performed before data stored in each memory cell is lost. In order to normally refresh the data stored in the memory cell, it is necessary that the change in the potential of the bit line caused by the charge released by the memory cell at the time of the selection is equal to or more than a certain amount. The amount of potential change generally depends on the capacity of the bit line, and the smaller the bit line capacity, the larger the change. Therefore, the smaller the bit line capacity, the longer the refresh cycle can be set. However, in the conventional circuit, the capacity of the bit line connected to each memory cell at the time of selection is the same regardless of the distance from the sense amplifier. Therefore, in the case of a memory cell near the sense amplifier, if an unnecessary portion of the bit line (a portion of the bit line other than between the selected memory cell and the sense amplifier) is cut, the bit line capacity can be reduced. Had the same bit line capacitance as a memory cell located far from the sense amplifier. As a result, when the memory cell is selected, the amount of potential change generated on the bit line is almost the same as that of the memory cell located far from the sense amplifier, so that the refresh cycle cannot be set long.

The present invention has been made to solve such a problem. When a selected memory cell is close to a sense amplifier at the time of refreshing by an internal clock, the refresh cycle is set to be long to reduce the number of refreshes of the entire chip. It aims to stabilize circuit operation and reduce current consumption.

[0010]

Therefore, a semiconductor memory device according to the present invention comprises a plurality of word lines, a plurality of bit line pairs, and memory cells respectively arranged and connected at intersections of the word lines and the bit lines. A semiconductor memory device having a function of selecting the memory cell and refreshing stored data stored at a predetermined cycle, wherein the bit line dividing circuit cuts the bit line pair at a predetermined position; A word line control circuit for limiting selection of the memory cell, the operation of the bit line division circuit is controlled according to the arrangement position of the memory cell selected at the time of refresh, and the word line control circuit is controlled according to the number of times of execution of the refresh. The operation is controlled.

[0011]

According to the semiconductor memory device of the present invention, when a memory cell located closer to the sense amplifier is selected at the time of refreshing, the bit line of the memory cell located farther from the sense amplifier is cut off. Thus, the capacity of the bit line connected at the time of the selection is reduced, and the refresh cycle can be set longer. As a result, the number of refreshes performed on the entire chip within a certain period of time is smaller than that of the conventional circuit, so that the generation of power supply noise due to refresh is suppressed, the circuit operates stably, and the current consumption accompanying refresh is reduced. Is done.

[0012]

FIG. 1 shows a simplified diagram of an embodiment of the present invention. In FIG. 1, reference numerals 101 to 112 denote memory cells, 1
13 is a bit line dividing circuit composed of N-channel transistors 114 to 117, P-channel transistors 118 to 121 and an inverter 122, 123 is an internal address counter circuit, 124 is a decoder circuit, 125 is a clock signal generation circuit, and 126 is an inverter. , 127 are word line control circuits, WL1 to WLk and WL (k + 1) to WL
m is a word line, BL1, / BL1 to BLn, and / BLn are bit line pairs, and SA1 to SAn are sense amplifiers.

The memory cell region in FIG. 1 includes a region 1 far from the sense amplifiers SA1 to SAn and a sense amplifier S1.
A bit line dividing circuit 11 is connected to an area 2 near A1 to SAn.
Divided through three.

Φ is a clock signal for determining the refresh interval when the refresh operation is controlled by the internal clock.
It is set to be. Φ is generated by the clock signal generation circuit 125. Here, the configuration of the clock signal generation circuit 125 is as shown in FIG. Therefore, Φ becomes a clock signal when the control signal REF is at H, and always becomes L when REF is at L.

The internal address counter circuit 123 is a circuit for generating signals A0 to Ax according to the clock signal Φ, and is composed of a flip-flop or the like. Here, A0 to A
x is an address signal for controlling the selection of a word line;
0-Ax is decoded by the decoder circuit 124 and one of the word lines WL1-WLk and WL (k + 1) -WLm is decoded.
A book is selected (the number of combinations of states A0 to Ax is m
Is). FIG. 2 shows the configuration of the internal address counter circuit 123. In FIG. 2, FF0 to FF (x + 1) are flip-flops having a function of inverting the output state each time the input changes from H to L, and 201 is a NAND gate. Ax of A0 to Ax is an address signal for determining an area, and when Ax is L, the word line of area 1
When x is H, the word line in region 2 is selected by the decoder circuit 124. Here, reference numeral 202 denotes a circuit similar to that of FIG. 8 showing a conventional circuit.
The timing chart shown in FIG. W in FIG.
LCTL is a word line control signal. When WLCTL is L, the corresponding word line is in a non-selected state. FIG. 3 is a timing chart showing the operation of WLCTL. As can be seen from FIG. 3, during the period when the control signal REF is at H, every time the address signal Ax changes from H to L, WLC
The state of TL is inverted. When the control signal REF is L, WLCTL is H regardless of the state of the signal CTLF.
Becomes

The bit line dividing circuit 113 generates an address signal A
When Ax is H, the bit lines of the regions 1 and 2 are disconnected, and when Ax is L, the bit lines of the regions 1 and 2 are connected. Here, the bit line dividing circuit 113 generates the bit line pair BL1, / BL1 to BLn, /
The capacitor is arranged at a position where the capacity of BLn is divided into two on the side of the region 1 and the side of the region 2.

The word line control circuit 127 outputs the signal WL (k +
1) A circuit for limiting selection of WLm (word line in region 2), including an inverter 401 and a NAND gate 402 as shown in FIG. 4, and a word line control signal WLCTL output from an internal address counter circuit 123 and a decoder circuit The operation is controlled by the output signal 124. As is apparent from the circuit configuration of FIG. 4, the word line control signal WLCTL
And when the output signal of the decoder circuit 124 is H
(K + 1) to WLm are H (selected state), and at other times, WL (k + 1) to WLm are L (unselected state). Here, from FIG. 3, for each memory cell in the region 1 and the region 2, the selection is performed once every two times with WLCTL being L, so that WL (k + 1) to WLm (region 2
Is selected every other time. As a result, WL (k + 1)-
Memory cell connected to WLm (memory cell in region 2)
, The refresh cycle is twice as long as the refresh cycle T1 of the area 1.

The refresh operation of the present invention will be described with reference to FIG.

First, the case where the first word line of the refresh belongs to the area 1 will be described with reference to the timing chart of FIG. 5 (the case where the initial state of the signal CTLF in FIG. 2 is L). Control signal RE
When F changes from L to H, Φ becomes a clock signal, and the internal address counter circuit 123 generates address signals A0 to Ax according to the clock signal Φ. Here, since the first word line of the refresh belongs to the area 1, the address signal Ax is L, and the bit line dividing circuit 1
13 connects the bit lines of the region 1 and the region 2 respectively. The decoder circuit 124 includes address signals A0 to Ax
And one word line WLi (i = 1 to k) of WL1 to WLk is selected. Selected word line WLi
, Discharges stored data as charges to the connected bit lines (BL1 to BLn or / BL1 to / BLn). The discharged charges are amplified by the sense amplifiers SA1 to SAn, and the amplified charges are sent back to the bit line pairs BL1, / BL1 to BLn, / BLn, and are again input to each memory cell as storage data. When the memory cells in one row are refreshed in this manner, the decoder circuit 124 sets the next word line WL.
(I + 1) is selected, and the same operation is repeated thereafter.
After all of WLi to WLk are selected in this way, the address signal Ax changes from L to H, and thereafter, the memory cells in the area 2 are refreshed. At the time of refreshing the area 2, since the address signal Ax is H, the bit lines of the area 1 and the area 2 are separated by the bit line dividing circuit 113 and connected to the sense amplifiers SA1 to SAn as compared with the case where the area 1 is refreshed. The length of the bit line is halved, resulting in halving the bit line capacitance. After all the word lines WL (k + 1) to WLm in the area 2 are selected, the address signal Ax changes from H to L, and the word line control signal WLCTL changes from H to L. Thereafter, the memory cells in the region 1 are successively refreshed (at this time, since the address signal Ax is L, the bit lines in the region 1 and the region 2 are respectively connected by the bit line dividing circuit 113). After selecting all of WL1 to WLk, the address signal Ax changes from L to H, and thereafter the memory cells in the area 2 are refreshed. However, since the word line control signal WLCTL is at L level, the word lines WL (k + 1) to WLm in the area 2 are always at L level due to the operation of the word line control circuit 127. Is not performed (at this time, since the clock signal Φ is valid, the address signals A0 to Ax are successively incremented). Then, the word lines WL (k + 1) to WL in the region 2
m, the address signal Ax changes from H to L, and the word line control signal WL
CTL changes from L to H. Thereafter, the memory cells in the region 1 are successively refreshed (at this time, since the address signal Ax is L, the bit line dividing circuit 113
Thus, the bit lines of the region 1 and the region 2 are connected to each other.) After selecting all of WL1 to WLk, the address signal Ax changes from L to H, and thereafter the memory cells in the area 2 are refreshed. Here, since the word line control signal WLCTL is H, the word line W
L (k + 1) to WLm can be selected and refresh is performed. When refreshing area 2,
Since the address signal Ax is H, the bit line dividing circuit 11
3, bit lines in the region 1 and the region 2 are separated. In this manner, while the control signal REF is at the H level, the refresh operation of the region 1 and the region 2 is repeated.

Next, a case where the head word line of the refresh belongs to the area 2 will be described with reference to the timing chart of FIG. 6 (a case where the initial state of the signal CTLF in FIG. 2 is L). Control signal RE
When F changes from L to H, Φ becomes a clock signal, and the internal address counter circuit 123 generates address signals A0 to Ax according to the clock signal Φ. Here, since the first word line of the refresh belongs to the area 2, the address signal Ax is H, and the bit lines of the area 1 and the area 2 are separated by the bit line dividing circuit 113, and the area 1 is refreshed. , The capacity of the bit line connected to the sense amplifiers SA1 to SAn is halved. The decoder circuit 124 decodes the address signals A0 to Ax and selects one word line WLj (j = k + 1 to m) from WL (k + 1) to WLm. One row of memory cells connected to the selected word line WLj are connected to the connected bit line (BL1 to BLn or / BL1 to / BLn).
The stored data is discharged as electric charges. The emitted charges are amplified by sense amplifiers SA1 to SAn, and the amplified charges are transferred to bit line pairs BL1, / BL1 to BLn,
/ BLn, and is again input to each memory cell as storage data. When the memory cells in one row are refreshed in this way, the decoder circuit 124 selects the next word line WL (j + 1), and the same operation is repeated thereafter. After all of WLj to WLm are selected in this way, the address signal Ax changes from H to L, and the word line control signal WLCTL changes from H to L. Thereafter, the memory cells in the region 1 are successively refreshed (at this time, since the address signal Ax is L, the bit lines in the region 1 and the region 2 are respectively connected by the bit line dividing circuit 113). Word lines WL1 to WLk in region 1
Are selected, the address signal Ax changes from L to H.
, And thereafter, the refresh of the memory cells in the area 2 is performed. However, here, the word line control signal WLCTL
Is set to L, the word lines WL (k + 1) to WLm in the area 2 are not selected by the operation of the word line control circuit 127. Therefore, word line WL
Refresh is not performed for the memory cells connected to (k + 1) to WLm (at this time,
Since the clock signal Φ is valid, the address signals A0 to A
x is incremented one after another). Word line WL
When the clock signals Φ are generated by the number of (k + 1) to WLm, the address signal Ax changes from H to L, and the word line control signal WLCTL changes from L to H. Thereafter, the memory cells in the region 1 are successively refreshed (at this time, since the address signal Ax is L, the bit lines in the region 1 and the region 2 are respectively connected by the bit line dividing circuit 113). After selecting all of WL1 to WLk, the address signal Ax changes from L to H,
Thereafter, the process proceeds to refresh the memory cells in the area 2. Here, since the word line control signal WLCTL is at H, the word lines WL (k + 1) to WLm can be selected, and the refresh is performed successively. At this time, since the address signal Ax is H, the bit lines in the region 1 and the region 2 are separated by the bit line dividing circuit 113. After all the word lines WL (k + 1) to WLm in the area 2 are selected, the address signal Ax changes from H to L, and the word line control signal WLCTL changes from H to L. Thereafter, the refresh of the memory cells in the area 1 is performed one after another. In this manner, while the control signal REF is at the H level, the refresh operation of the region 1 and the region 2 is repeated.

As described above, in the present invention, with respect to the word lines WL (k + 1) to WLm in the region 2, the capacity of the bit line connected at the time of the selection is halved, and the selection is performed every other time. Therefore, the number of refreshes performed in a certain period of time is smaller than that of the conventional circuit, and as a result, the charge / discharge current accompanying the refresh is reduced. 0.625 times). Here, in the refresh operation of the present invention, a case where the refresh cycle is T1 and a memory cell of the area 1 is selected, and a case where the refresh cycle is twice the T1 and a memory cell of the area 2 is selected when the refresh cycle is twice the T1. (Sense amplifier SA1
To half the capacitance of the bit line connected to SAn), the amount of potential change generated in the bit line is not necessarily the same.
The latter may be smaller than the former. Therefore, for example, when the refresh cycle T1 is the refresh limit cycle of the memory cell in the region 1 (the potential change amount generated on the bit line when the memory cell is selected depends on the sense amplifiers SA1 to SA1).
When the refresh period is set to the minimum amount that can be amplified by An), the amount of potential change generated in the bit line when selecting the memory cell in the region 2 becomes smaller than that of the memory cell in the region 1 and the sense amplifier SA1 to SA
In some cases, amplification by n cannot be performed (normal refresh is not performed). In such a case, normal refresh operation is ensured by adjusting the refresh cycle T1 according to the refresh limit cycle of the memory cells in the area 2.

Although the present invention has been described with respect to an example in which a memory cell region is divided into two regions, a region 1 and a region 2, the number of divisions is not limited to two, and may be three or more.

[0023]

As is clear from the above description, in the semiconductor memory device of the present invention, the number of selections of the memory cells arranged in the area 2 in the refresh by the internal clock is made half of that in the area 1. As a result, the number of refreshes performed on the entire chip within a certain time is reduced as compared with the conventional circuit, and power supply noise due to the refresh operation can be suppressed, thereby contributing to the stabilization of the circuit operation. At the same time, reduction in current consumption due to refresh can be realized.

[Brief description of the drawings]

FIG. 1 is a diagram showing an example of a semiconductor memory device of the present invention.

FIG. 2 is a diagram showing a configuration of an internal address counter circuit 123 of the present invention.

FIG. 3 is a timing chart showing the operation of the internal address counter circuit 123 of the present invention.

FIG. 4 is a diagram showing a configuration of a word line control circuit 127 of the present invention.

FIG. 5 is a timing chart showing a first operation of the semiconductor memory device of the present invention.

FIG. 6 is a timing chart showing a second operation of the semiconductor memory device of the present invention.

FIG. 7 illustrates an example of a conventional semiconductor memory device.

FIG. 8 is a diagram showing a configuration of a conventional internal address counter circuit 723.

FIG. 9 is a timing chart showing the operation of a conventional internal address counter circuit 723.

FIG. 10 is a timing chart showing an operation of a conventional semiconductor memory device.

FIG. 11 is a diagram showing configurations of a clock signal generation circuit 125 of the present invention and a conventional clock signal generation circuit 725.

[Explanation of symbols]

101 to 112, 701 to 708 ... Memory cells 114 to 117 ... N-channel transistors 118 to 121 ... P-channel transistors 122, 126, 401, 1101 ... Inverters 201, 402, 1102 ... Nand gates 113: bit line dividing circuit 123, 723: internal address counter circuit 124, 724: decoder circuit 125, 725: clock signal generating circuit 127: word line control circuit 202: FIG. 1103 ··· Inverter REF, WLCTL, CTLF ··· Control signal Φ ··· Clock signal A0 to Ax ··· Address signal WL1 to WLk and WL (k + 1) to WLm ..Word lines BL1, / BL1 to BLn, / BLn... Bit lines SA1~SAn ··· sense amplifier FF0~FF (x + 1) ··· flip-flop

Claims (1)

[Claims] A plurality of word lines, a plurality of bit line pairs,
A semiconductor memory device comprising a memory cell disposed and connected to each of the intersections of the word line and the bit line, and having a function of refreshing stored data at a predetermined cycle by selecting the memory cell; A bit line division circuit for cutting a bit line pair at a predetermined position; and a word line control circuit for restricting selection of the word line, wherein the bit line division circuit is provided in accordance with the arrangement position of a memory cell selected at the time of refresh. Is controlled, and the operation of the word line control circuit is controlled according to the number of times of execution of the refresh.