JPH11296310A - Buffer access device and cd-rom decoder, dvd decoder, cd-rom drive and dvd drive using the same device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a buffer access device of a disk reproducing device for managing a data area in a buffer RAM by a sector of a certain specified size, and having a data structure having fields suited to the sizes of plural data items in each sector. SOLUTION: This buffer access device manages a data area in a buffer RAM 6 by a sector of a certain specified size, and handles a data structure having fields suited to the sizes of plural data items in each sector. The data area is constituted of one kind of sector so that the address of the buffer RAM can be easily calculated from a sector number, sector length (fixed), field heading address (fixed) in the sector, and address in the field. The combination of the data items or the designation of a sub-address obtained by dividing unit data is operated in response to an instruction from a host CPU 8, and host transfer data can have various kinds of formats.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk reproducing apparatus having a CD-ROM decoder, a DVD decoder, and the like. The present invention relates to a system using a storage device such as a buffer RAM for the purpose of compensating for a difference in transfer speed between input / output devices.

[0002]

2. Description of the Related Art At present, in the field of audio equipment, an audio signal is converted to a P signal to perform high-density and high-fidelity recording / reproduction.
2. Description of the Related Art A digital recording / reproducing system that converts a signal into a digitized signal by a CM (Pulse Code Modulation) technique, records the signal on a recording medium such as a disk or a magnetic tape, and reproduces the signal is known. Such a disk playback device,
By moving the optical pickup device with a built-in semiconductor laser and photoelectric conversion device from the inner circumference to the outer circumference of the disk in linear tracking, and rotating the disk at a constant linear velocity (CLV). Reads data recorded on the disc. A CD is well known as a disk reproducing device, and a CD-ROM is one of the typical examples. The CD-ROM is a device that reproduces audio signals mixed in a disc and ROM data such as image information and character codes.

[0003]

Conventionally, as shown in FIG. 1, in a disk reproducing apparatus such as a CD-ROM drive or a DVD drive, a CD player (CD) is used.
P) and a buffer RAM for taking in data from an input device such as a DVD player and, after signal processing, outputting the data to an output device such as a host CPU in order to correct errors and compensate for differences in transfer speed between input / output devices. Are stored. FIG. 1 is a configuration diagram of a general CD-ROM drive used in the related art and the present invention. The conventional CD-ROM drive uses the conventional buffer address generation circuit shown in the circuit diagram of FIG. 12 and the sequence control diagram of FIG. The generation circuit generates an address from an area start address, a sector number, a sector length, and a byte address for each of a plurality of data types (hereinafter, referred to as items), and detects the end of a sector transfer by counting up the byte address. doing. When sending multiple data items, each setting must be made. FIG.
FIG. 8 shows a case of a 1 Mbit DRAM, and FIG. 8 shows a case of alternately sending a data signal Data (16 to 2063 bytes) and a flag Flag (0 to 293 bytes).

[0004] DVD-ROM data (information) includes a data signal (Data) and a flag signal (Flag). CD-ROM data includes a data signal (Data) and a flag signal (Flag). , A subcode signal (hereinafter, referred to as a sub (Sub)), a subcode Q signal (hereinafter, referred to as a sub Q (SubQ)), and the like.
These various types of data are composed of units having different sizes. In the buffer RAM for temporarily storing data, it is necessary to allocate a buffer sector corresponding to the data item. Hereinafter, a conventional example will be described with reference to a CD-ROM decoder. In a CD-ROM decoder,
The data input from the CD player is signal-processed and temporarily stored in the buffer RAM. At this time, the data and flags are
Recognition of each sector in the header synchronization signal cycle
The data is written to the buffer RAM through F (interface). The sub and sub-Q are recognized on a sector-by-sector basis at the sub-code synchronization signal period, and are written to the buffer RAM through the SUB-IF (interface).

[0005] Since these data have different unit sizes, the buffer RAM is divided into areas for each data item, and used by being divided into sectors corresponding to the respective sizes. FIG. 9 is a diagram showing a first allocation example of a conventional buffer RAM. To reduce the number of bits of an address designated by a microcomputer at the time of transfer, the head of each area is set to, for example, 25 bytes.
This is an example in which a block unit such as 6 bytes is used, and is used as an offset address in association with an area code. FIG. 9A shows the area of the buffer RAM.
(B) shows an offset address and an absolute address (1M
2 shows an example of allocation of bit DRAMs. When the host transfer item is only a data signal, the microcomputer specifies a data area code, a data sector address to be transferred,
The byte address in the sector to start the transfer and the byte address (or transfer length) to end the transfer are specified. The buffer address generation circuit calculates these offset addresses, obtains an absolute address at which transfer is started, and starts reading data (read) by a host transfer command of the microcomputer. The address is incremented while reading the data, and when the data is output to the host CPU for the specified transfer length, the reading of the buffer RAM is also completed. The microcomputer recognizes the end of the host transfer by a microcomputer interrupt or the like, and if necessary, specifies the next sector and performs the host transfer again.

When a data item (Data) and a flag item (Flag) are transferred to the host by a command from the host CPU, for example, the data signal and the flag signal must correspond to each other. Must be sent alternately. At this time, the microcomputer issues a host transfer instruction by designating an area code and a sector address of the data, and after the transfer of the data sector, performs a host transfer by designating the area code and the sector address of the flag. After the transfer of the flag sector is completed, the data sector is transferred again. Since this is repeated alternately, there is a problem that the program of the microcomputer becomes complicated, and the time required for the microcomputer processing is reduced, so that the efficiency of the host transfer is reduced. Buffer RA of different capacity
Considering the compatibility with M and applications to various types such as CD-ROM drives and DVD players, the number of sectors and data items are different, so the buffer allocation cannot be fixed. Further, since the difference between the absolute addresses of the sectors of a plurality of corresponding data items such as the data sector and the flag sector differs for each sector number and is not constant, a relative jump with a fixed length offset cannot be performed. Therefore,
In order to transfer a plurality of data items by a single transfer instruction, address jumps of absolute addresses different for each sector are required many times.

For example, FIG. 9 shows an example of the allocation of a 1-Mbit DRAM (m + 1 = 40). Here, data sector # 2
And flag sector # 2. When 2336 bytes of data are transferred from the address 16 in the data sector, the buffer address at the end of the transfer becomes data sector # 2.
(1B90H). To subsequently read the head (17450H) of the flag sector # 2, a jump is performed by the difference (158A0H), so that a wide address width is required. Similarly, considering the transfer of the data sector # 0 and the sub-Q sector # 0, this address jump needs to deal with the entire area of the buffer DRAM. If the above-described measures are taken in this conventional example, the circuit becomes large due to a jump of a wide address width, and the cost is increased. Also, because this address calculation takes time,
As a result, host transfer may be delayed. When transferring large-capacity data such as data sectors, the address of the next sector can be calculated during the transfer and the data can be transferred continuously. To do so requires very fast processing and is not practical.

Next, FIG. 10 is a diagram for explaining a second example of the allocation of the conventional buffer RAM, which aims at increasing the speed of the host transfer and simplifying the address generation at the time of the host transfer.
In this method, only data to be transferred to the host is stored at consecutive addresses in the buffer RAM in accordance with the transfer format of the instruction of the host CPU. As shown in FIG. 11, the CD-ROM data format is composed of subfields according to modes and forms. This includes not only actual data (UserData) but also auxiliary data such as a synchronization signal (Sync) and an identification address (Head) in data units, and parity (EDC, ECC) for error correction. What the host CPU needs is mainly a User Data subfield, which is written in a sector in the User Data area and the remaining auxiliary data is written in a sector in the AUX Data area. This allows the microcomputer to use User Data
Necessary data sectors can be continuously transferred to the host simply by designating the transfer start address and end address of the area.

However, as also shown in FIG.
User D depending on the mode and form of the CD-ROM
Since the start address and size of data are different, a system for extracting only User data at the time of buffer write becomes very complicated and large. Mode1 or m
After writing the buffer RAM from the CD player in the mode2 from1, the ECC
For example, when reading or writing UserData while referring to, the User Data sector and AUX D
The operation is further complicated because divided processing for separately accessing the ata sector is required.

At the time of transfer from the CD player to the buffer RAM, the number of sectors exceeding the transfer length of the command of the host CPU may be written. This is to prepare for the second and subsequent host transfer commands to be continuous data with the previous transfer data, and is used as a prefetch buffer.
However, when the mode or form of the CD-ROM data changes in the middle, or when the format of the transfer data is changed by a host CPU instruction, the buffer R is changed.
Since the data format on the AM differs from the format to be transferred, the conventional example of FIG. 10 has a problem that it cannot be used as a prefetch buffer. The present invention has been made in view of such circumstances, and manages the data area of the buffer RAM with sectors of a certain size, and has a data structure having a field in each sector having a size corresponding to a plurality of data items. Provided are a buffer access device of a disk reproducing apparatus provided with the same, and a CD-ROM decoder, a DVD decoder, a CD drive device, and a DVD drive device using the same.

[0011]

SUMMARY OF THE INVENTION The present invention provides an R
It is characterized in that the data area of the AM is managed in sectors of a certain fixed size, and a data structure in which each sector has a field corresponding to the size of a plurality of data items. Since the data area is composed of one type of sector, the address of the buffer RAM can be easily calculated from the sector number, the sector length (fixed), the start address of the field in the sector (fixed), and the address in the field.
According to an instruction from the host CPU, the combination of data items and the designation of the sub-address obtained by dividing the unit data are performed, and the host transfer data can have various formats. Further, according to the present invention, since a plurality of corresponding data are stored in the same sector, a combination of a plurality of fields can be transferred by designating a small address width. Access to subfields in each field can be easily performed by using an address pointer in the sector. Buffer R at this time
The access to the AM is performed based on the sector number, the sector length (fixed), the intra-sector transfer start address, and the intra-sector transfer end address. In addition, since each sector has the same data structure, once an address in a sector is designated once, a plurality of sector transfers of the same format can be realized only by changing the sector number.

The buffer address device of the present invention takes in a plurality of data having different formats and sizes from an input device, temporarily transfers the data to an output device asynchronously in a format different from that at the time of input after signal processing. In a system for storing data in a buffer RAM,
AM is managed in data units called sectors, and has a data structure including a plurality of data fields therein,
Writing from input device to buffer RAM and buffer R
When a buffer address generation circuit that reads data from the AM to the output device is provided, and a plurality of data items of different formats and sizes are fetched from the input device and are generally asynchronously transferred to the output device in a format different from the input time after signal processing. Is characterized by temporarily storing data in a buffer RAM. A CD-ROM and a DVD decoder according to the present invention include the buffer access device described above. The CD-ROM drive of the present invention
A CD player that reads and demodulates information data from a disk storing the data, a CD-ROM decoder that decodes the demodulated data, a buffer RAM that stores the demodulated data, and the buffer access device. It is characterized by having. Further, the DVD drive of the present invention comprises a CD player for reading and demodulating information data from a disk storing the data, and a DVD for decoding the demodulated data.
It is characterized by comprising a decoder, a buffer RAM for storing the demodulated data, and the buffer access device.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a system block diagram of a disc reproducing apparatus, for example, a CD-ROM drive. The CD-ROM drive includes a disk 1 on which data is recorded, a motor 2 for rotating the disk 1,
It has a mechanical part consisting of a pickup 3 for reading the data, and further has a CD player (CDP) 4,
The host CP includes a CD-ROM decoder 5, a buffer RAM 6, and a microcomputer (system controller) 7.
Connected to U8.

Next, a CD player and data output from the CD player will be described. Laser light is emitted from the pickup 3 onto the disk 1, and the reflected light is received to read data recorded on the disk 1. The read data is supplied to an RF circuit, where a waveform-equivalent RF signal is generated. R
The F signal is binarized into digital data and becomes an EFM signal. The EFM signal is input to a PLL circuit, from which a synchronous clock signal is extracted. Further, a data signal is generated in the PLL circuit. The data signal and the clock signal are sent to a correction circuit through a synchronization separation circuit in a signal processing circuit in the CD player 4, and error correction processing is performed using a correction memory (RAM). The data corrected here is, for example,
Read by the crystal system reference clock. The correction circuit outputs a data signal and a synchronous clock signal.

The data is audio data and CD-RO data.
There is M data, and in the CD-ROM mode, the data signal is not processed by the DAC and the LPF, is sent to the CD-ROM decoder 5, and is output as a digital output. CD
The signal corrected by the correction circuit in the player 4 is sent from the signal processing circuit of the CD player 4 to the CD-ROM decoder 5, where the data is transferred to the host CPU 8 after correcting and buffering the CD-ROM. You. In the audio mode, the processing is performed by the CD player 4 so that the 1x speed CLV
, And in normal CD-ROM mode, nx speed CLV
It will be played back. On the other hand, the servo system signal read from the pickup 3 is sent to the servo circuit through the RF circuit, and is subjected to equalizing processing, and then drives the actuator of the pickup 3 and the pickup feed motor. In the signal processing circuit of the CD player 4, the disc 1
Is generated, and this signal drives the motor 2. The microcomputer (system controller) 7 controls a servo circuit that controls various CD servo systems through the microcomputer.

The data output from the CD player 4 is
The data is written into both the buffer RAM 6 for storing the transfer data and the correction memory (not shown) for storing data for performing error correction. An error correction process is performed on one block (2352 bytes of data called one sector in a CD-ROM) for error correction stored in the correction memory. After the error correction processing, all data in the sector or necessary partial data is read from the memory as needed. Data input to the correction memory is subjected to error correction by an error correction circuit (ECC) based on a syndrome operation. The error-corrected data is written to the correction memory and the buffer RAM 6 and then output from the buffer RAM 6 to the host CPU 8. Writing to the correction memory and error correction are performed under the control of the microcomputer 7.

As described above, in the CD-ROM drive shown in FIG.
The CD player 4 is started, and the transfer from the CD player 4 to the buffer RAM 6 is started. The CD-ROM data includes a data signal Date, a flag signal Flag, and a sub (Su
b) and sub-Q (SubQ), which are CD-I
Buffer RAM 6 via F10 or SUB-IF11
However, for the data signal Date, reading and writing of the buffer RAM 6 are repeated to perform error correction as necessary. When the necessary data is obtained, the microcomputer 7 starts host transfer by designating a buffer address, and the data is transferred to the host CPU 8 through the host IF 13.
Is output to The buffer RAM 6 is accessed by using an address obtained by calculating an offset address specified by the microcomputer by the buffer address generation circuit 91 and receiving an access request for each block such as a CD-IF.
Done by

This CD-ROM drive uses the buffer address generation circuit shown in the circuit diagram of FIG. 2 and the sequence control diagram of FIG. The buffer address generation circuit 91 of the buffer access device 9 provided in the CD-ROM decoder 5 generates an address from an area head address, a sector number, a sector length and a byte address for each of a plurality of data items, and converts the byte address. By counting up, the end of the sector transfer is detected. When sending multiple data items, each setting must be made. FIG. 2 shows a case of a 1 Mbit DRAM, and FIG. 3 shows a data signal Data (16 to 2063 bytes).
And the flag Flag (2352 to 2645 bytes) are sent alternately. In the present invention, since the data sector has a field for each data item, it is not necessary to load the area start address and the sector length with fixed values each time. After the transfer of one item is completed, the transfer address of the next item is generated by detecting the end of the field, and the transfer can be continuously performed.

FIG. 4 is a diagram showing an example of buffer allocation according to the present invention. In this embodiment, in the data area of the buffer RAM, in the case of a DVD drive, the data Data and flag Flag, and in the case of a CD-ROM drive, the data Data and flag Flag, sub (Sub), sub Q
For example, a data sector having a plurality of fields for storing a plurality of items, such as (SubQ), is provided. When fetching data from an input device such as a CD player, a corresponding data item is written in a field in the same sector. This is because, in a CD-ROM drive, the data Da
It is assumed that the header synchronization signal for inputting the ta and the flag Flag and the subcode synchronization signal for inputting the sub and the sub-Q input data while maintaining a certain fixed phase. This allows the corresponding data items to be written on successive addresses in the buffer RAM. The data sectors are all the same size, and the addresses in the sectors can be shown in 0 to 4 KB.
Even if the sector address is different, the same data item can be accessed if the address is within the same sector.

For example, data D in data sector # 2
Data and flag are to be transferred to the host CPU. Byte address 16 to 2 in the data field
When the transfer in 336 is performed, the buffer address at the end of the transfer points to the tail (1F30H) in the data field. After this, the head of the flag field (1F40
H) can be read by jumping by the difference (10H). Since the corresponding jump for transferring the data item is smaller than the size of the data sector, it can be handled by an address jump within 4 KB (12 bits or less). For example, CD-ROM data 4
In order to correspond to various data items (fields), four sets of byte address pointers in the sector for host transfer are prepared, and the transfer start and end byte addresses of each field (or the transfer start and end of each field). Address transfer length). Then, the transfer length specifies the total of the transfer lengths of the respective fields.

When the microcomputer designates a sector address, a pointer to a maximum of four sets of byte addresses, and a total transfer length within a sector, the buffer address generation circuit first calculates the first set of transfer start byte addresses to obtain an absolute address. Transfer starts with a transfer start command. The first set of transfer end byte addresses is transferred, and if the transferred data length is shorter than the specified transfer length and the transfer of the second set of data fields is valid, the transfer is continued from the second set of transfer start byte addresses. Perform host transfer. Similarly, the third and fourth data fields are transferred. In this manner, host transfer of a plurality of corresponding data items can be realized by one transfer command. When transferring the same data item by the same size over multiple sectors, it is only necessary to change the sector address and issue the host transfer instruction again without changing the byte address in the sector, reducing the processing time and operation of the microcomputer. As a result, the efficiency of host transfer is improved.

Next, referring to FIGS. 5 and 6, the data signal and the flag signal (Data + Fla) will be compared with the conventional example.
The microcomputer operation at the time of the host transfer in g) will be described. FIG.
FIG. 7 is a flowchart showing a conventional microcomputer setting operation when allocating a buffer when performing host transfer of two items of a data signal Data and a flag signal Flag. In the conventional example shown in FIG. 5, the microcomputer 7 must specify an address for each of the Data sector and the Flag sector, issue a transfer instruction, and wait for the end of the transfer to perform the next transfer. However, in the present invention shown in FIG.
Since the field and the Flag field can be sent together, it is only necessary to wait for the end of one transfer. Also, when transferring fields of the same address in consecutive sectors,
It can be realized only by changing the sector address by one address specification. When the automatic increment is performed at the end of one sector transfer, it is not necessary to specify a sector address.
The transfer length designation (DSL) (* 1) in FIG. 5 designates a transfer length or a transfer end address, and designates a sector (FS
A) (* 2) can be omitted when transferring the same sector. The designation (Data) (* 1) of the area in FIG.
When there is an area in addition to the Data area, and when transfer of all sectors cannot be completed (No) (* 2),
If the sector address does not automatically increment after the transfer of one sector, a transfer start command is issued after designating the next sector.

Next, referring to FIG. 7, the data signal and the flag signal (Da
The relationship between the host transfer time (ta + Flag) and the overhead will be described. FIG. 7 shows the host transfer time required for conventional single item transfer (FIG. 7 (a)) and the host transfer time required for multiple item transfer of the present invention (FIG. 7 (b)). Are arranged in chronological order, and represent the difference in the transfer preparation period of the microcomputer. In the present invention, when there is no overhead and a plurality of items are continuously transferred in a plurality of sectors, the time difference between the present invention and the conventional example becomes large. In the data transfer of the present invention (* 1), if the sector address does not automatically increment after the transfer of one sector, the next sector is designated and a transfer start command is issued.

[0024]

Since a plurality of data items can be transferred at one time, the transfer operation of the microcomputer is reduced and the transfer processing time is reduced. This reduces the waiting time of the host CPU,
The occupancy of the host CPU also decreases. Further, since other processing such as ECC is performed during the idle time of the transfer processing of the microcomputer, the transfer time to the host is also reduced. Even if the number of sectors changes due to the sector allocation of the buffer RAM, there is no change in address processing, so that it is possible to handle from a small capacity to a large capacity DRAM. Also, assuming that a header synchronization signal for inputting data and a flag and a subcode synchronization signal for inputting sub and sub-Q are synchronized, all field data in the same sector correspond to each other. From that
When transferring data in the same sector, the data header address (absolute address of the data system) and the sub-Q ATI
There is no need to compare with the ME address (absolute address of the subcode system), and the processing by the microcomputer can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of the present invention and a conventional CD-ROM drive.

FIG. 2 is a block circuit diagram of a CD-ROM drive of the present invention.

FIG. 3 is a sequence control diagram of the CD-ROM drive of the present invention.

FIG. 4 is a diagram showing buffer allocation of the CD-ROM drive of the present invention.

FIG. 5 shows a conventional data signal Data and a flag signal Fla.
FIG. 8 is a flowchart showing a microcomputer setting operation at the time of buffer allocation when performing host transfer of two items g.

FIG. 6 shows a data signal Data and a flag signal Fl according to the present invention.
FIG. 11 is a flowchart showing a microcomputer setting operation at the time of buffer allocation when performing host transfer of two items ag.

FIG. 7 is an operation diagram of a microcomputer showing a host transfer time required for conventional single item transfer and a host transfer time required for multiple item transfer of the present invention.

FIG. 8 is a sequence control diagram of a conventional CD-ROM drive.

FIG. 9 is a diagram showing buffer allocation of a conventional CD-ROM drive.

FIG. 10 is a diagram showing buffer allocation of a conventional CD-ROM drive.

FIG. 11 is a format diagram of CD-ROM data.

FIG. 12 is a block circuit diagram of a conventional CD-ROM drive.

[Explanation of symbols]

1 ... disk, 2 ... motor, 3 ...
Pickup, 4 ... CD player, 5 ... C
D-ROM decoder, 6 ... buffer RAM, 7
... microcomputer, 8 ... host CPU, 9 ...
Buffer access device, 10 ... CD-IF, 1
1 ... SUB-IF, 12 ... ECC circuit, 1
3: Host IF, 91: Buffer address generation circuit, 92: Buffer RAMIF

Claims (5)

[Claims] When a plurality of data having different formats and sizes are fetched from an input device and are asynchronously transferred to an output device in a format different from the input format after signal processing, the data is temporarily stored in a buffer RAM. In the storage system, the buffer RAM is managed in data units called sectors, and has a data structure including a plurality of data fields therein, and writes from the input device to the buffer RAM and reads from the buffer RAM to the output device. A buffer address generation circuit that performs data processing, and buffers multiple data of different formats and sizes from the input device and temporarily buffers the data when it is asynchronously transferred to the output device in a format different from the input format after signal processing. A buffer access device stored in a RAM. 2. A CD-ROM decoder comprising the buffer access device according to claim 1. 3. A DVD decoder comprising the buffer access device according to claim 1. 4. A CD player that reads and demodulates information data from a disk storing the data, a CD-ROM decoder that decodes the demodulated data, a buffer RAM that stores the demodulated data, A CD-ROM drive comprising the buffer access device according to claim 1. 5. A CD player for reading and demodulating information data from a disk storing the data, a DVD decoder for decoding the demodulated data, and a buffer RAM for storing the demodulated data. A DVD drive, comprising: the buffer access device according to (1).