JPH11288431A - Substrate designing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a substrate designing system by a timing verifying/graphical displaying function. SOLUTION: Each reference signal/electronic part inside connection/timing information to be defined is designated by an inputting part 1, and the arrangement and wiring of electronic parts of prepared circuit diagram data is separately operated by a substrate arrangement and wiring designing part 2. Then, substrate connection data are extracted from substrate layout design data stored in a substrate layout design data storing part 3 by a substrate connection data extracting part 4, and stored in a substrate connection data storing part 5. The stored substrate connection data and each reference signal/electronic part inside connection/timing information stored in a reference signal information storing part 6 and an electronic part timing information storing part 7 from the inputting part 1 are inputted to a timing analyzing part 8 so that inter- electronic part timing having a timing constraint condition can be analyzed, and the analyzed result is stored in an analyzed result storing part 9, and displayed at an analyzed result displaying part 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention can easily define information such as a reference signal cycle and a skew between reference signals in a function / logic / layout design of a board such as a printed wiring board, and a circuit operation timing in consideration of a wiring delay time on the board. The present invention relates to a board design device having a verification function and a graphical display function.

[0002]

2. Description of the Related Art As shown in FIG. 27, for example, a conventional board design apparatus disclosed in Japanese Patent Application Laid-Open No. HEI 5-89198 requires reference signal information of a printed wiring board mounted circuit manually created while viewing an electronic component catalog or a circuit diagram. And a design method (a board design method using reference signal information by hand). First, the logic circuit input section inputs a logic circuit for executing a logic simulation, and the discrimination section inputs information that causes a signal transmission delay.
Determine whether there is a delay information file that stores (wiring capacitance value, wiring resistance value, etc. after the logic circuit layout), and if there is, calculate the actual wiring delay value based on the delay information file in the wiring delay calculation unit ( The above procedures S1 to S3). Next, the automatic node generation unit automatically creates a node information table having delay values for different wirings based on the calculation result, and the element delay calculation unit calculates the delay of the element to be subjected to the logic simulation to obtain individual delay values. (The above procedures S4 and S5). Further, the logic simulation execution unit verifies the logic circuit based on the node information table and the delay value (step S6).

[0003]

The above-described conventional board design apparatus employs a board design method using manual reference signal information. Therefore, the definition of a reference signal such as an operation clock of a board-mounted circuit, especially the It takes time to calculate the skew information manually. Electrical characteristics (reflection of signals transmitted on printed wiring boards, crosstalk, etc.)
The required timing cannot be verified using the wiring delay data in consideration of the above. There is also a problem that the difference between the wiring delay time due to the resistance (R) / capacitance (C) replacement and the actual wiring delay time on the substrate is large.

Further, the conventional board design apparatus employs a method of performing timing verification to confirm circuit operation using the wiring delay estimated by RC (a board design method using a timing verification function for circuit operation verification). Therefore, since the board design method that uses the timing verification function to check the circuit operation is adopted, the timing verification result is not reflected in the layout design, and it takes time to return to the design when a timing error occurs, resulting in a problem. Was.

The problem to be solved by the present invention is to simplify the method of verifying the circuit operation timing in consideration of the wiring delay time on the substrate and the definition of the reference signal information so as to solve the above-mentioned problems in the substrate design apparatus. It is an object of the present invention to provide a method of performing a graphical display (a board design method using a timing verification / graphical display function).

Another problem to be solved by the present invention is a method of performing a layout design based on a wiring allowable delay for each wiring calculated by timing verification (a wiring allowable delay calculation / comparison function in timing verification). To provide a circuit board design method).

[0007]

According to the present invention, there is provided a board designing apparatus provided with the following means for solving the above-mentioned problems, and adopting a board designing method using a timing verification / graphical display function.

The input section defines and specifies the reference signal information, the electronic component internal connection information, and the timing information.

The board layout / wiring section / board layout design data storage section performs layout and wiring of electronic components on circuit diagram data which is separately created, and generates and stores board layout design data.

The board connection data extraction / storage unit extracts and stores board connection data from the stored board layout design data stored in the board layout design data storage unit.

The reference signal information / electronic component timing information storage unit stores designated reference signal information / electronic component internal connection information and timing information by the input unit.

[0012] The timing analysis unit sets a timing constraint condition on the storage reference signal information / electronic component internal connection information and timing information by the reference signal information / electronic component timing information storage unit and the storage board connection data by the board connection data storage unit. Analyze the timing between electronic components.

The analysis result storage / display unit stores and displays the analysis result by the timing analysis unit.

The net name search section is provided separately. The input unit searches the storage board connection data of the board connection data storage unit for the net name of the designated reference signal information, and generates connection information corresponding to the net name or the like as temporary reference signal information.

The provisional reference signal information storage / display unit is provided separately. For the generated temporary reference signal information by the net name search unit,
The information is stored, and the connection information corresponding to the net name or the like is graphically displayed.

The reference signal information defining section is provided separately. Display temporary reference signal information displayed by the temporary reference signal information display unit, use the specified reference signal information by the input unit, add the period and skew information, formally certify, and specify the reference signal information by the input unit as the reference signal information Is output to the reference signal information storage unit.

The reference signal path search section is provided instead of the net name search section. With respect to the stored electronic component internal connection information and the timing information stored in the electronic component timing information storage unit and the stored board connection data stored in the board connection data storage unit, a path corresponding to the reference signal is searched and generated. The parts and connection information are output to the temporary reference signal information storage unit as temporary reference signal information.

The property information search section is provided instead of the net name search section. The storage board connection data stored in the board connection data storage unit is searched for a net name of a signal to which a reference signal designation property is added. Output to the information storage unit.

The data discriminating unit is provided separately. For each generated temporary reference signal information by the net name search unit, the reference signal path search unit, and the property information search unit, the search method is determined, and the net name and the reference signal specified by the timing verification implementer are determined. The electronic component and connection information corresponding to the path or the like to be searched and generated for any combination or all of the path and the net name of the signal to which the reference signal designation property is added as the provisional reference signal information, and each net search unit Is output to the temporary reference signal information storage unit in place of the temporary reference signal information generated by.

The virtual wiring delay data calculator is provided separately. Based on the storage board layout design data stored in the board layout design data storage unit and the designated timing information specified by the input unit, virtual delay data is calculated from the estimated wiring length between connection pins.

The wiring delay data storage section is provided separately. The virtual wiring delay data calculated by the virtual wiring delay data calculation unit is stored and output to the timing analysis unit.

The waveform analyzer is provided in place of the virtual wiring delay data calculator. The waveform analysis preparation data stored in the separately provided waveform analysis preparation data storage unit is read, a waveform analysis simulation is performed, and the calculated wiring delay data for each wiring is output to the wiring delay data storage unit.

A board designing apparatus according to another aspect of the present invention is provided with the following means in order to solve the above-mentioned problems, and adopts a board designing method using a wiring allowable delay calculation / comparison function in timing verification.

The input section defines and designates the reference signal information, the electronic component internal connection information, the timing information, the board design information, and the waveform analysis preparation data.

The circuit diagram data storage section stores circuit diagram data for which a circuit has been designed.

The reference signal information storage unit / electronic component timing information storage unit stores designated reference signal information / electronic component internal connection information and timing information by the input unit.

The timing analysis unit / timing analysis result storage unit stores reference signal information / electronic component timing information storage unit stored reference signal information / electronic component internal connection information and timing information, and circuit diagram data storage unit stored circuit diagram data. On the other hand, the timing between electronic components having the timing constraint condition is analyzed, and the analysis result is stored.

The wiring allowable delay calculation unit / storage unit calculates a delay time allowable as a wiring delay for each wiring from a timing margin (a margin for timing constraint conditions) with respect to the storage analysis result by the timing analysis result storage unit.
Store.

The board design information storage unit stores the board specifications (layer configuration, conductor width / gap value, etc.) defined by the input unit and the electrical characteristic values of the board (characteristic impedance, delay time per unit line length). , Relative permittivity, etc.).

The board placement / wiring design unit stores the circuit diagram data, the wiring allowable delay, and the board design information by the circuit diagram data storage unit, the wiring allowable delay storage unit, and the board design information storage unit.
Implement the layout of electronic components and signal wiring.

The virtual wiring delay calculation unit / wiring delay storage unit
The Manhattan length is calculated from the XY coordinates of the components of the board placement and wiring information with respect to the board placement and wiring information by the board placement and wiring design unit and the board design information by the board design information storage unit, and the delay per unit line length of storage of the board design information The virtual wiring delay is calculated by multiplying by the time and stored.

The wiring delay comparing section checks whether the wiring delay information satisfies the wiring allowable delay with respect to the storage wiring allowable delay stored in the wiring allowable delay storage section and the storage wiring delay information stored in the wiring delay storing section. Compare the delay information with the allowable wiring delay.

The wiring delay comparison result storage / display unit stores and displays the result of the wiring delay comparison by the wiring delay comparing unit.

The reference value storage section is provided separately. Stores a reference value defined using the input unit, which is used as a reference for checking whether the wiring allowable delay by the wiring allowable delay storage unit is actually in a range where the electronic components can be arranged and the wiring between the electronic components is possible. .

The wiring allowable delay check section is provided separately.
The allowable wiring delay by the allowable wiring delay storage unit is compared with the reference value by the reference value storage unit.

The circuit diagram data discriminating unit is provided separately.
Parts that are not related to timing (for example, resistors and capacitors) for the circuit diagram data stored in the circuit diagram data storage unit
Is deleted from the circuit diagram data. The determination as to whether the component is irrelevant to the timing is made by reading additional information attached to the electronic component information of the circuit diagram data in advance.

The electronic component information discrimination processing section is provided instead of the circuit diagram data discrimination processing section. From the circuit diagram data stored in the circuit diagram data storage unit, information on components (for example, resistors and capacitors) that are not related to timing is deleted from the circuit diagram data. The determination as to whether or not the component is irrelevant to the timing is made from the electronic component internal connection information / timing information in the electronic component timing information storage unit and the net name given to each wiring of the circuit diagram data in the circuit diagram data storage unit. .

The delay data converter is provided separately. For the allowable wiring delay and the delay time per unit line length by the board placement and wiring design unit, the allowable wiring delay between the component selected for placement study and the component connected to the component is expressed as the delay time per unit line length. Divide and convert to line length data.

The line length data storage section is provided separately. The line length data by the delay data conversion unit is stored.

The component allocable area indicating section is provided separately. In response to the line length data stored in the line length data storage unit, an area where components to be arranged can be arranged is designated to the board arrangement and wiring design unit based on the line length data.

The general wiring delay calculator is provided in place of the virtual wiring delay calculator. The line delay data and the delay time per unit line length are multiplied by the line length data and the delay time per unit line length by the board placement and wiring design unit, and the calculated wiring delay is calculated by the wiring delay storage unit. Output to

The waveform analysis preparation data storage section is provided separately. Checks the information required for waveform analysis defined using the input section (for example, VI characteristics of output pins of components, rise / fall time of output signal, etc.) and whether waveform analysis considering crosstalk is necessary (Parallel wiring number / wiring interval / parallel wiring length) to be stored.

The waveform analyzer is provided in place of the virtual wiring delay calculator. Read the waveform analysis preparation data stored by the separately provided waveform analysis preparation data storage unit and the wiring information (wiring layer, wiring length, board specification, etc.) of the wired signal by the board layout and wiring design unit (or automatic wiring design unit) and read the waveform. An analysis simulation is performed, and the calculated wiring delay data for each wiring is output to the wiring delay storage unit.

The automatic wiring design unit is provided separately. Wiring design is automatically performed on the line length data stored in the line length data storage unit so as to satisfy the line length data.

The parallel wiring number check section is provided separately. For the wiring information (including the number of adjacent wiring and gap value other than the above wiring information) of the signal wired by the board layout wiring design unit, the waveform defined in the waveform analysis preparation data storage unit using the input unit in advance Compare with the number of parallel wirings that need to be analyzed, and check whether the wiring needs waveform analysis taking into account crosstalk.

The waveform analysis result storage section is provided separately. The waveform information of the result of the waveform analysis in consideration of the crosstalk by the waveform analysis unit is stored.

The timing analysis result display section is provided separately. The timing analysis is performed again using the waveform information from the waveform analysis result storage unit, and the stored timing analysis result is displayed.

The highlight display instruction section is provided instead of the wiring delay comparison result storage section. Based on the wiring delay comparison result stored in the wiring delay comparison result storage unit, the board placement and wiring design unit highlights and instructs the signal that caused the timing error.

[0049]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 A board design apparatus according to an embodiment of the present invention has an input unit 1 as shown in FIG.
Is the reference signal information (information such as the operation clock cycle and skew of the circuit), the internal connection information of electronic components, and the timing information.
(Definition information of timing constraint conditions such as internal delay time and setup / hold time) and specify using keyboard / mouse etc. The board layout and wiring design unit 2 performs layout of electronic components and wiring between the electronic components with respect to circuit diagram data to be separately created, and generates board layout design data.
(For example, a circuit diagram shown in FIG. 2). The board layout design data storage unit 3 stores the board layout design data generated by the board layout and wiring design unit 2. The board connection data extraction / storage section 4/5 stores the board connection data (for example, net names and electronic components necessary for timing verification) shown in FIG. Data such as location number / pin number / model name) is extracted and stored.
The reference signal information storage section 6 stores reference signal information specified by the input section 1. The electronic component timing information storage unit 7
The electronic component internal connection information and timing information designated by the input unit 1 are stored. The timing analysis unit 8 compares the stored board connection data from the board connection data storage unit 5, the stored reference signal information from the reference signal information storage unit 6, and the stored electronic component internal connection information and timing information from the electronic component timing information storage unit 7. Analyze the timing between electronic components with timing constraints. Analysis result storage / display section 9/10
Stores and displays, for example, the analysis result shown in FIG. 3B by the timing analysis unit 8. The circuit operation timing can be verified in consideration of the wiring delay time on the substrate. The board connection data extraction unit 4 generally includes a drawing input logic CAD (computer-aid) in addition to the board layout design data.
The board connection data may be extracted from the circuit diagram data created by the circuit designer using an ed design) application. The analysis result display unit 10 is, for example, as shown in FIG.
As shown in the figure below, the information on which path in the circuit caused the timing error and how much margin (timing margin) exists in each path, etc. , The deficiency (meaning a timing error) and the margin for the defined timing constraint are indicated by minus and plus values, respectively.

Embodiment 2 In the embodiment of the invention shown in FIG. 1, as shown in FIG. 4, for example, "CLK" is designated by the input unit 1 for the storage board connection data shown in FIG. Search for a net name that includes the “CLK” character specified by the timing verification practitioner of the reference signal information to be connected. The connection information corresponding to the net name and the location number and pin number of the electronic component connected to the net name is searched. Generated as provisional reference signal information. A net name search unit 11 and a temporary reference signal information storage / storage unit that stores the temporary reference signal information generated by the net name search unit 11 and graphically displays connection information corresponding to the net name and the like as shown in FIG. Display unit 12/13
With the provisional reference signal information displayed by the provisional reference signal information display unit 13, information such as the cycle and skew is added using the designated reference signal information by the input unit 1 to formally certify, and the input unit 1 May be provided separately from the reference signal information defining unit 14 that outputs the reference signal information to the reference signal information storage unit 6 instead of the designated reference signal information. By searching for a net name specified by the timing verification implementer and displaying a graphical display of electronic components and connection information corresponding to the searched net name, the cycle and skew can be easily set for the reference signal. The designation of the reference signal search may be freely determined by the timing verification implementer, and need not always be designated as “CLK”. Instead of the graphical display example shown in FIG. 5, a highlight display of the reference signal wiring may be displayed on a circuit design / board layout design CAD used by a circuit designer / board layout designer.

Embodiment 3 FIG. Further, in the embodiment of the invention shown in FIG. 4, instead of the net name search unit 11, as shown in FIG. 6, the storage board connection data by the board connection data storage unit 5 and the storage electronic component inside the electronic component timing information storage unit 7 are stored. For connection information and timing information, setup /
An electronic device corresponding to the net name, etc., which searches for and generates a path that can be the reference signal until a reference signal such as a clock is input to a designated pin at a timing between electronic components having timing constraint conditions such as a hold time, is generated. A reference signal path search unit 15 that outputs parts and connection information to the provisional reference signal information storage unit 12 as provisional reference signal information may be provided. By automatically inspecting a path that can be a reference signal and displaying a graphical display of electronic components and connection information corresponding to the searched net name and the like, the cycle and skew of the reference signal can be easily set.

Embodiment 4 FIG. Further, in the embodiment of the invention shown in FIG. 4, instead of the net name search unit 11, the reference signal designation property on the board layout design CAD is stored on the board connection data stored in the board connection data storage unit 5 as shown in FIG. Property information for outputting electronic components and connection information corresponding to the net name and the like to be searched and generated to the temporary reference signal information storage unit 12 as temporary reference signal information, by searching for and generating the net name of the signal to which the connection order and the operating frequency are added. A search unit 16 may be provided. By searching the board connection data for the net name of the signal to which the reference signal designation property has been added, and graphically displaying the electronic components and connection information corresponding to the searched net name, the cycle and skew of the reference signal can be determined. Easy to set up. For example, as shown in FIG. 9, the reference signal designation property is defined as board layout design data such as a part enclosed in parentheses () after a net name in the board connection data of the board circuit diagram shown in FIG.

Embodiment 5 In the embodiment of the invention shown in FIG. 4, as shown in FIG. 10, the reference signal path search unit 15 and the property information search unit shown in FIGS. 6 and 7, which are provided separately from the net name search unit 11 shown in FIG. 16 for each generated temporary reference signal information,
Searches for any combination or all of the net name specified by the user, the path that can be the reference signal and the net name of the signal with the reference signal specification property added, and generates the electronic components and connection information corresponding to the path etc. As the temporary reference signal information, a data determination processing unit 17 that outputs the temporary reference signal information generated by the net name search unit 11 to the temporary reference signal information storage unit 12 may be separately provided. Searches for any combination or all of the net name specified by the user, the path that can be the reference signal, and the net name of the signal to which the reference signal specification property is added, and searches for electronic components or the like corresponding to the searched net name, etc. By displaying the connection information graphically, the period and skew can be easily set for the reference signal.

Embodiment 6 FIG. Also, in the embodiment of the invention shown in FIG. 10, as shown in FIG. 11, the virtual wiring delay data calculating section 18 stores the stored board layout design data by the board layout design data storage section 3 and the designated timing information by the input section 1. Virtual wiring delay data is calculated from the wiring length between the connection pins to be estimated, and the wiring delay data storage unit 1 is calculated.
The virtual wiring delay data stored in step 9 may be output to the timing analysis unit. Using virtual wiring delay data that is calculated by estimating the wiring length between electronic components, it is possible to verify the circuit operation timing close to the actual operation state. First, the virtual wiring delay data calculating unit 18 calculates the connection between the connection pins 4 and 11 of the electronic components IC1 and IC2 shown in FIG. 12 based on the layout information of the electronic components mounted on the substrate stored in the board layout design data storage unit 3. Is calculated by adding the X- and Y-axis direction wirings Aa and Ab estimated from the connection pin XY coordinates to the shortest distance wiring A connecting. Next, the virtual wiring is multiplied by the delay time per unit line length specified by the input unit 1 to obtain virtual wiring delay data.

Embodiment 7 FIG. In addition, in the embodiment of the invention shown in FIG. 11, instead of the virtual wiring delay data calculation unit 18, the waveform analysis preparation data storage unit 20 separately provided as shown in FIG. A wiring delay data and wiring delay data storage unit 19 for each wiring which is read by reading wiring characteristics data in consideration of electrical characteristics (reflection, crosstalk, etc.) and performs a waveform analysis simulation to calculate. May be provided. The circuit operation timing close to the actual operation state can be verified by using the wiring delay data for each wiring calculated in consideration of the electrical characteristics of the substrate in the waveform analysis simulation.

The board designing apparatus according to the embodiment shown in FIGS. 1, 11 and 13, and FIGS. 4, 6, 7 and 10,
A method of verifying the circuit operation timing in consideration of the wiring delay time on the substrate and a method of performing a graphical display so as to facilitate the definition of the reference signal information (a board design method using a timing verification / graphical display function) are employed.

Embodiment 8 FIG. As shown in FIG. 14, in a board design apparatus according to another embodiment of the present invention, an input unit 1 includes reference signal information (information such as a circuit operation clock cycle and skew) and electronic component internal connection information. And timing information (definition information of timing constraints such as internal delay time and setup / hold time) and board design information
(Information such as layer configuration, conductor width, gap value, characteristic impedance, delay time per unit line length and relative permittivity as board specifications) and reference value (wiring allowable delay is Set value to check if the wiring between them is within the allowable range) and waveform analysis preparation data (VI characteristics of output pins of components, rise / fall time of output signal, and parallel wiring requiring crosstalk analysis) Information such as numbers), and specify with keyboard / mouse etc. The circuit diagram data storage unit 51 stores separately created circuit diagram data. The reference signal information storage section 6 stores reference signal information specified by the input section 1. The electronic component timing information storage unit 7 stores the electronic component internal connection information designated by the input unit 1 and the timing information. Timing analysis unit 8
The circuit diagram data storage 51 shown in FIG.
The storage circuit diagram data shown in (a), the stored reference signal information stored in the reference signal information storage unit 6, and the stored electronic component internal connection information and the timing information stored in the electronic component timing information storage unit 7 between the electronic components having a timing constraint condition Analyze the timing of The timing analysis result storage unit 9 stores an analysis result by the timing analysis unit 8. The wiring allowable delay calculation / storage unit 52/53 obtains, for example, the storage timing analysis result of FIG.
The allowable delay time for each wiring shown in FIG. The board design information storage unit 54 stores the board specifications (layer configuration, conductor width and gap value, etc.) and the board's electrical characteristic values (characteristic impedance, delay time per unit line length, relative dielectric constant) by the input unit 1. Etc.) is stored.

The board layout and wiring design unit 55 stores the circuit diagram data stored in the circuit diagram data storage unit and the wiring allowable delay storage unit 5.
3 and the wiring between the electronic components is performed based on the wiring allowable delay caused by the step 3 and the substrate design information stored in the substrate design information storage unit 54. The virtual wiring delay calculation unit 56 calculates a Manhattan length as a virtual wiring from the XY coordinate information of each connection pin of the electronic component by the board placement and wiring design unit 55, and calculates a per-unit line length by the virtual wiring and the board design information storage unit 54. Is multiplied by the delay time of the virtual wiring to obtain a virtual wiring delay. The wiring delay storage unit 57 stores the wiring delay by the virtual wiring delay calculating unit 56. The wiring delay comparing unit 58 includes a wiring allowable delay storage unit 5
3 is compared with the wiring delay by the wiring delay storage unit 57, and it is confirmed whether the component placement in the board placement and wiring design unit 55 satisfies the timing. The wiring delay comparison result storage / display unit 59/60 stores the comparison result by the wiring delay comparison unit 58 and displays it on a text basis (outputs it to a file).

As a result, the result of the timing analysis can be used for the layout design of the board (disposition of electronic components), and the number of design repetitions is reduced, so that the board design period can be shortened.

The wiring delay comparing section 58 may compare the wiring delay every time the connected electronic components are arranged, or may compare the wiring delays after all the electronic components are arranged.

Embodiment 9 FIG. In the embodiment of the invention shown in FIG. 14, as shown in FIG.
Check whether the allowable wiring delay due to 3 is within the range in which the arrangement of the electronic components and the wiring between the electronic components are actually possible (for example, if the allowable wiring delay is close to 0 (zero), the arrangement of the electronic components and the distance between the electronic components are checked). Input unit 1)
Is stored in the reference value storage unit 61. The wiring allowable delay check unit 62 compares the wiring allowable delay stored in the wiring allowable delay storage unit 53 with the reference value stored in the reference value storage unit 61, and compares the wiring allowable delay before the actual operation by the board placement and wiring design unit 55. It is possible to confirm that the arrangement of the components and the wiring between the electronic components are within a possible range.

Embodiment 10 FIG. Also, in the embodiment of the invention shown in FIG. 14, as shown in FIG. 17, in order to delete electronic components unrelated to timing from the circuit diagram data stored in the circuit diagram data storage unit 51, the circuit diagram data determination processing unit 6
Reference numeral 3 denotes additional information (for example, attached to a terminating resistor or a capacitor in the circuit diagram of the substrate shown in FIG. 18) which is previously attached to an electronic component (for example, a resistor or a capacitor) unrelated to the timing of the circuit diagram data. The information of the electronic component is read from the circuit diagram data and output to the timing analysis unit 8 (for example, in the circuit diagram data shown in FIG. 19, (a) is before deletion, and (b) is deleted). rear). By deleting information on electronic components that are not related to timing,
The analysis time in the timing analysis unit 8 can be reduced.

Embodiment 11 FIG. Also, in the embodiment of the invention shown in FIG. 17, as shown in FIG. 20, an electronic component irrelevant to the timing is not determined from the additional information of the circuit diagram data. An electronic component information discrimination processing unit 75 for judging from the internal connection information / timing information and the net name of the circuit diagram data by the circuit diagram data storage unit 51 may be provided.

Specifically, the internal delay time is 0 (zero) in the timing information of the electronic component timing information storage unit 7.
It is checked from the circuit diagram data whether there is a one-to-one relationship between the input and output pins and one of the pins is connected to the power supply or GND. Judge as a part and delete its information from the circuit diagram data.

Embodiment 12 FIG. Further, as shown in FIG. 21 in the embodiment of the invention shown in FIG. 14, the delay data conversion unit 64 includes an electronic component selected for board placement and wiring design by the board layout and wiring design unit 55 and an electronic component connected thereto. Is divided by the delay time per unit line length to convert to line length data. The line length data storage unit 56 stores the line length data calculated by the delay data conversion unit 64. The component allocable area indicating unit 66 includes a line length data storage unit 65.
Is calculated on the basis of the storage line length data according to (1), and an instruction to display the area on the board layout and wiring design unit 55 is issued.

By displaying an area where components can be placed on the board placement / wiring design unit 55, it is easy to study the placement of electronic components.

Embodiment 13 FIG. Further, instead of the virtual wiring delay calculating unit 56 in the embodiment of the invention shown in FIG.
As shown in FIG. 22, a general wiring delay calculating unit 67 may be provided which calculates a wiring delay by multiplying the wiring length wired by the board arrangement wiring design unit 55 by a delay time per unit line length.
By comparing the wiring delay calculated based on the actual wiring length with the allowable wiring delay, it is possible to determine whether it is possible to route the wiring connecting the electronic components in addition to examining the placement of the electronic components in consideration of the timing. You can also consider.

Embodiment 14 FIG. Further, instead of the virtual wiring delay calculation unit 11 in the embodiment of the invention shown in FIG.
Information necessary for waveform analysis using input unit 1 as shown in FIG.
(E.g., a waveform analysis preparation data storage unit 68 that defines and stores (e.g., VI characteristics of output pins of electronic components and rise / fall times of output signals) and a signal that is wired by the board placement / wiring design unit 55. A waveform analysis unit 69 that performs a waveform analysis simulation on the wiring information (wiring layer, wiring length, board specification, etc.) and the waveform analysis preparation data stored in the waveform analysis preparation data storage unit 68 to calculate a wiring delay may be provided. . By comparing the wiring delay calculated by the waveform analysis unit 69 with the wiring allowable delay, the wiring delay taking into account the electrical characteristics of the substrate such as reflection, and the arrangement of the electronic components and the distance between the electronic components under conditions close to actual operation. Can be considered.

Embodiment 15 FIG. In the embodiment of the invention shown in FIG. 14, as shown in FIG. 24, first, the arrangement of the electronic components is examined and determined by the means shown in FIG. The line length data converted from the hit delay time is stored in the line length data storage unit 65, and the automatic wiring design unit 70 performs automatic wiring based on the line length data. A waveform analysis simulation is performed on the wiring information of the signal automatically wired by the automatic wiring design unit 70 and the waveform analysis preparation data by the waveform analysis preparation data storage unit to calculate a wiring delay, and the wiring delay and the allowable wiring delay And confirm that there is no problem in timing. In order to check the wiring delay calculated by waveform analysis by examining the arrangement of electronic components based on the allowable wiring delay and performing automatic wiring,
It is possible to reduce the number of design iterations and shorten the design period.

The waveform analysis performed on the signals automatically routed by the automatic route design unit 70 may be performed after each signal has been routed or after all the signals have been routed.

Embodiment 16 FIG. In the embodiment of the invention shown in FIG. 14, as shown in FIG. 25, first, the arrangement of the electronic components is examined and determined by the means shown in FIG. Parameter to check whether the waveform analysis considering the crosstalk defined in (1) is necessary (for example, when 32/64 bits and a plurality of parallel wirings are used like a bus signal, the waveform analysis considering the crosstalk is necessary) (Number of parallel wires / interval /
(Parallel wiring length) and a parallel wiring number checking unit 71 for checking the number of wirings of signals adjacent to the signal wired by the board placement and wiring design unit 55 are separately provided. If the number of parallel wirings exceeds the defined number of parallel wirings, crosstalk is generated. The waveform analysis taking into account the waveform analysis unit 69 and the result (waveform data) is stored in the waveform analysis result storage unit 72. The timing analysis is performed again by the timing analysis unit 8 using the waveform analysis result from the waveform analysis result storage unit 72, and the analysis result is stored in the timing analysis result storage unit 9 and graphically displayed on the timing analysis result display unit 73.

Embodiment 17 FIG. Also, instead of the wiring delay comparison result display section 60 in the embodiment of the invention shown in FIG. 14, the wiring having a timing error based on the comparison result of the wiring delay comparison result storage section 59 as shown in FIG. A highlight display instructing unit 74 may be provided for performing a highlight display on the placement and wiring design unit 55.

The board design apparatus of the embodiment shown in FIGS. 14, 16, 17, 20, 21, 22, 23, 24, 25, and 26 has a timing verification at the circuit design stage. To calculate the permissible delay for wiring, and use the permissible wiring delay to examine and determine the layout of electronic components and wiring between electronic components. Method).

[0074]

As described above, the board design apparatus of the present invention employs a board design method based on a timing verification / graphical display function, so that the wiring delay on the board is smaller than that of a conventional method using reference signal information manually. In addition to being able to verify the circuit operation timing in consideration of time, the following effects are obtained for each invention. (1) Search for the net name specified by the user, the net name of the path that can be a reference signal or the signal added with the reference signal specification property, or any combination or all of the above, and enter the searched net name, etc. By graphically displaying the corresponding electronic components and connection information, the period and skew can be easily set for the reference signal. (2) Circuit operation that is close to the actual operation state using virtual wiring delay data that estimates and calculates the wiring length between electronic components or wiring delay data for each wiring that is calculated by considering the electrical characteristics of the board in a waveform analysis simulation It can be verified at the timing.

Further, in the board design apparatus according to another aspect of the present invention, a board design method based on a timing verification / wiring allowable delay calculation function is employed. In comparison, there is an effect that the number of design iterations can be reduced and the design period can be shortened. In addition, when examining and deciding the arrangement of electronic components and wiring between electronic components, timing analysis / waveform analysis is performed, so that design quality can be improved. Also, the timing analysis time can be shortened by deleting the information of the electronic component unrelated to the timing from the circuit diagram data. Further, the wiring allowable delay is calculated after the timing analysis, and the component allocable area is displayed on the board design CAD based on the wiring allowable delay, so that the layout of electronic components can be easily studied. Further, the wiring allowable delay is calculated after the timing analysis, and the wiring between the electronic components is automatically routed based on the wiring allowable delay, thereby shortening the board design period. Further, by highlighting the wiring that causes a timing error on the board design CAD, it is easy to change the component arrangement / wiring.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a board design apparatus according to an embodiment of the present invention.

FIG. 2 is a board circuit diagram for explaining board layout design data generated by a board placement and wiring design unit shown in FIG. 1;

3 is a diagram illustrating board connection data extracted by a board connection data extraction unit illustrated in FIG. 1 and a result analyzed by a timing analysis unit.

FIG. 4 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 5 is a diagram for explaining connection information corresponding to the net name to be graphically displayed on the provisional reference signal information display unit shown in FIG. 4;

FIG. 6 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 7 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 8 is a board circuit diagram shown as board layout design data for describing a reference signal designation property used in the property information search unit shown in FIG. 7;

FIG. 9 is a diagram for explaining a reference signal designation property used in the property information search unit shown in FIG. 7;

FIG. 10 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 11 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 12 is a diagram for explaining a function of a virtual wiring delay data calculation unit shown in FIG. 11;

FIG. 13 is a functional block diagram of a board design apparatus showing another embodiment of the present invention.

FIG. 14 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

15 is a diagram for explaining a wiring allowable delay stored in a wiring allowable delay storage unit shown in FIG. 14;

FIG. 16 is a functional block diagram of a board design apparatus showing another embodiment of the present invention.

FIG. 17 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

18 is a board circuit diagram shown as board layout design data for describing additional information of circuit diagram data used in the circuit diagram data determination processing unit shown in FIG.

19 is a diagram showing circuit diagram data before and after processing by the circuit diagram data determination processing unit shown in FIG. 17;

FIG. 20 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 21 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 22 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 23 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 24 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 25 is a functional block diagram of a board designing apparatus showing another embodiment of the present invention.

FIG. 26 is a functional block diagram of a board design apparatus showing another embodiment of the present invention.

And FIG. 27 is a flowchart illustrating the operation of the board design apparatus according to the related art.

[Explanation of symbols]

1 input section, 2 board layout and wiring design section, 3 board layout design data storage section, 4 board connection data extraction section, 5
Board connection data storage unit, 6 reference signal information storage unit, 7
Electronic component timing information storage unit, 8 timing analysis unit, 9 (timing) analysis result storage unit, 10 analysis result display unit, 11 net name search unit, 12 temporary reference signal information storage unit, 13 temporary reference signal information display unit, 14 Reference signal information definition unit, 15 reference signal path search unit, 16 property information search unit, 17 data discrimination processing unit, 18 virtual wiring delay data calculation unit, 19 wiring delay data storage unit, 2
0 waveform analysis preparation data storage unit, 21 waveform analysis unit, 5
1 circuit diagram data storage unit, 52 wiring allowable delay calculation unit,
53 wiring allowable delay storage unit, 54 board design information storage unit, 55 board arrangement wiring design unit, 56 virtual wiring delay calculation unit, 57 wiring delay storage unit, 58 wiring delay comparison unit,
59 wiring delay comparison result storage unit, 60 wiring delay comparison result display unit, 61 reference value storage unit, 62 wiring allowable delay check unit, 63 circuit diagram data discrimination processing unit, 64 delay data conversion unit, 65 line length data conversion unit, 66 Component allocable area indicating section, 67 Schematic wiring delay calculating section, 68
Waveform analysis preparation data storage unit, 69 Waveform analysis unit, 70
Automatic wiring design section, 71 Parallel wiring number check section, 72
Waveform analysis result storage unit, 73 Timing analysis result display unit, 74 Highlight display instruction unit, 75 Electronic component information discrimination processing unit.

Claims (17)

[Claims] An input section for defining and designating reference signal information, electronic component internal connection information, and timing information, and a board layout design data for arranging and wiring electronic components for separately created circuit diagram data. And a board layout design data storage unit for storing the generated board layout design data, and a board for extracting board connection data from the stored board layout design data by the board layout design data storage unit. A connection data extraction unit; a board connection data storage unit that stores the extracted board connection data; a reference signal information storage unit that stores reference signal information specified by the input unit; and an electronic device specified by the input unit. An electronic component timing information storage unit for storing component internal connection information and timing information; and a reference signal information storage unit The reference signal information stored in the electronic component timing information storage unit, the electronic component internal connection information and the timing information, and the timing between the electronic components having the timing constraint conditions with respect to the board connection data stored in the board connection data storage unit. A board design apparatus, comprising: a timing analysis unit for analyzing; an analysis result storage unit for storing an analysis result by the timing analysis unit; and an analysis result display unit for displaying the stored analysis result. 2. Searching the board connection data stored in the board connection data storage unit for a net name of reference signal information specified by an input unit, and generating connection information corresponding to the net name or the like as temporary reference signal information. Net name search unit, a temporary reference signal information storage unit for storing temporary reference signal information generated by the net name search unit, and a temporary reference signal information display unit for graphically displaying connection information corresponding to the net name and the like With the provisional reference signal information displayed by the provisional reference signal information display unit, the period and skew information are added using the reference signal information designated by the input unit to formally certify, and the input as reference signal information is performed. The board design apparatus according to claim 1, further comprising: a reference signal information definition unit that outputs the reference signal information to the reference signal information storage unit instead of the reference signal information specified by the unit. 3. A reference signal for electronic component internal connection information and timing information stored in a timing information storage unit and board connection data stored in a board connection data storage unit instead of a net name search unit. A reference signal path search unit for outputting electronic components and connection information corresponding to the net name or the like for searching and generating a path that can be used as temporary reference signal information to a temporary reference signal information storage unit. 3. The substrate designing apparatus according to 2. 4. A method for searching for and generating a net name of a signal obtained by adding a reference signal designation property to board connection data stored in a board connection data storage unit, instead of the net name search unit, and corresponding to the net name or the like. 3. The board designing apparatus according to claim 2, further comprising a property information search unit that outputs electronic components and connection information as a temporary reference signal to a temporary reference signal information storage unit. 5. Searching the board connection data stored in the board connection data storage unit for a net name of the reference signal information specified by the input unit, and generating connection information corresponding to the net name or the like as temporary reference signal information. And a path that can be a reference signal for the electronic component internal connection information and timing information stored in the timing information storage unit and the board connection data stored in the board connection data storage unit. A reference signal path search unit that outputs electronic components and connection information corresponding to the generated net name and the like to the provisional reference signal information storage unit as provisional reference signal information, and a board connection data stored in the board connection data storage unit. On the other hand, search for the net name of the signal to which the reference signal designation property is added and generate the electronic component and connection information corresponding to the net name etc. as the temporary reference signal. The property information search unit to be output to the reference signal information storage unit, the temporary name signal information generated by the net name search unit, the reference signal path search unit, and the property information search unit, and the respective search methods are determined and the timing verification is performed. Searches for any combination or all of the net name specified by the implementer, the path that can be the reference signal, and the net name of the signal with the reference signal specification property added, and generates the electronic components and connection information corresponding to the path etc. A data discrimination processing section that outputs as provisional reference signal information, a provisional reference signal information storage section that stores the provisional reference signal information generated by the data discrimination processing section, and graphical display of connection information corresponding to the net name and the like A temporary reference signal information display unit, and a temporary reference signal information specified by the input unit with respect to the temporary reference signal information displayed by the temporary reference signal information display unit. A reference signal information defining unit that performs formal recognition by adding a cycle and skew information using the reference signal information, and outputs the reference signal information to the reference signal information storage unit instead of the reference signal information specified by the input unit; The substrate designing apparatus according to claim 1, further comprising: 6. Virtual wiring delay data for calculating virtual wiring delay data from the board layout design data stored in the board layout design data storage unit and the wiring length between connection pins for estimating the timing information specified by the input unit. 6. The circuit according to claim 5, further comprising: a calculation unit; and a wiring delay data storage unit that stores the virtual wiring delay data calculated by the virtual wiring delay data calculation unit and outputs the data to the timing analysis unit. Board design equipment. 7. A waveform analysis preparation data storage unit for storing waveform analysis preparation data, and reading the waveform analysis preparation data stored in the waveform analysis preparation data storage unit, performing a waveform analysis simulation, and executing wiring analysis data for each wiring. 6. A waveform analysis unit that calculates the delay time, and a wiring delay data storage unit that stores the wiring delay data calculated by the waveform analysis unit and outputs the wiring delay data to the timing analysis unit.
A substrate designing apparatus according to item 1. 8. An input unit used for setting reference signal information, internal connection information of electronic components, timing information, and board design information; a circuit diagram data storage unit for storing circuit diagram data; a period and a pulse width of the reference signal; A reference signal information storage unit that stores information such as internal connection information and timing information of electronic components; a circuit diagram data storage unit, a reference signal information storage unit, and electronic component timing information. A timing analysis section for analyzing timing between electronic components having timing constraints from information in the storage section, a timing analysis result storage section for storing analysis results of the timing analysis section, and information stored in the timing analysis result storage section A wiring allowable delay calculating unit for calculating an allowable range as a wiring delay from the following: a value calculated by the wiring allowable delay calculating unit A wiring allowable delay storage unit, a board design information storage unit storing information on board specifications and electrical characteristics of the board, and a wiring allowable delay storage unit, a board design information storage unit, and a circuit diagram data storage unit. The board placement and wiring design unit that places and routes components based on the information, the Manhattan length between the connection pins of electronic components calculated from the component placement information by the board placement and wiring design unit, and the board design information storage unit A virtual wiring delay calculation unit that calculates a wiring delay by multiplying a delay time per unit line length, a wiring delay storage unit that stores the wiring delay calculated by the virtual wiring delay calculation unit, and a wiring allowable delay storage unit. A wiring delay comparison unit that compares the delay values of the wiring delay storage unit, a wiring delay comparison result storage unit that stores the comparison result of the wiring delay comparison unit, a wiring delay comparison result display unit that displays the wiring delay comparison result, To Board design and wherein the was e. 9. An input unit is used to check whether the value of the allowable wiring delay time of the allowable wiring delay storage unit is within a range in which electronic components can be actually arranged and wiring between electronic components is possible. A reference value storage unit that stores the set reference value, a wiring allowable delay check unit that compares the reference value and the wiring allowable delay stored in the reference value storage unit and the wiring allowable delay storage unit,
The substrate designing apparatus according to claim 8, further comprising: 10. An electronic component that is independent of timing with respect to circuit diagram data in a circuit diagram data storage unit is set at the time of circuit diagram creation. From the additional information of the electronic component of the circuit diagram data stored in the circuit diagram data storage unit. The board design apparatus according to claim 8, further comprising a circuit diagram data determination processing unit that determines and deletes information of the electronic component having the additional information from the circuit diagram data. 11. An electronic component having no relation to timing with respect to circuit diagram data in a circuit diagram data storage unit. The internal connection information and timing information of the electronic component stored in the electronic component timing information storage unit, and the circuit diagram data storage unit. 9. An electronic component information discriminating unit for judging from a net name given to each wiring of the circuit diagram data stored in the electronic device and deleting information of the electronic component from the circuit diagram data. Or the substrate designing apparatus according to 9. 12. The wiring allowable delay time between an electronic component selected for layout examination by a board layout and wiring design part and an electronic component connected thereto is divided by a delay time per unit line length into line length data. A delay data conversion unit for conversion, a line length data storage unit for storing the line length data converted from the delay time, and an area where parts can be arranged based on the line length data in the line length data storage unit. The board designing apparatus according to any one of claims 8 to 11, further comprising: a component allocable area indicating section for displaying on a design section. 13. An outline of calculating a wiring delay by arranging and wiring components in a board layout and wiring design unit and multiplying the wiring length by a delay time per unit line length stored in a board design information storage unit. 13. The board designing apparatus according to claim 8, wherein the wiring delay calculating unit is provided in place of the virtual wiring delay calculating unit. 14. A waveform analysis preparation data storage section storing data necessary for performing a waveform analysis using an input section, and data of the waveform analysis preparation data storage section and a component placement by a board placement and wiring design section. And a waveform analysis unit for performing a waveform analysis based on information such as a wiring length and a wiring layer for a signal after the wiring is performed, and a virtual wiring delay calculation unit are provided. 13. The substrate designing apparatus according to any one of 8 to 12. 15. A delay data conversion unit for converting allowable wiring delay time into line length data for data of a board placement and wiring design unit for which component placement has been considered, and storing line length data converted from the delay time. A line length data storage unit, an automatic wiring design unit that performs automatic wiring based on the line length data, and a waveform analysis unit that performs waveform analysis of signals routed by the automatic wiring design unit. 12. The board designing apparatus according to claim 8, wherein the wiring delay storage unit stores the wiring delay data calculated by the waveform analysis unit. 16. A parallel wiring number checking unit for checking the number of parallel wirings when wiring is performed on data of a board layout and wiring design unit for arranging and wiring components, and necessary for waveform analysis using an input unit. A waveform analysis preparation data storage section that stores parameters that check whether or not waveform analysis taking into account important information and crosstalk is necessary, a waveform analysis section that performs waveform analysis that takes into account crosstalk of parallel wiring, and a waveform analysis section 9. A waveform analysis result storage unit for storing result information, and a timing analysis result display unit for performing timing verification based on the waveform analysis result and displaying the result. 12. The substrate designing apparatus according to any one of claims 11 to 11. 17. A highlight display instructing unit for performing processing for highlighting a path on which an error has occurred based on the comparison result on the data in the wiring delay comparison result storage unit on a board placement and wiring design unit. 9. The method according to claim 8, wherein
17. The substrate designing apparatus according to any one of claims 16 to 16.