JPH11284914A - Solid-state image pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a still image with high image quality. SOLUTION: A shutter device 17 placed between a lens 16 and a solid-state image pickup element 11 is kept open in a 1st image pickup operation and closed after opening for a prescribed period in a 2nd image pickup operation. A drive circuit 12 is operated, based on a reference clock CKH whose frequency is high in the 1st image pickup operation and the drive circuit 12 is operated, based on a reference clock CKL whose frequency is low in the 2nd image pickup operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state imaging device using a frame transfer type CCD solid-state imaging device.

[0002]

2. Description of the Related Art An electronic still camera using a solid-state imaging device has been used as a means for taking image information into a computer device such as a personal computer or a word processor. This electronic still camera is configured to capture a subject image as a moving image, that is, a sequence of still images, and extract desired one-screen image information from the moving image, that is, a sequence of still images, similarly to a conventional imaging device such as a television camera. .
Usually, in the processing of image information of such an electronic still camera, in order to speed up the processing, a continuous image is reproduced with an image signal of a small amount of information which is appropriately thinned out, and one screen of an image to be finally extracted is finally obtained. Complete signal processing is performed only on image information.

FIG. 3 is a block diagram showing a configuration of an electronic still camera. The CCD solid-state imaging device 1 has a plurality of light receiving pixels arranged in a matrix and a shift register associated with each light receiving pixel. The plurality of light receiving pixels generate and accumulate information charges in response to light corresponding to the subject image irradiated on the light receiving surface by a known lens mechanism. The shift register transfers and outputs information charges accumulated in each light receiving pixel in a predetermined order. Further, the solid-state imaging device 1 is provided with a capacitor for accumulating information charges in pixel units at an output end of the shift register, and the amount of information charges transferred and output is converted into a voltage value and taken out. It is output as an image signal Y0 (t).

A drive circuit 2 supplies a multi-phase vertical transfer clock φv and a horizontal transfer clock φh to each shift register of the solid-state image pickup device 1, and converts information charges accumulated in a plurality of light receiving pixels in a predetermined order. Transfer and output. That is, after the information charges are transferred from the light receiving pixels of the solid-state imaging device 1 to the shift register at the timing according to the vertical synchronization signal VT, the information charges are transferred and output line by row at the timing according to the horizontal synchronization signal HT, thereby obtaining the image signal Y0. (t). The timing control circuit 3 generates a vertical scanning signal VT and a horizontal synchronization signal HT based on a reference clock having a constant period, and supplies the generated signal to the drive circuit 2. The vertical synchronizing signal VT and the horizontal synchronizing signal HT are for determining the timing of the vertical scanning and the horizontal scanning of the solid-state imaging device 1, and are generated according to a predetermined television system. At the same time, a timing signal PC for normalizing the image signal Y0 (t) in accordance with the vertical synchronizing signal VT and the horizontal synchronizing signal HT is generated and supplied to a signal processing circuit 4 described later. Further, the timing control circuit 3 stops the continuous imaging operation of the drive circuit 2 in response to the image determination instruction DM, and instructs the signal processing circuit 4 to output image data D of one specific screen corresponding to the image signal Y0 (t). (n) is output.

[0005] The signal processing circuit 4 captures the image signal Y0 (t) output from the solid-state image sensor 1 and outputs the timing signal P
Various processes such as sample hold and level correction are performed according to C, and an image signal Y1 (t) conforming to a predetermined format is performed.
Is supplied to the display 5. This signal processing circuit 4
A / D converter and a D / A converter, perform signal processing using the image signal Y0 (t) as digital data, and after completion of predetermined signal processing, return to an image signal Y1 (t) of an analog value to display. 5. Further, the signal processing circuit 4 supplies digital image data D (n) corresponding to one screen of the image signal Y0 (t) when the timing control circuit 3 receives the image determination instruction DM to the outside as a still image output. I do. The display 5 is composed of an LCD panel or the like, and continuously displays images taken by the solid-state imaging device 1 according to the image signal Y1 (t) supplied from the signal processing circuit 4. After receiving the image confirmation instruction DM, a still image corresponding to the image data D (n) output as a still image output is displayed.

FIG. 4 is a schematic diagram showing the configuration of the frame transfer type CCD solid-state imaging device 1, and FIG. 5 is a timing chart showing the relationship between a synchronization signal and each transfer clock for driving the solid-state imaging device 1. . In this figure, for simplification of the drawing, the arrangement of the light receiving pixels is shown by 12 rows × 16 columns. The frame transfer type CCD solid-state imaging device 1 includes a light receiving unit 1i, a storage unit 1s, a horizontal transfer unit 1h, and an output unit 1d. The light receiving section 1i is composed of a plurality of CCD shift registers that are continuous in the vertical direction and are parallel to each other, and each bit of these shift registers constitutes a light receiving pixel. A multi-phase frame transfer clock φf synchronized with the vertical synchronizing signal VT is applied to the light receiving unit 1i, and information charges accumulated in each light receiving pixel during the imaging period are supplied to the accumulation unit 1s during the vertical scanning blanking period. High-speed transfer.

The storage section 1s is composed of a plurality of CCD shift registers of the same number of bits which are continuous with the shift register of the light receiving section 1i, and each bit of these shift registers is transferred and output from each light receiving pixel of the light receiving section 1i. Information charges are temporarily stored. A multi-phase vertical transfer clock φv synchronized with the vertical synchronizing signal VT and the horizontal synchronizing signal HT is applied to the storage unit 1s, and information charges are taken from the light receiving unit 1i in units of one screen, and the taken information charges are taken. Are transferred to the horizontal transfer unit 1h on a row-by-row basis during the blanking period of horizontal scanning.

The horizontal transfer unit 1h is composed of a single CCD shift register in which the output of each shift register of the storage unit 1s is combined with each bit, and stores information charges transferred and output from each shift register of the storage unit 1s. Receive a bit. A multi-phase horizontal transfer clock φh synchronized with the horizontal synchronization signal HT is applied to the horizontal transfer unit 1h, and information charges transferred and output from each shift register of the storage unit 1s in units of one horizontal line are sequentially output to the output unit 1d. Transferred to the side.

The output section 1d includes a capacitor for receiving information charges on the output side of the horizontal transfer section 1h, receives the information charges transferred and output from the horizontal transfer section 1h, and outputs a voltage value corresponding to the charge amount. A reset clock φr according to the horizontal transfer clock φh is applied to the output unit 1d, and the horizontal transfer unit 1h
By discharging the information charges sequentially transferred and output from each pixel, a voltage value corresponding to the information charge amount for each pixel is extracted. The change in the voltage value output here becomes the image signal Y0 (t).

In such a solid-state imaging device 1 of the frame transfer system, the storage section 1s for temporarily storing the information charges obtained by imaging is separated from the light receiving pixels of the light receiving section 1i. Leakage of unnecessary charges from the device is small.
Therefore, the present invention is suitable for an electronic still camera that obtains a still image by reading information charges from a solid-state imaging device at an arbitrary timing.

[0011]

The above-mentioned solid-state image pickup device 1
, The vertical transfer clock φv and the horizontal transfer clock φh depend on the cycle of the vertical synchronization signal VT and the number of light receiving pixels.
Is set. That is, the number of horizontal scans corresponding to the number of light receiving pixels (the number of horizontal lines) in the vertical direction during vertical scanning is enabled, and information charges can be read from all light receiving pixels of one horizontal line during each horizontal scan. Vertical transfer clock φ
v and the frequency of the horizontal transfer clock φh are set. Therefore, as the number of light receiving pixels of the solid-state imaging device 11 increases, the frequencies of the vertical transfer clock φv and the horizontal transfer clock φh increase. For example, if the number of light receiving pixels of the solid-state
When an image of 30 frames per second is obtained at 0 (V) × 800 (H), the output frequency is 14.4 MHz even if the blanking period is ignored, so that the actual horizontal transfer clock φh is , The frequency must be set to about 20 MHz.

In a CCD shift register having a semiconductor structure,
When the frequency of the transfer clock increases, the change in the potential of the electrode cannot sufficiently follow the transfer clock, so that the transfer capability of the information charge decreases. Therefore, the transfer of the information charges is apt to occur in the shift register, and the S / S of the image signal is reduced.
The N ratio decreases, and the image quality of the playback screen deteriorates. Such deterioration in image quality becomes more noticeable when a still image is displayed by an image signal.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to prevent a deterioration in image quality due to a higher frequency of a transfer clock when the number of light receiving pixels of a solid-state imaging device is increased.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and the feature of the present invention is that a subject image is repeatedly captured and image information is continuously displayed in units of one screen. A first imaging operation for obtaining a first image signal to be performed, and one of continuous images displayed by the first image signal
A second image capturing operation for newly capturing a subject image corresponding to the second image signal to obtain a second image signal including image information for one screen;
A solid-state imaging device including a light receiving unit in which a plurality of light receiving pixels are arranged in a matrix and a storage unit in which a plurality of storage pixels corresponding to the plurality of light receiving pixels are arranged in a matrix, A lens mechanism for forming a subject image on a light receiving portion of the imaging device, a shutter mechanism for opening and closing on the optical path of light irradiated to the light receiving portion of the solid-state imaging device through the lens mechanism, and a first imaging operation. Opening the shutter mechanism, transferring the information charges continuously accumulated in the respective light receiving pixels of the light receiving unit of the solid-state imaging device to the storage pixels of the storage unit at a fixed cycle, and then transferring the information charges from the storage unit in units of one row. The first image signal is output to obtain a first image signal, and in the second imaging operation, the shutter mechanism is opened and closed for a predetermined period and then closed, and the information charges accumulated in each light receiving pixel of the light receiving section of the solid-state imaging device are accumulated. To the storage pixels After feeding, and a driving circuit for obtaining a second image signal transferred output from the storage unit on a line-by-line basis,
The drive circuit is configured to set a transfer frequency for transferring and outputting information charges from a storage unit of the solid-state imaging device to be lower in the second imaging operation than in the first imaging operation.

According to the present invention, the shutter mechanism operates only in the second imaging operation for obtaining a still image, and the irradiation of light to the light receiving section is cut off. In this state,
By setting the transfer frequency for transferring and outputting information charges from the storage unit lower than in the first imaging operation,
The transfer efficiency of the solid-state imaging device can be prevented from being lowered.

[0016]

FIG. 1 is a block diagram illustrating an embodiment of a solid-state imaging device according to the present invention, and FIG. 2 is a timing chart illustrating the operation thereof. The solid-state imaging device according to the present invention is provided with a first image signal for obtaining a first image signal for displaying a moving image.
And the second imaging operation for obtaining a second image signal for displaying a still image are executed in response to an external instruction.

The CCD solid-state imaging device 11 is of the same frame transfer system as the solid-state imaging device 1 shown in FIG. 4, and has a light receiving section and a storage section. The solid-state imaging device 11 outputs a first image signal Y0 (t) that continuously displays an image at a constant period in the first imaging operation, and outputs an image for one screen in the second imaging operation. Is output as the second image signal y0 (t).

The drive circuit 12 supplies a multi-phase frame transfer clock φf, a vertical transfer clock φv, and a horizontal transfer clock φh to each part of the solid-state imaging device 11, and converts information charges accumulated in each light receiving pixel to a predetermined value. Transfer and output in order. The drive circuit 12 is configured to generate a frame transfer clock φf, a vertical transfer clock φv, and a horizontal transfer clock φh according to one of two types of reference clocks CKH and CKL having different frequencies. That is, in the first imaging operation in which the solid-state imaging device 11 is continuously operated, each transfer clock is generated based on, for example, a high first reference clock CKH having a frequency of 20 MHz. And
In the second imaging operation in which the solid-state imaging device 11 is operated only once, each transfer clock is generated based on, for example, a second reference clock CKL having a frequency of 200 kHz.

The timing control circuit 13 generates a vertical synchronizing signal VT and a horizontal synchronizing signal HT based on a reference clock having a constant period, and supplies the generated signal to the drive circuit 12. The vertical synchronizing signal VT and the horizontal synchronizing signal HT allow the driving circuit 12 to operate continuously in the first imaging operation so that the solid-state imaging device 11 can obtain an image signal Y0 (t) for displaying a moving image. Then, the driving circuit 12 is operated only once in the second imaging operation so that the image signal y0 (t) for displaying a still image can be obtained from the solid-state imaging device 11. Further, the timing control circuit 13 opens the shutter mechanism 17 in the first imaging operation, and opens the shutter mechanism 17 for a certain period in the second imaging operation.
Control signal S instructing to close after opening
T is generated and supplied to the shutter drive circuit 18.

The signal processing circuit 14 includes an A / D converter and a D / D converter.
/ A converter, performs signal processing using the image signals Y0 (t) and y0 (t) as digital data, and converts the analog image signals Y1 (t) and y1 (t) after predetermined signal processing is completed. It is configured to be returned to the display 15. In the first imaging operation, the signal processing circuit 14
The image signal Y0 (t) output from the device is taken in, subjected to various processes such as sample hold, level correction, etc., in accordance with the timing signal PC.
It is supplied to the display 15 as 1 (t). In the second imaging operation, the image signal y0 (t) output from the solid-state imaging device 11 is fetched and subjected to various processes such as sample hold and level correction similarly to the image signal Y0 (t). , And supplies digital image data D (n) corresponding to the image signal y0 (t) to the outside as a still image output. At this time, an image signal y1 (t) is also supplied to the display 5 in response to the still image output. The display 15 includes an LCD panel or the like, and displays an image according to the image signals Y1 (t) and y1 (t) supplied from the signal processing circuit 14.

The lens mechanism 16 is arranged corresponding to the light receiving section of the solid-state image sensor 11, takes in light from the object, and forms a subject image on the light receiving section of the solid-state image sensor. The shutter mechanism 17 is disposed between the lens mechanism 16 and the solid-state imaging device 11, and blocks light emitted to a light receiving unit of the solid-state imaging device 11 as necessary. This shutter mechanism 17
Any device that can control light transmission may be used, and a liquid crystal panel, a light shielding plate, or the like may be used. The shutter drive circuit 18 generates a drive clock φd based on a shutter control signal ST supplied from a timing control circuit 13 described later.
Is generated, and the shutter mechanism 17 is driven to open and close. For example,
The shutter mechanism 17 is opened while the shutter control signal ST is rising, and the shutter mechanism is closed while the shutter control signal ST is falling.

In the first imaging operation, the timing control circuit 13 continuously generates the vertical synchronizing signal VT and the horizontal synchronizing signal HT, and operates the driving circuit 12 periodically.
As a result, the solid-state imaging device 11 repeats the operation in a cycle according to the vertical synchronization signal VT, and the image signal Y for displaying a moving image
Outputs 0 (t). At this time, the shutter control signal ST
The shutter drive circuit 18 is still activated,
The shutter mechanism 17 is kept open.

When the image determination instruction DM is input while the first imaging operation is continued, first, the shutter control signal ST falls, the shutter mechanism 17 is closed once, and the solid-state imaging device 11 The light receiving unit is shielded from light. In this state, a frame transfer operation is performed to discharge information charges accumulated in each light receiving pixel of the light receiving section. This discharging operation is achieved by repeating the same operation as the transfer operation up to that time once more.

When the discharging operation is completed, the first imaging operation is completed, and the operation shifts to the second imaging operation. In the second imaging operation, the shutter control signal ST is raised for a predetermined period to open the shutter mechanism 17, and information charges are accumulated in each light receiving pixel of the light receiving section of the solid-state imaging device 11. The opening time of the shutter mechanism 17 is set in accordance with the brightness of the subject so that the average of the information charges accumulated in the light receiving unit of the solid-state imaging device 11 falls within a predetermined range. Here, the optimal shutter release time may be set based on the average level of the image signal Y0 (t) obtained in the first imaging operation, or may be set by directly measuring the brightness of the subject. Then, after the shutter control signal ST falls, a new frame transfer operation is performed to transfer the information charges accumulated in each light receiving pixel of the imaging unit to the accumulation unit, and further, from the accumulation unit according to the horizontal synchronization signal HT. Transfer and output line by line. At this time, in the drive circuit 12, since the second reference clock CKL having a low frequency is selected, the information charges are surely transferred at the time of horizontal transfer, so that a transfer failure rarely occurs, and the image signal y0 (t) is not transferred. The S / N ratio is kept high.

In the above embodiment, the driving circuit 12
In this example, the frequency of each transfer clock is switched by switching the frequency of the reference clock supplied to the drive circuit 12. However, the frequency of the transfer clock can be switched by switching the frequency division ratio inside the drive circuit 12. It is. In this case, only the horizontal transfer clock φh needs to set the frequency low in the second imaging operation.

[0026]

According to the present invention, the frequency of the transfer clock is set low in the second imaging operation for obtaining a still image in which image deterioration is conspicuous, so that the transfer efficiency of the shift register of the solid-state image sensor decreases. Is prevented. Therefore, it is possible to prevent a decrease in the S / N ratio of the image signal and prevent the image quality of the still image represented by the image signal from deteriorating.

Further, since the shutter mechanism operates only in the second imaging operation, power consumption by driving the shutter mechanism can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an embodiment of a solid-state imaging device according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the solid-state imaging device of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a conventional solid-state imaging device.

FIG. 4 is a plan view schematically showing a conventional frame transfer type solid-state imaging device.

FIG. 5 is a timing chart for explaining the operation of the solid-state imaging device of the frame transfer system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1, 11 CCD solid-state image sensor 1i Light receiving part 1s Storage part 1h Horizontal transfer part 1d Output part 2, 12 CCD drive circuit 3, 13 Timing control circuit 4, 14 Signal processing circuit 5, 15 Display 16 Lens mechanism 17 Shutter mechanism 18 Shutter drive circuit

Claims (2)

[Claims] 1. A first image capturing operation for repeatedly capturing an image of a subject to obtain a first image signal in which image information is continuous for each screen, and a first image capturing operation of the continuous image displayed by the first image signal A second imaging operation for newly capturing a subject image corresponding to one and obtaining a second image signal including image information for one screen, wherein the plurality of light receiving pixels are A solid-state imaging device including a light-receiving portion arranged in a matrix and a storage portion in which a plurality of storage pixels corresponding to the plurality of light-receiving pixels are arranged in a matrix, and a lens mechanism that forms a subject image on the light-receiving portion of the solid-state imaging device. A shutter mechanism that is controlled to open and close on an optical path of light emitted to the light receiving unit of the solid-state imaging device through the lens mechanism, and that the shutter mechanism is opened in a first imaging operation, and a light receiving unit of the solid-state imaging device is opened. Continuously accumulated in each light receiving pixel After transferring the information charges to the storage pixels of the storage unit at a fixed period, the storage unit transfers and outputs the information charges on a row-by-row basis to obtain a first image signal. After the information charge stored in each light-receiving pixel of the light-receiving section of the solid-state imaging device is transferred to the storage pixel of the storage section, the storage section transfers and outputs the information charge in units of one row to form a second image. A driving circuit for obtaining a signal;
Wherein the drive circuit sets a transfer frequency for transferring and outputting information charges from a storage unit of the solid-state imaging device to be lower in the second imaging operation than in the first imaging operation. Imaging device. 2. A driving circuit according to claim 1, wherein said driving circuit generates a multi-phase transfer clock in response to a reference clock whose frequency is switched between said first imaging operation and said second imaging operation. The solid-state imaging device according to claim 1, wherein the solid-state imaging device is supplied to an imaging element.