JPH11282767A - Data processor and fault recovery method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processor and its fault recovery method which can recover a bus line fault generated by accompanying pulling out of an input/ output substrate without stopping system operation. SOLUTION: When a fault occurs to a bus line 2, an interruption signal is transmitted to each of input/output substrates 4, 5, 6 and 7 from a CPU substrate 1, it is confirmed whether or not there is a response from each of the input/output substrates to this interruption signal and the input/output substrate which does not respond is specified as a occurrence factor of the bus error. Then, structural information of the input/output substrate that is the occurrence factor of the bus error is deleted from the whole and is undefined. Thus, it is possible to restart system operation without reactivating the system and restructuring the structural information and to realize a transmitter that enables twenty-four hours' continuous operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing apparatus such as a transmission apparatus that operates continuously for 24 hours and a method for recovering from a failure.

[0002]

2. Description of the Related Art Some industrial transmission apparatuses operate in a continuous operation for 24 hours so that data is not lost. In such a transmission device operating continuously for 24 hours, it is necessary to avoid shutting down the system by turning off the power supply of the system under any circumstances.

In such a non-stop transmission device, the CP
Various input / output boards for communication for inputting / outputting data to / from peripheral devices, digital input / output, and analog input / output are connected to the CPU board on which the U and the memory are mounted via bus lines. It is configured to mutually input and output data with the CPU board through this bus line.

[0004] In such a non-stop transmission device, at the time of system startup, configuration information on each input / output board (such as information defining the type of the input / output board and the access method) is stored in the CP.
The information is stored in a storage unit such as a RAM mounted on the U board, and the system is operated based on the stored configuration information. That is, the CPU generates periodic access timing to the target input / output board while referring to the configuration information, and inputs / outputs data to / from each input / output board according to the access timing.

In such a non-stop transmission device, when an input / output board during operation of the system is removed for maintenance or replacement, the configuration information of the mounting board referenced by the system and the actual board mounting state Therefore, no response is returned to the access to the extracted input / output board, and a bus error occurs due to a timeout. Therefore, a method is used in which an interrupt signal is sent from the input / output board to the CPU, and data is input / output to / from the input / output board that has been confirmed to be mounted by the interrupt signal.

However, even with this method, the CP
If the I / O board is removed before U starts to access the board after confirming the mounting of the I / O board, a bus error similarly occurs. When a bus error occurs in this way, it is necessary to stop the system once, remove the cause of the failure, and then restart the system to recover from the failure. For this reason,
It has been considered difficult to completely stop the transmission device.

[0007]

As described above, in a data processing apparatus such as a transmission apparatus which is intended to operate completely without interruption for 24 hours, the insertion / removal work of the input / output board during the system operation is performed. When a bus error occurs, it is necessary to temporarily stop and restart the system in order to recover from the bus error. Therefore, it has been difficult to realize complete non-stop operation.

The present invention has been made to solve such a problem, and a data processing apparatus capable of recovering from a bus line failure caused by removal of an input / output board without stopping system operation. And a method for recovering from the failure.

[0009]

In order to achieve the above object, a data processing apparatus according to the present invention comprises at least a main board on which a central processing unit is mounted, and a plurality of input / output terminals for inputting / outputting peripheral devices. A board, and a bus line for transferring data between the main board and each of the input / output boards, wherein the central processing unit is configured to control the input / output board based on configuration information regarding the mounted input / output boards. In a data processing device for inputting and outputting data, when a failure occurs in the bus line, the presence / absence of each of the input / output boards is checked by interrupt processing, and a configuration relating to the input / output boards not mounted is provided. It is characterized by having means for deleting information from the whole.

According to the present invention, when a failure occurs in a bus line due to removal of an input / output board or the like, the presence or absence of mounting of the individual input / output boards is confirmed by interrupt processing, and mounting is performed based on the confirmation result. By deleting the configuration information relating to the non-existent I / O boards from the entire system, it is possible to recover the bus line without restarting the system and reconstructing the configuration information relating to each I / O board.
It is possible to improve the reliability of the data processing device for continuous operation for four hours.

[0011]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of an interference cancellation receiver according to the present invention.

FIG. 1 is a diagram showing a configuration of a transmission apparatus according to an embodiment of the present invention for continuous operation without interruption for 24 hours.

As shown in FIG. 1, this transmission device has a CP
CPU board 1 on which U, memory, etc. are mounted, and this CPU
It comprises various input / output boards connected to the board 1 via a bus line 2 and an interrupt signal line 3, for example, communication interface boards 4 and 5, a digital input / output board 6, an analog input / output board 7, and the like.

The CPU board 1 and the input / output boards 4, 5, 6,
7 is performed using the bus line 2. Further, the CPU checks whether or not the input / output board is mounted on the basis of the interrupt signals individually sent from the individual input / output boards 4, 5, 6, 7 via the interrupt signal line 3, and confirms that the input / output board is mounted. Input / output data to / from the confirmed input / output board.

In this transmission device, when the system is started, information on each of the input / output boards 4, 5, 6, and 7 (for example, information defining the type of the board and the access method) is transmitted to the CP.
The configuration information is stored in a storage unit such as a RAM mounted on the U board 1, and the system is operated based on the configuration information. That is, as shown in FIG. 2, the CPU generates periodic access timings for each of the input / output boards 4, 5, 6, and 7 based on the configuration information. Each input / output board 4,
The input / output board, which has been confirmed to be mounted by the interrupt signals from 5, 6, and 7, is accessed to input and output data to and from the input / output board.

Next, in the transmission apparatus of the present embodiment, a bus error due to the removal of the input / output board, particularly, the bus error between the time when the CPU starts accessing the certain input / output board and the time when the response is returned. The failure recovery operation when a failure occurs in line 2 will be described with reference to the flowchart in FIG.

A failure of the bus line 2 occurs (step 3).
1) When the CPU bus error signal is asserted, C
The PU generates a second interrupt signal for specifying the cause of the fault (step 32), and sends the second interrupt signal to each of the input / output boards 4, 5, 6, and 7 via the interrupt signal line 3 (step 33). ). The CPU confirms whether or not there is a response from each of the input / output boards 4, 5, 6, and 7 in response to the transmission of the interrupt signal, and specifies the access address of the input / output board to which this response does not return as a cause of the bus error (step 3
4).

Subsequently, the CPU deletes unnecessary configuration information related to the input / output board from the storage unit from the access address of the input / output board specified as the cause of the bus error (step 35). This completes the interrupt processing, and upon completion of the interrupt processing, the CPU resumes access to the input / output board based on the updated configuration information (step 36).

As described above, in the present embodiment, when a bus error occurs, the input / output board which caused the failure is specified by the interrupt processing, and the configuration information relating to the input / output board is undefined. By deleting from the original overall configuration information, the system can be restarted without restarting the system and reconstructing the configuration information on the I / O board. The reliability of the transmission device can be improved.

Although the above is an embodiment in which the present invention is applied to a transmission apparatus, the present invention is not limited to a data transmission apparatus, but may be any other data processing apparatus such as a personal computer. It goes without saying that the present invention can be applied to an apparatus.

[0021]

As described above, according to the present invention, when a bus line failure occurs due to removal of an input / output board or the like, whether or not each input / output board is mounted is confirmed by interrupt processing. Based on the confirmation result, the configuration information on the unmounted I / O boards is deleted from the whole, so that the system is restarted and the failure recovery of the bus line is performed without reconstructing the configuration information on each I / O board. Therefore, it is possible to improve the reliability of the data processing device intended for continuous operation for 24 hours.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a configuration of a transmission apparatus according to an embodiment of the present invention for non-stop operation for 24 hours.

FIG. 2 is a flowchart illustrating a procedure of accessing an input / output board in the transmission device of FIG. 1;

FIG. 3 is a flowchart illustrating a procedure for recovering from a bus line failure in the transmission apparatus of FIG. 1;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU board 2 Bus line 3 Interrupt signal line 4, 5 Communication interface board 6 Digital input / output board 7 Analog input / output board

Claims (2)

[Claims] 1. A main board on which at least a central processing unit is mounted; a plurality of input / output boards for inputting / outputting to / from peripheral devices; and a bus for transferring data between the main board and each of the input / output boards. Wherein the central processing unit is configured to input / output data to / from each of the input / output boards based on configuration information regarding the mounted input / output boards. The data processing device further comprises means for confirming whether or not each of the input / output boards is mounted by interrupt processing, and deleting the configuration information relating to the unmounted input / output boards from the whole. 2. A main board on which at least a central processing unit is mounted; a plurality of input / output boards for inputting / outputting with peripheral devices; and a bus for transferring data between the main board and each of the input / output boards. A central processing unit, wherein the central processing unit is configured to perform input / output of data with respect to each of the input / output boards based on configuration information regarding the mounted input / output boards. When a line failure occurs, the presence / absence of each of the I / O boards is confirmed by interrupt processing, and the bus line failure is recovered by deleting the configuration information relating to the unmounted I / O boards from the whole. Recovery method for a data processing device.