JPH11282751A - System and method for data processing - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a data processing system which enable an out-of-order transfer without influencing existing software and is of high performance and efficient in a data processor having a virtual storage system. SOLUTION: In response to a request from I/O adapters 10-1 to 10-3, an I/O bus bridge 7 allows an ADT 8 to translate an address outputted to an I/O bus 9 into a virtual storage address then allows a host bus bridge 4 to translate the virtual storage address after translation into a physical address of a main storage device 2 by using a TLB 5. Thus, it is possible to flexibly deal with data transfer in a different address space at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a data processing system and a data processing method, and more particularly to data transfer between a plurality of bus systems having different address space definitions in information processing supporting a virtual storage system including a plurality of bus systems. It is about the method.

[0002]

2. Description of the Related Art Generally, in an information processing system,
The main storage device is connected to the host bus, while the input / output device is connected to the I / O bus via an I / O adapter. Therefore, when performing data transfer between the input / output device and the main storage device, it is necessary to perform data transfer across the host bus and the I / O bus. Further, in the host bus, the physical address of the main storage device is used as address information, and the I / O
The bus has an architecture unique to the I / O bus, and defines a unique address space different from address information on the host bus.

Furthermore, today's general computer systems have realized virtual memory systems, and these three types (host bus address space = main memory physical address space,
It is necessary to solve the correspondence between the I / O bus address space and the virtual memory address space. Generally, I / O operations are described by a control structure generated by software called a channel program. For example, in the case of a disk device, it is necessary to indicate movement of a head, an instruction of a block number of data, an instruction of the number of transfer blocks, an instruction of read or write, and an intermediate report to software during operation. Are included in the channel program.

[0004] The channel program also includes the following information. That is, when data is read from the I / O device, the address of the main storage device where the read data is to be written, and when the data is written to the I / O device, the data is stored. The address of the main storage device is included, and these are prepared by software.

Further, in order to reduce the load on the central processing unit, addresses of data on the main storage device are described by virtual storage addresses. The I / O processor knows the address of the channel program placed in the main storage device according to an instruction from the central processing unit, reads the channel program, converts the virtual storage address included in the channel program into a physical address of the main storage device, Hardware must be able to access main storage.

In a computer system having a virtual storage system, a virtual storage address space is divided and managed in units of several kilobytes (kilobytes = 210 bytes) called pages. Pages are arranged at consecutive addresses in the virtual memory address space. However, even if the pages are adjacent pages in the virtual memory address space, there is a possibility that each page is distributed and arranged in the main storage device (addresses inside a page are both physical addresses and virtual memory addresses). With consecutive addresses). Therefore,
Each time a page boundary is crossed, a translation from a virtual storage address to a physical address must be performed.

In order to satisfy the above-described conditions, focusing on handling of data addresses when performing data transfer (Direct Memory Access; also referred to as DMA), there are the following conventional techniques.

First, in the first conventional example, a physical address of data is stored in the host bus bridge, and the address is updated (added or subtracted) every time data is transferred. I /
In a device higher than the O bus bridge (closer to the main storage device), the address space of the I / O bus is ignored, and the address registers and I / O adapters are identified and managed by IDs unique to the I / O adapter. An address register is provided for each I / O adapter inside the host bus bridge, and a microprogram of the I / O processor stores a data transfer start address (main storage device physical address) in the address register.
Write. The conversion into the virtual storage address or the physical address is performed while the I / O processor microprogram refers to the conversion table expanded in the main storage device.

A description will be given with reference to FIG. In FIG. 12, a CPU 1 and a main storage device (MMU) 2 are connected to a host bus 3, and a plurality of I / O adapters (I / OA) 10-1 to 10-3 are connected to an I / O bus 9. It is connected. The physical address registers PADR4-1a to PADR4-1c are
The adapter holds the physical address of the main storage device to which data is transferred. For example, PADR4-1a stores the physical address of the data transfer that the I / O adapter 10-1 is trying to perform. The setting of the PADR is performed by a microprogram of the I / O processor 6.

The I / O processor 6 performs conversion from a virtual storage address to a physical address by referring to various conversion tables developed in the main storage device by software, and obtains the obtained physical address (data area of the main storage device). To the head of PADR4-1a). I / O adapter 10-1 to I
When there is a data transfer request via the / O bus 9, the bus controller 4-2 corresponds to the I / O adapter 10-1.
An ID number is generated, PADR4-1a is read, and sent to the host bus 3 (line 4-4). Each time a data transfer request is completed,
The value of PADR4-1a is updated and written back by the adder 4-3.
For example, if 32 bytes are transferred in one request, the content is +32 written back to PADR4-1a.

When it is detected that the added result exceeds the page boundary (for example, when the page size is 4 kilobytes, the value of PADR4-1a before addition is 0000FFE0 (h), and the value after addition is Becomes 00010000 (h)), interrupts the microprogram of the I / O processor 6, the microprogram of the I / O processor 6 obtains the address of the next page, and updates the value of PADR4-1a. To the physical address corresponding to the top of the page.

In the second conventional example, when data is transferred between a main storage device and an input / output device, the input / output device issues a request using a virtual storage address on an I / O bus.
Each time data transfer is performed (by the host bus bridge or the I / O bus bridge), the virtual memory is converted into a physical address, and the main storage is accessed with the converted physical address. This conversion is performed using the translation look-up buffer (Translation Look-
aside Buffer: TLB). The TLB has a plurality of pairs of a virtual memory address and a corresponding main memory physical address, and each time the access is made, the virtual memory address in the TLB is compared with the accessed virtual memory address.

If there is an address that matches the TLB,
The main memory is accessed using the physical address paired with the virtual memory address, and if they do not match, a page fault interrupt is generated. Due to the page fault interrupt, the conversion pair of the TLB is exchanged, and the virtual memory address and physical address of the accessed page are newly added to the TLB.
Registered in.

FIG. 13 shows an example of the configuration. FIG.
, The same parts as those in FIG. 12 are indicated by the same reference numerals. Reference numeral 15 in FIG. 13 corresponds to the address translation pair. Examples of this prior art include JP-A-173930 and JP-A-6-19836.

[0015]

A first problem of the prior art is that it cannot cope with out-of-order data transfer. In the conventional data transfer, reading or writing of data from the main storage always starts from the first address of the data area. Then, in the case of transfer in the forward direction, data is always transferred to consecutive addresses in ascending order of addresses (in the case of transfer in the backward direction, descending order of addresses). For example, when data is written from address 200,000 (h) to the main memory in the forward direction of 64 kilobytes, data transferred from the I / O device starts from address 200,000, 200001, 200002,.
And ends with address 20FFFF (h). Such a transfer is called an in-order transfer.

On the other hand, in the Out-of-Order transfer, the order of the transfer data is not guaranteed. If the start address of the main memory of the transfer data is 200,000 and the transfer byte count is 64 kilobytes, the order of data transfer between addresses 200,000 and 20FFFF is a transfer method that is not guaranteed. For example, an I / O device has 20
When it is detected that there is 32 kilobytes from address 8000, data transfer is not started from address 200,000, but is started from address 208000, and transfer to address 20FFFF is performed first. In addition, during the above transfer, read the remaining 32 Kbytes from the device, then
Transfer from address 0000 to address 207FFF is performed.

The first prior art system is based on the premise of in-order transfer. That is, it is assumed that data is always continuously transferred on the virtual storage address. Therefore, there is a problem that it is not possible to cope with an out-of-order transfer in which data may be scattered on a virtual memory address or an address regularity may not be maintained as in an out-of-order transfer. Out-of-order transfer is a transfer method adopted to improve the performance of a disk having a disk array or a cache.

Next, the problem of the second prior art will be described. In large computer systems, I / O devices or I / O adapters are connected to the I / O bus through a bus bridge, rather than directly to the host bus. this is,
Such a configuration is unavoidable due to restrictions on the electrical load of the host bus. The I / O bus shares an address line and a data line, and its bit width is about 32 bits. Therefore, the address space that can be used on the I / O bus is limited to about 4 GB.

On the other hand, the size of the virtual memory address space provided by the computer system ranges from several gigabytes (gigabytes = 230 bytes) to several tera (terabytes = 240).
It is. On the other hand, the size of the address space that the input / output device can handle is at most about 4 GB. Therefore, when a part of the virtual memory address space is assigned as an I / O bus address space, the area of the virtual memory address space that can be used as an input / output buffer area becomes (lower address space).
There is a problem that the size of the virtual memory address space cannot be used effectively because of the restriction. Furthermore, there is a problem that this restriction must be imposed even in software development.

An object of the present invention is to enable a data processing apparatus having a virtual storage system to perform out-of-order transfer without affecting existing software, and to provide a high-performance and efficient data processing system and data processing method. It is to provide.

[0021]

According to the present invention, a virtual storage system is adopted, a central processing unit, a main storage unit, a host bus connecting these central processing units and the main storage unit, and Data including an I / O bus having a unique address space different from each address space of the virtual storage system and the main storage device, and an I / O adapter connected to the I / O bus and having an input / output device under the I / O bus A processing system, comprising: a first address converter connected to the I / O bus for converting an address output on the I / O bus in response to a request from the I / O adapter to a virtual memory address Means for making an access request to the main storage device using the virtual storage address converted by the first address conversion means in response to a request from the I / O adapter. An I / O bus control means having a stage, and connected to the host bus, for converting the virtual storage address into a physical address of the main storage device in response to an access request from the I / O bus control device. There is provided a data processing system including: a host bus control unit having a second address conversion unit and a unit for accessing the main storage device using the physical address.

When the access request is a read request to the main storage device, the host bus control means reads data from the main storage device to read the I / O data.
Means for transmitting the read data to the O bus control means, and the host bus control means transmits the I / O to the main storage device when the access request is a write request to the main storage device. It is characterized by having means for writing data from the bus control means.

Further, when the access request is a read request to the main storage device, the I / O bus control means includes means for transmitting data transmitted from the host bus control means to the I / O bus. When the access request is a write request to the main storage device, the I / O bus control means fetches the data sent to the I / O bus and sends the data to the host bus control means. It is characterized by having means for performing.

According to the present invention, a virtual storage system is adopted, a central processing unit, a main storage unit, a host bus connecting these central processing units and the main storage unit, the virtual storage system and the main storage unit. An I / O bus having a unique address space different from each address space of the storage device, and an I / O connected to the I / O bus and having an input / output device under the I / O bus
A data processing method in a data processing system including an I / O adapter, the method comprising: converting an address output on the I / O bus into a virtual memory address in response to a request from the I / O adapter; Making an access request to the main storage device using the converted virtual storage address in response to a request from the I / O adapter; and responding to the access request from the I / O bus control device. A data processing method is provided, comprising: converting a storage address into a physical address of the main storage device; and accessing the main storage device using the physical address.

The operation of the present invention will be described. In response to the request from the I / O adapter, the I / O bus bridge, which is the I / O bus control means, converts the address output to the I / O bus into a virtual storage address, and converts the virtual storage address after the conversion. By converting the address into the physical address of the main storage device in the host bus bridge as the host bus control means, data transfer in different address spaces can be dealt with at high speed and flexibly.

[0026]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of an embodiment of the present invention, and the same parts as those in FIGS. In FIG. 1, a CPU 1 and a main storage device 2 are connected to a host bus 3, and each of a plurality of I / O adapters 10-1 to 10-3 has an I / O device under its control. It is connected to a bus 9. A host bus bridge 4 and an I / O bus 9 are connected between the host bus 3 and the I / O bus 9.
An O bus bridge 7 is provided. This data processing device employs a virtual storage system, and the relationship among the virtual storage address space, the physical address space of the main storage device, and the address space of the I / O bus is as shown in FIG. It is assumed that

Data transfer requests from the I / O adapters 10-1 to 10-3 are transmitted to the I / O bus bridge 7 via the I / O bus 9. The I / O bus bridge 7 arbitrates (arbitrates) requests for the I / O bus 9, and gives the right to use the bus to the I / O adapter with the highest priority.
The I / O adapter given the right to use the bus outputs a command and an address on the I / O bus 9 and, if the data transfer is a write, outputs write data. The I / O bus bridge 7 inputs an address on the I / O bus to the ADT 8 which is an address conversion means, and obtains a virtual memory address as an output of the ADT 8.

The I / O bus bridge 7 sends the main storage device 2 to the host bus bridge 4 using the obtained virtual storage address.
Request access. Host bus bridge 4 is TLB
5 is used to convert the virtual storage address sent from the I / O bus bridge 7 into a physical address. Further, the host bus bridge 4 accesses the main storage device 2 using the converted physical address. If the request from the I / O bus bridge 7 indicates a write to the main storage device 2,
The data received from the I / O bus bridge 7 is written into the main storage device 2, and if a request from the I / O bus bridge 7 indicates a read from the main storage device 2,
Is returned to the I / O bus bridge 7.

When the request from the I / O adapter is a read from the main storage device 2, the I / O bus bridge 7 transfers the read data from the main storage device 2 returned from the host bus bridge 4 to the I / O bus 9. Output to Requester I /
The O adapter takes in the read data into its own device.

Referring to each part in FIG. 1, reference numeral 1 denotes a CPU (central processing unit) for executing a program, and 2 denotes a main storage device, which stores control information such as programs, data, and channel programs. Reference numeral 4 denotes a host bus bridge which includes a TLB 5 and an I / O processor 6 therein.
The CPU 1, the main storage device 2, and the host bus bridge 4 are connected by the host bus 3 to exchange data. TL
B5 converts the virtual storage address into a physical address of the main storage device. The I / O processor 6 is a microprocessor that controls I / O processing controlled by a microprogram. The I / O processor 6 receives an I / O signal from the CPU 1
The channel program stored in the main storage device is read and executed based on the instruction by the O instruction. The channel program is prepared by the operating system (OS) before issuing the I / O instruction.

Reference numeral 7 denotes an I / O bus bridge, which internally includes an address conversion table ADT8. ADT8 is I /
Information for converting the address output on the O bus 9 into a virtual storage address is stored. Reference numeral 9 denotes an I / O bus, which includes an I / O bus bridge 7 and I / O adapters 10-1 to 10-3.
And connect. The address space on the I / O bus has its own address space different from the address space on the host bus and the virtual address space. Each I / O adapter has an input / output device under its control, and controls device-specific functions. The host bus bridge 4 and the I / O bus bridge 7 are connected by a unique interface.

Next, the virtual storage system will be described. The virtual storage system is a mechanism for showing a program a memory space larger than a main storage device actually existing. For example, in a computer system having a main storage device of only 256 MB (megabyte), a program is virtually provided with a memory space of 1 GB (gigabyte). The substance of the data arranged in the virtual storage space is stored in a high-speed external storage device such as a disk array device. The virtual storage space is divided into fixed sizes called pages, and where each page is stored in the external storage device is managed by the OS. Pages required to execute the storage program (pages in which the program itself exists and pages in which data are arranged) are loaded from the external storage device to the main storage device by the OS.

The space actually allocated for program execution is even less than the maximum capacity of main storage. For example, if the main storage device actually allocated for executing the program is 4 MB and the page size is 4 KB (kilobytes), up to 1024 pages can be stored in the main storage device. In addition, when page 1025 is needed,
A page that has already been loaded into the main storage device and a page that is newly needed are exchanged. One of the pages in the main storage is written to the external storage, and a new page is loaded into an empty area of the main storage. These page replacement processes are not recognized by the program, and are all performed by the OS.

Pages are guaranteed to be contiguous on a virtual memory address. That is, the last byte of the page +
One byte address is the address of the next page. However, on a physical address, it is not guaranteed that consecutive pages are arranged at consecutive physical addresses. While the program performs memory access to the virtual storage space at a virtual storage address, the hardware of the computer system must access the main storage device at a physical address. Therefore, it is necessary to convert a virtual storage address to a physical address.

The mechanism for performing this conversion at high speed is TLB
It is. The TLB holds a pair of a virtual storage address and a corresponding physical physical storage device address. For example, if there are 32 pairs, there will be a conversion table for 32 pages. Since the relative byte position from the top of the page is the same for the virtual storage space address and the main storage device physical address, it is not necessary to store the relative address inside the page (that is, the lower 12 bits of the address) in the TLB. Absent.

When the program accesses the memory, the hardware compares the virtual storage address used for the memory access by the program with the virtual storage address stored in the TLB. If there is a match, the hardware compares the virtual storage address (called a TLB hit). ), And accesses the main storage device 2 by using the corresponding physical address. If there is no matching virtual storage address (referred to as a TLB miss), I
An interrupt occurs in the microprogram of the / O processor 6, and the microprogram replaces the contents of the TLB. This replacement is performed as follows.

The microprogram invalidates any pair of TLBs (called entries). The physical address is calculated from the virtual memory address accessed by the program and written to the invalidated entry. The hardware refers to the TLB again using the virtual storage address accessed by the program. Since the replacement has already been performed by the microprogram, a match is found and the main storage device is accessed. In order for the microprogram to calculate the main storage device physical address from the virtual storage address, it is necessary to refer to various correspondence tables stored in the main storage device, but this embodiment will not be described in detail.

The description of this embodiment will be made under the following assumptions. That is, 16 GB (234 bytes) of virtual storage space,
Main memory capacity 256 MB (228 bytes), page size 4K
B (4096 bytes).

Next, the operation of the I / O bus 9 will be described. The I / O bus 9 in FIG. 1 includes a set of 32-bit data lines and other control signal lines. The address is shared with the data line and defines a 4 GB address space. Registers inside each I / O adapter are mapped to its address space. That is, when the I / O processor 6 sends a command to the I / O adapter 10-1,
Corresponds to the command register of I / O adapter 10-1 (I
A command is sent to the I / O bus bridge 7 by specifying an address (on the / O bus).

In order to perform data transfer with the main storage device 2, I
The I / O adapter 10-n uses an address space defined on the I / O bus 9, not a physical address or a virtual memory address. Therefore, in order to perform data transfer, it is necessary for hardware to convert an address on the I / O bus 9 into a physical address. The conversion means for performing this conversion is ADT8. This conversion is performed through the following two steps. That is, in the first stage, the conversion from the I / O bus address to the virtual storage address is performed, and in the second stage, the conversion from the virtual storage address to the main storage device physical address. The details of these address conversion operations will be described in the following operation description.

In the description of this embodiment, the correspondence between the virtual storage address space visible from the program, the physical address space of the main storage device, and the address space of the I / O bus is as shown in FIG. 2 as described above. It is assumed that In the following description, an address is represented by a hexadecimal number unless otherwise specified. In other words, the channel program
The data area is located at address 020100000 (physical address 00010000), and the data area is 9 KB starting from address 00FF0000 (address 000A0000). The data area is I
It is mapped to three pages from the memory space 03620000 of the / O bus.

Next, the operation of the embodiment of the present invention will be described. The CPU 1 executes an OS and a program. FIG.
As shown in the flowchart, when the program issues an I / O request (step S1), the OS generates a channel program (step S2) and stores it in the main storage device 2 (step S3). Next, the first byte address storing the channel program is written to a predetermined address (referred to as a channel program pointer) of the main storage device 2 (step S4), and an interrupt is issued to the I / O processor 6 (step S4). S5). This interrupt is issued by the CPU 1 as a transaction on the host bus, and the I / O
O processor 6 receives it.

Next, the format of the channel program will be described with reference to FIG. The channel program 102 is stored in the main storage device 2 and includes a 16-byte header portion and a 16-byte channel command entry portion. The header portion includes an I / O bus bridge number, an I / O adapter number, and a device number, which are information for specifying a device to be subjected to an I / O operation.

The channel command entry is composed of four parts. A command for instructing the device or the I / O adapter to operate, a flag indicating whether there is a subsequent command, a byte count of data to be transferred, and a virtual storage address of the data. When the data transfer is a read (transfer in the direction from the device to the main storage device), the virtual storage address of the data indicates the first byte position of the area in which the data is written by an address on the virtual storage. When the data transfer is a write (transfer from the main storage device to the device), the first byte position of the area from which data is read is indicated by an address on virtual storage.

It is possible to chain two or more channel command entries as needed. The state in which channel command entries are chained is called a command chain. For example, such a usage as a command chain of a channel command entry for reading or writing data following a channel command entry for setting a mode of a device is possible.

In the example of FIG. 4, the channel program pointer is stored at the physical address 0000 0100. I
Referring to FIG. 5 showing the operation flow of the / O processor 6, upon receiving an interrupt from the CPU 1 (step S11), the / O processor 6 reads the address 0000 0100. I / O processor
6, the channel program pointer contains both the virtual storage address where the channel program is located and the physical address of the storage device corresponding to the channel program pointer. I / O processor 6 is 0000 010
Address 0 is read, and the position where the channel program is stored is known (step S12). In this embodiment, the head address of the channel program is set to the physical address 0001
The description will be made assuming that the address is 0000 and the virtual memory address is 02010 0000.

The I / O processor 6 refers to the channel program pointer 101 to read the channel program from the physical address 0001 0000 at 16 bytes. 00001 00
Information for specifying a device is stored at addresses 0C to 0001000F, and the I / O processor 6 can know the target of the I / O operation based on this information (step S).
13).

Next, the I / O processor 6 reads consecutive 16 bytes from address 0001 0010. Next, the command is analyzed (step S14), and it is determined whether or not the command requires data transfer. For example, in the case of a command for instructing device initialization, data transfer is not required because it is not necessary. In the case of a command requiring data transfer (step S15), 5 bytes from address 0001 0014 become a virtual storage address indicating a data area. In this example, a description will be given on the assumption that the virtual storage address of data is 00FF0000 and the physical address of the main storage device is 000EE000. The I / O processor 6 has a virtual memory address of 00FF0 0000
To obtain the corresponding physical address 000EE000,
The obtained result is registered in the TLB 5 (step S16).

Here, the configuration of the TLB 5 will be described with reference to FIG. FIG. 6 mainly shows functional blocks of the host bus bridge 4, 5-2 is a virtual memory address array for storing virtual memory addresses, and 5-1 is the physical memory of the main memory device paired with 5-2. This is a physical address array that holds addresses. 5-1 and 5-2 contain 32 entries. I / O
Processor 6 sets the upper 22 bits of the virtual memory address to 5-2
Write the upper 20 bits of the physical address to 5-1. The entry to be written is, for example, entry # 3. That is, 00FF00 (in binary notation, 0000 is assigned to # 3 of 5-2)
001111111100000000), 000A0 is written in 5-1 respectively.

The comparison circuit 5-6 is provided with an address buffer 4-30.
Is compared with the virtual memory address array 5-2, and together with the hit determination circuit 5-5, a so-called TLB hit or mishit is determined. Each buffer 4-
Reference numerals 30 to 4-33 store addresses, write data, control information, and reply data, respectively.

Next, the I / O processor 6 adds the byte count stored in 2 bytes from address 10012 and the virtual storage address of the data, and checks whether the data area exceeds the page boundary. In this example, the byte count will be described as 9 KB, that is, 2400 (h). Since the byte count is 2400 (h), the data transfer is performed over three pages. In other words, the virtual memory addresses 00FF0 0000, 00FF0 1000, 00
Referring to three pages starting from FF0 2000, the last byte is 00FF0 23FF.

On the other hand, description will be made assuming that physical memory addresses corresponding to these virtual storage addresses are set as shown in FIG. That is, in the physical address space,
The first page is 4 KB starting at 000A 0000, the second page starts at 000A 2000, and the last page starts at 000A 4000. As can be seen from the address, each page is not arranged consecutively in the physical address space.

Also, 00ff0 0000 of the virtual memory address space
Are mapped consecutively to an area starting from address 00362000 in the I / O bus space. I / O
When the processor 6 performs transfer over two or more pages,
The address pair corresponding to the next page is written to entry # 4 of virtual memory address array 5-2. That is, this 5-2
00FF01 for entry # 4 of 5-1 and 00 for entry # 4 of 5-1
Write A2. At this point, the third page is not set in the TLB.

Next, the I / O processor 6 sets the conversion means ADT8 in the I / O bus bridge. The operation of the ADT 8 will be described with reference to FIG. As described above, the I / O adapter 10-n performs data transfer using the address of the I / O bus 9. The ADT 8 operates to convert an address on the I / O bus to a virtual memory address. First, the I / O processor 6 performs mapping between the virtual storage address of the data area and the I / O bus address (step 17). Virtual memory address 00FF0 0000 ~
00FF0 9KB of address 23FF is set to 00 of the address on the I / O bus.
An example in which mapping is performed from addresses 36 2000 to 0036 43FF will be described.

8-1 in FIG.
The I / O adapter 10-1 has an entry for each I / O adapter.
Write 0FE9B, which is the difference between address FF00000 and address 00362000. Since the relative addresses in the page of 4 KB are the same, it is not necessary to hold the address of the lower 12 bits in 8-1. This calculation is performed by a microprogram of the I / O processor 6, and writing to 8-1 is performed using the signal line 7-5 via the I / O bus bridge 7.

Next, the I / O processor 6 assigns the command extracted from the channel command entry, the I / O bus address and the byte count to the I / O adapter indicated by the I / O bus bridge number and the I / O adapter number. The device number is sent (step S18). The command sent to the I / O adapter is converted by the I / O processor 6 into a command corresponding to a device under the I / O adapter (for example, a SCSI command format for a disk). The above commands, addresses, byte counts and device numbers are I / O
The data is written from the processor 6 to the register of the I / O adapter 10-1 via the I / O bus bridge and the I / O bus 9. I /
The register of the O adapter 10-1 is mapped in advance in the address space of the I / O bus, and is information known to the I / O processor 6.

Next, the operation of the I / O bus bridge 7 will be described with reference to FIGS. I / O adapter 10
-1 analyzes the command when there is a write from the I / O processor 6, activates the device, and prepares for data transfer. In this embodiment, a device read operation (transfer in the write direction from the device to the main storage device 2) will be described as an example.
When reading data from the device, the I / O adapter 10-1 issues a write request to the I / O bus 9. At this time, the address outputted on the bus outputs 00362000 which is the address of the address space of the I / O bus.

When there is a request (step S21),
The I / O bus bridge 7 arbitrates the request by the bus arbitration control circuit 7-1 (step S22), and takes the address from the I / O bus 9 into the buffer 7-10 (step S2).
3). The request ID queue 7-2 stores information on which I / O adapter is using the bus. Adds 8FB to the fetched address 0036 2000 and adds 0FB9E stored in 8-1
And store the result in register 8-3. At the time of this addition, 0 is complemented by the lower 12 bits of the value of 8-1. Which entry of 8-1 is used is determined by the contents of the queue 7-2. The result of the addition is the virtual memory address 00
The address becomes FF0000 and this address is sent to the host bus bridge 4 via the register 8-3 and the interface control circuit 7-3.

7-10, an address buffer, 7-11, a control buffer, 7-12, a write data buffer, 7-13.
Is a reply data buffer, and 7-14 to 7-17 are registers corresponding to these buffers.

Next, the operation of the host bus bridge 4 will be described with reference to FIGS. The virtual memory address sent from the I / O bus bridge 7 is transferred from the line 4-40 to the buffer 4-30.
(Step S31). Then, the comparison circuit 5-
In step 6, the contents of the buffer 4-30 and the contents of the virtual memory address array 5-2 are compared (only the upper 22 bits are to be compared) (step S32). The virtual memory address array 5-2 has 32 entries, but is compared simultaneously by 32 comparators to speed up the processing (step S33). One of the comparators is a comparison circuit 5-6. As a result of comparison, 0FF00 stored in entry # 3 matches (hits).

Then, the contents (000A) of the physical address array paired with entry # 3 are read (step S3).
4), concatenated with lower 12 bits of register 4-30, 00
The address 0A 0000 is accessed (step S35). When the channel command entry is a read command, the write data is sent to the I / O adapter 10-1, the I / O bus 9, and the write data buffers 7-12 and 4-31, and written into the main storage device 2.

When the first request is completed on the I / O bus, the I / O adapter 10-1 issues requests one after another. Since one transaction on the I / O bus is issued in units of 32 bytes, the address output by the I / O adapter 10-1 to the I / O bus 9 is increased by +32 bytes for each request. Until the address of the I / O bus 9 is 0036 2FE0, entry # 3 of the virtual memory address array is hit, and 003630
Entry # 4 hits up to addresses 00-0036 3FE0.

When the address of the I / O bus becomes 036 4000, the virtual memory address becomes 00FF0 2000, and there is no match in the virtual memory address array 5-2. 6 is sent an interrupt (step S36). Then, the operation is temporarily stopped (step S37), and an operation restart instruction from the I / O processor 6 is waited (step S38).

The microprogram of the I / O processor 6 has a virtual memory address 00FF as shown in the flow chart of FIG.
0 The main memory physical address of 2000 is calculated and written to the entry # 3 of the virtual memory address array 5-2. After that, the control circuit (not shown) of the host bus bridge instructs a retry of the address comparison. In the address comparison after the redo, the entry # 3 hits, so that the main memory can be accessed thereafter. Therefore, the restart of the operation to the TLB 5, that is, the restart of the operation to the host bus bridge 4 is instructed. The above processing corresponds to steps 41 to S in FIG.
Indicated at 44.

The above description is for the case where the channel command entry is a device read. However, the address processing is the same in the case of a channel command entry device write (data flows from the main storage to the I / O adapter). . The difference is that the data read from the main storage device is sent to the I / O bus 9 through the reply data buffer 4-33 in FIG. 6 and the reply data buffer 7-13 in FIG.
Eventually, it is written to a device under the I / O adapter 10-1.

The above example shows the case where the data transfer starts from the first byte of the data area, but one of the features of the present invention is that it can cope with out-of-order transfer. In the case of out-of-order, data transfer does not always start from the first byte address as described above. For example,
In the above example, the data transfer is performed using the address 0036 of the I / O bus.
An example will be described in which the address starts from the address 4000 and the virtual memory address 00FF0 2000. In this case, the I / O processor 6 is interrupted without hitting the entries # 3 and # 4 of the TLB 5-2 set prior to the transfer.

In response to this interrupt, as shown in FIG. 10, the I / O processor 6 calculates the physical address corresponding to the address 00FF02000 and writes it to entry # 5. Then, the address of the subsequent data transfer is entry # 5 of 5-2.
To hit. The transfer is performed on the I / O bus address 0036 43E0
When the address reaches (virtual storage address 00FF0 23E0), even if the address returns to, for example, 00362000 (0FF00000), since the valid address pair is already set in entry # 3 in 5-2, the data is The transfer can be continued. When the transfer of all data is completed, the I / O processor 6 reports the completion to the OS (reporting means is not shown).

In the present embodiment, the address conversion means 5
In the example described above, the TLB 5 and the I / O processor 6 are provided in the O-bridge 7 and the I / O processor 6 is provided in the host bus bridge 4. However, in principle, the I / O processor 6 is located at an independent position connected to the host bus. It is obvious that there may be. As another embodiment of the present invention, as shown in FIG. 11, an example in which an I / O cache 12 is mounted on the host bus bridge 4 to further speed up data transfer can be considered.

[0070]

The first effect is that an I / O bus subsystem having a unique address space can be incorporated into a computer system. The reason is that a part of the virtual memory address can be dynamically mapped in the address space of the I / O bus.

A second effect is that data can be transferred out-of-order even when a channel program including a virtual memory address is executed. The reason is that a two-stage address conversion is performed in which the address of the data is converted from the address of the I / O bus to the virtual storage address and further converted to the physical address of the main storage device by the TLB.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing a relationship between address spaces.

FIG. 3 is a flowchart showing the operation of the OS of the CPU 1;

FIG. 4 is a diagram illustrating an example of a channel program and address mapping.

FIG. 5 is a flowchart showing an operation of the I / O processor 6;

FIG. 6 is a configuration diagram of a host bus bridge.

FIG. 7 is a configuration diagram of an I / O bus bridge 7.

FIG. 8 is an operation flow chart of the I / O bus bridge 7.

FIG. 9 is an operation flowchart of the host bus bridge.

FIG. 10 is an operation flowchart of the I / O processor at the time of a TLB mishit;

FIG. 11 is a configuration diagram of another embodiment of the present invention.

FIG. 12 is a block diagram illustrating an example of a conventional technique.

FIG. 13 is a block diagram showing another example of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CPU 2 Main storage device 3 Host bus 4 Host bus bridge 5 TLB 6 I / O processor 7 I / O bus bridge 8 Address conversion part (ADT) 9 I / O bus 10-1 to 10-3 I / O adapter

Claims (6)

[Claims] A virtual storage system is adopted, a central processing unit, a main storage unit, a host bus connecting these central processing units and the main storage unit, and each of the virtual storage system and the main storage unit. A data processing system comprising: an I / O bus having a unique address space different from an address space; and an I / O adapter connected to the I / O bus and having an input / output device under control of the I / O bus. First address conversion means connected to a bus for converting an address output on the I / O bus into a virtual memory address in response to a request from the I / O adapter; Means for making an access request to the main storage device using the virtual storage address converted by the first address conversion means in response to the request. Second address translation means connected to the host bus for translating the virtual storage address into a physical address of the main storage device in response to an access request from the I / O bus control device; Means for accessing the main storage device by using a host bus control means,
A data processing system comprising: 2. The host bus control means, when the access request is a read request to the main storage device, reads data from the main storage device and sends the read data to the I / O bus control means. 2. The data processing system according to claim 1, further comprising a sending unit. 3. The host bus control means includes means for writing data from the I / O bus control means to the main storage device when the access request is a write request to the main storage device. The data processing system according to claim 1 or 2, wherein: 4. The I / O bus control means, if the access request is a read request to the main storage device, sends data sent from the host bus control means to the I / O bus control means.
4. A data processing system according to claim 2, further comprising means for sending data to an I / O bus. 5. The I / O bus control means, when the access request is a write request to the main storage device, fetches the data sent to the I / O bus and sends the data to the host bus control means. 5. The data processing system according to claim 2, further comprising a sending unit. 6. A virtual storage system is adopted, a central processing unit, a main storage unit, a host bus connecting these central processing units and the main storage unit, and each of the virtual storage system and the main storage unit. A data processing method in a data processing system including an I / O bus having a unique address space different from an address space, and an I / O adapter connected to the I / O bus and having an input / output device under control thereof, In response to a request from the I / O adapter,
Converting the address output on the I / O bus into a virtual storage address; and responding to a request from the I / O adapter, using the converted virtual storage address to request access to the main storage device. Converting the virtual storage address to a physical address of the main storage device in response to an access request from the I / O bus control device; and accessing the main storage device using the physical address. And a data processing method.