JPH11275081A - Atm system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce jitters of a SYNC event signal. SOLUTION: This asynchronous transfer mode(ATM) system, including a waveform equalizer that applies waveform equalization of a received serial transmission code attenuated by a transmission line and a PLL circuit that generates a clock signal synchronously with received data which are waveform- equalized by the waveform equalizer, is provided with a SYNC event generating circuit 18 that frequency-divides an output signal of the PLL circuit in a PMD section for generating a SYNC event signal, so as to reduce the jitters by the use of a stable received recovery clock signal for generating the SYNC event.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nous transfer mode (asynchronous transfer mode) device and a technique for improving a TC (Transmission Convergence) sublayer in the device.

[0002]

2. Description of the Related Art The specification of ATM technology is carried out by The ATM Forum established in the United States. In Ethernet, since a plurality of LAN nodes share one transmission medium, the more LAN nodes, the more LAN
The bandwidth that can be used per node (the width of the transmission rate at which information is transmitted) decreases, and the overall throughput drops sharply when many nodes are trying to transmit almost simultaneously. On the other hand, a LAN in which the ATM technology is introduced (referred to as an ATM-LAN) allows the bandwidth to be freely changed even during communication, from low-speed communication and communication with a small amount of information to high-speed and high-bandwidth communication. ATM that can do
An exchange technique is introduced, and transmission and reception are performed in a one-to-one correspondence, thereby achieving ultra-high-speed transfer with improved throughput.

[0003] Examples of documents describing ATM devices include "The ATM Forum Technical Committee Physic."
al Specification for 25.6Mb / s over Twisted Pair ca
ble ”.

[0004]

The bit rate 25.5
In the TC sublayer (referred to as TC section) of the Mbps ATM device, a PMD sublayer (referred to as PMD section)
After the received clock signal is reproduced, the signal is transmitted to the TC unit. The received data (Rxdata) is scrambled data, and is transmitted to the TC unit after the sub-layer has equivalently reproduced the received clock signal. The received data is scrambled bit-serial data, and is obtained with 5 bits and 1 symbol.
It consists of 16 types of data and escape codes.
In the TC section, first, after the NRZI conversion is performed by the NRZI decoder, an escape code X_X for searching for the head of the ATM is detected. When the X_X code is detected, the cyclic data of the descrambler is reset, and thereafter, the data is divided into 5-bit data and converted into 4-bit parallel data. This 4
The bit parallel data is decoded by a descrambler, converted into 8-bit parallel data by an octet interface controller, and transmitted to an upper layer.

[0005] However, the bit rate is 25.5 Mb.
ps ATM device is different from 155Mbps etc.
Does not have a frame structure. To synchronize cells,
Use escape codes that use special bit strings. That is, in an ATM device having a bit rate of 115 Mbps or the like, a frame having a bit stream time of 125 μS is continuously transmitted as shown in FIG. However, in the case of an ATM device having a bit rate of 25.5 Mbps, as shown in FIG. 8, the bit frame has a period without data (indicated by 81). Competition is synchronized based on the provided escape code.

[0006] There are three special escape codes, X_X, X_4 and X_8, which indicate the beginning of a cell.

Among them, X_X and X_4 are synchronization signals indicating the beginning of a cell, and start of operation of the TC unit and reset of the descrambler periodically. X_8 is used for an upper layer synchronization signal. Generally, the period of the SDH frame structure is used as the synchronization signal 125 μS. Since this signal is used as a synchronizing signal of the audio signal, stable operation is essential.

[0008] An escape code of X_X or X_4 is always added to the head of the cell, and when there is no data to be transmitted (the period indicated by 81 in the figure), only random data having no meaning is transmitted. X_8 is issued irregularly by a request signal from an upper layer. At some point, it is inserted in the middle of a valid cell, and at some point, it is inserted when there is no valid cell. If there is no valid cell, indicate the beginning of the cell
Since X_X does not come, the state where reset is not applied continues for a long time. At this time, if a bit error occurs and an error occurs in the octet alignment (separation of 5-bit symbols), X_8 cannot be decoded correctly thereafter. Further, the transmission request of X_8 is a request from the upper layer and is an asynchronous signal from the TC unit, so that a shift of up to one symbol (5 bits) occurs. Due to the shift, the SYNC event signal on the receiving side becomes a signal having large jitter, and as a result, the stability of the system is reduced.

An object of the present invention is to reduce the jitter of a SYNC event signal.

[0010]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application.

That is, a waveform equalizer (223) for equalizing the waveform of the received serial transmission code attenuated by the transmission line, and a clock signal synchronized with the received data waveform-equalized by the waveform equalizer are generated. A including the PLL circuit (23)
When a TM device is formed, a SYNC event generation circuit (18) is provided for dividing a PLL circuit output signal in the PMD section to form a SYNC event signal.

According to the above means, the SYNC event generation circuit divides the frequency of the output signal of the PLL circuit in the PMD section to form a SYNC event signal. Since the output signal of the PLL circuit is a received and recovered clock and is stable, the frequency of the signal is divided to form a SYS event signal, thereby reducing the jitter of the SYNC event signal.

An HEC check unit for detecting a header error, and a FIFO unit for outputting an output signal of the HEC check unit to the ATM unit in a first-in first-out manner in synchronization with a clock signal output from the ATM unit. When the ATM device is configured to include the above, the SYNC event generation circuit may synchronize the frequency of the output signal of the PLL circuit with the reception clock signal output from the ATM unit.

[0014]

FIG. 3 shows a configuration example of an ATM-LAN adapter card. ATM-L shown in FIG.
The AN adapter card 200 is an IC card such as a PC
MCIA (Personal Computer Memory Card Internatio)
and is configured as an example of an ATM-LAN interface circuit. The ATM-LAN adapter card 200 is a firmware in which a microprocessor 202, a microprogram, and the like, which are individually integrated in a semiconductor integrated circuit, are stored on a card substrate 201 on which required wiring is provided on the front surface or the back surface. ROM 20
3. RAM2 as work area for microprocessor
04, RAM unit 20 used for ATM unit 205, TC unit 208, transmission data buffer, reception data buffer, etc.
6. The PMD unit 9 as a physical layer control chip and the filter transformer 207 are mounted and configured.

The filter transformer 207 is connected to a transmission line such as a twisted pair line. The filter / transformer 207 is integrated into one chip including an output resistor, a filter and a transformer.

The ATM unit 205 is coupled to a terminal device such as a personal computer with an interface specification conforming to the PCMCIA standard. And the ATM unit 2
Reference numeral 05 denotes a cell formed from data supplied from the terminal device through scramble and coding processes, multiplexed, and passed to the PMD unit 9. Also, the ATM unit 205
When the information received by the D unit 9 is received, the destination header is confirmed, and the cell is decomposed and decoded. ATM
The control of the unit 205 is performed by the microprocessor 202 according to a program stored in the ROM 203. The microprocessor 202, ROM 203, RAM 204,
The ATM unit 205 and the TC unit 208 function as means for controlling an ATM-LAN transmission protocol.

Although the PMD unit 9 is not particularly limited,
It is formed on one semiconductor substrate such as a silicon substrate.
s satisfies the transmission signal waveform defined in the template for the physical layer for the ATM-LAN, and the transmission signal from the transformer in the transformer filter 207 has a zero-to-peak as defined in the template. Satisfies a signal amplitude of about 2V. Thereby, the power consumption of the PMD unit 9 can be suppressed to, for example, about 200 mW. The PMD unit 9 is an ATM-LAN adapter card 200
It is the circuit part that consumes the largest amount of power.

FIG. 1 shows an example of the configuration of the TC section 208.

As shown in FIG. 1, the TC unit 208
NRZI decoder 14, bit conversion (5B4B) circuit 15, ESC detection circuit 16, descrambler 17,
A SYNC (sink) event generation circuit 18 and an HEC check circuit 19 are included.

The NRZI decoder 14 performs NRZI (Non-Return to Zero) conversion on the received serial transmission code. This converted output is transmitted to the bit conversion circuit 15 at the subsequent stage.
In the bit conversion circuit 15, the input NRZI conversion signal (received serial data) is grouped into 5-bit symbols and converted into 4-bit data corresponding to the symbols. The bit conversion circuit 15 determines the octet alignment when the escape code indicating the head of the cell is detected by the ESC detection circuit 16, and thereafter converts the octet alignment into 5-bit data and converts it into 4-bit data.

The ESC detection circuit 16 has an escape code
(X_X, X_4, X_8) is detected. When X_X is detected, a signal for resetting the cyclic data (PRING) of the subsequent descrambler 17 is output.

The descrambler 17 descrambles 4-bit parallel data and converts it into 8-bit parallel data. When the escape code X_X is detected, the cyclic data (PRING) is reset.

Although not particularly limited, the SYNC event generation circuit 18 divides the reception reproduction clock signal output from the PLL (face locked loop) circuit in the PMD section 9 by 1/4000 as shown in FIG. Divide 8
Generate a KHz SYNC event signal.

One byte of C included in the first five bytes of the cell
The RC (Cycle Redundancy Check: header error control) is adopted, and the HEC check circuit 19 detects this header error, and if a header error occurs, discards the cell.

The cells for which no error has been detected by the HEC check circuit 19 are rate-converted by the FIFO unit (first-in first-out) 20 at the subsequent stage and transmitted to the ATM unit 205.

The FIFO unit 20 belongs to the UTOPIA interface, and may be formed in the ATM unit 205.

FIG. 4 shows an example of the configuration of the PMD unit 9.

The PMD unit 9 includes, but is not limited to, a transmitting circuit 10 and a receiving circuit 11, and includes a pair of transmitting terminals TxA and TxB, a pair of receiving terminals RxA and RxB, Output terminal RxDATA,
Data input terminal TxDATA, clock signal input terminal T
xCLK, and a clock signal output terminal RxCLK.
As the external power supply terminal, a terminal to which the power supply voltage Vdd such as 3.3 [V] is supplied and a terminal to which the ground potential Vss such as 0 [V] is supplied are shown.

The transmission circuit 10 includes a flip-flop 25 such as a D-type latch, an output control circuit 20, and an output circuit 21. The output control circuit 20 and the output circuit 2
Reference numeral 1 denotes an output driver circuit 50 for transmission. The data input from the data input terminal TxDATA is latched by the flip-flop 20 in synchronization with the clock signal TxCLK, and the latched data is supplied to the output control circuit 20. The output control circuit 20 provides the output circuit 21 with a control signal according to the logical value of the data supplied thereto,
As a result, the output circuit 21 sets the terminal TxA to the power supply voltage V
At dd, the terminal TxB is driven to the ground voltage Vss, or the terminals TxA and TxB are driven to the opposite state.

The receiving circuit 11 included in the PMD unit 9 includes an input buffer 22, a PLL circuit 23, and an output latch 24. The receiving terminals RxA and RxB have resistors 220 and 2 respectively.
21, the bias voltage VB is supplied from the voltage follower circuit 222 to the receiving terminals RxA,
The signal input to RxB is subjected to waveform shaping by the waveform equalizer 223 on the transmission line.

The PLL circuit 23 includes a phase comparison circuit (P
C) 230, frequency comparator (FC) 231, signal detection circuit (E-Det) 232, selector (SEL) 234,
A charge pump (C-Pump) 235 and a voltage controlled oscillator (VCO) 236 are provided. Frequency comparator 231
Forms an error signal corresponding to the frequency difference between the clock signal input from the clock signal terminal TxCLK and the clock signal fed back from the voltage controlled oscillation circuit 236. The phase comparison circuit 230 forms an error signal corresponding to the phase difference between the input signal Din transmitted from the waveform equalizer 223 and the clock signal RxCLK fed back from the voltage controlled oscillation circuit 236. The signal detection circuit 232 detects whether an effective signal component is included in the output of the waveform equalizer 223, for example, based on the energy of the signal. Signal detection circuit 2
32 is a selector 234 when a valid signal is detected.
Select the output of the phase comparator 230, and when no valid signal is detected, the selector 234 causes the frequency comparator 23
1 is selected. The charge pump 235 generates a current according to the error signal output from the selector 234, and converts it into a predetermined voltage signal. The voltage controlled oscillation circuit 236 outputs a signal having an oscillation frequency corresponding to the voltage level of the voltage signal supplied thereto.

The PLL circuit 23 includes a waveform equalizer 223
Is not a valid signal, synchronization with the clock signal supplied from the clock signal terminal TxCLK is performed. Thereafter, when the output signal of the waveform equalizer 223 becomes valid, the phase pull-in is efficiently performed. Will be able to do it. When the output signal of the waveform equalizer 223 becomes valid, the output of the voltage controlled oscillator 236 becomes a clock signal synchronized with the output signal of the waveform equalizer 223. The data latch 24 is connected to the voltage controlled oscillation circuit 23.
In synchronization with the output clock signal of No. 6, the output signal of the waveform equalizer 223 is latched. As a result, the received data is output from the data output terminal RxDATA, and a clock signal synchronized therewith is output from the clock signal terminal RxCLK.

Further, in order to stabilize the operation irrespective of the decrease in the rate of change of the logic level of the input data, the output signal of the signal detection circuit 232 and the voltage control oscillation circuit 236 are used.
A gain controller (G-Cont) 237 is provided which takes in the output signal RxCLK of the PLL circuit 23 and the system clock signal SyCLK input from outside the PMD unit 9 and controls the loop gain of the PLL circuit 23 to be constant. That is, the gain controller 237 acts to increase the charge / discharge current of the capacitor included in the charge pump 235 when the rate of change in the logic level of the output signal of the signal detection circuit 232 is low, and thereby. This prevents loss of synchronization even when the rate of change of the logic level of the input signal to the PLL circuit 23 is low. Such an output signal RxCL of the PLL circuit 23
K is the NIZI decoder 4 shown in FIG.
It is transmitted to a SYNC event generation circuit 18 for forming a C event signal.

According to the above example, the following effects can be obtained.

(1) SY for dividing the output signal of the PLL circuit in the PMD section 9 to form a SYNC event signal
By providing the NC event generation circuit (18), S
Since a stable reception / reproduction clock signal can be used for YNC event generation, the jitter of the SYNC event signal can be reduced.

(2) Due to the operation and effect of the above (1), SY
Since the jitter of the NC event signal is reduced, the operation of the ATM-LAN adapter card 200 using such a SYNC event signal and the operation of a system including the same can be stabilized.

Although the invention made by the inventor has been specifically described based on the embodiments, the present invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say.

For example, as shown in FIG. 5, the reception clock signal RX at the interface with the ATM layer
A SYNC event signal synchronized with CLK may be formed. The FIFO unit 19 forms an interface with the ATM layer. The FIFO unit 19 takes in the reception clock signal RXCLK input as an operation clock signal into the SYSNC event generation circuit 18 and, as shown in FIG. Is synchronized with the reception clock signal RXCLK.

[0039]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the output signal of the PLL circuit in the PMD section is divided to form a SYNC event signal.
By providing a YNC event generation circuit and using a stable reception / reproduction clock signal for SYNC event generation,
The jitter of the NC event signal can be reduced.

[Brief description of the drawings]

FIG. 1 is an example of an ATM device according to the present invention.
FIG. 3 is a detailed configuration example block diagram of a TC unit included in the LAN adapter card.

FIG. 2 is an operation timing chart of a main part in the TC section.

FIG. 3 is a block diagram showing a configuration example of the ATM-LAN adapter card.

FIG. 4 shows the P in the ATM-LAN adapter card.
FIG. 3 is a block diagram illustrating a configuration example of an MD unit.

FIG. 5 shows T in the ATM-LAN adapter card.
It is another example block diagram of a structure of a C section.

FIG. 6 is an operation timing chart of a main part in the circuit shown in FIG. 5;

FIG. 7 is a bit stream timing diagram of a frame structure in a bit rate 156 Mbps ATM device.

FIG. 8 is a bit stream timing diagram of a frame structure in a bit rate 25.6 Mbps ATM device.

[Explanation of symbols]

 Reference Signs List 9 PMD unit 14 NRZI decoder 15 Bit line conversion circuit 16 ESC detection circuit 17 Disk RAM Buller 18 SYNC event generation circuit 19 HEC check circuit 201 Card board 202 Microprocessor 203 ROM unit 204, 296 RAM unit 205 ATM unit 208 TC unit

Claims (3)

[Claims] 1. A waveform equalizer for performing waveform equalization of a reception serial transmission code attenuated by a transmission line, and a PLL circuit for generating a clock signal synchronized with the reception data waveform-equalized by the waveform equalizer. An ATM device comprising: a SYNC event generation circuit that divides a circuit output signal of the PLL to form a SYNC event signal. 2. A waveform equalizer for performing waveform equalization of a received serial transmission code attenuated on a transmission line, and a PLL circuit for generating a clock signal synchronized with the received data waveform-equalized by the waveform equalizer. An ATM device comprising: a PMD unit comprising: a PMD unit disposed after the PMD unit; and a TC unit for processing an output signal of the PMD unit. SYN
An ATM device comprising a SYNC event generation circuit for forming a C event signal. 3. An HEC check section for detecting a header error and an output signal of the HEC check section synchronized with a clock signal output from the ATM section.
3. The ATM device according to claim 1, further comprising a FIFO unit for outputting the data in a first-in first-out manner, wherein the SYNC event generation circuit synchronizes the SYNC event signal with the reception clock signal.