JPH11274933A - Integrated circuit for supplying multiple output current - Google Patents

Abstract

PROBLEM TO BE SOLVED: To control the current value to be supplied to each driven element by increasing or reducing it and to simplify the constitution or control of a microprocessor, etc., by making every switching means, corresponding one-on-one to every driven element into a current synthesizing circuit, i.e., a connection body, where N pieces of unit switching parts having almost equal current capacitance are connected in parallel to each other. SOLUTION: A data shift register part 14 consists of (m) pieces of D flip-flops 14-1 to 14-m. The binary serial data which are fetched via a data terminal 14b, every time a single pulse of a 1st clock signal is added to a 1st clock terminal 14a, are shifted, and the area equivalent to one printed line are converted into a parallel form from 9 serial form. A latch circuit array part 15 consists of latching circuits(LAT) 15-1 to 15-m of flip-flops and primarily holds the contents of each digit of the part 14 by the latch synchronizing signal that is inputted to a latch terminal 15a. Then the correction data shift register parts 16 are shifted one by one.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit for supplying multiple output currents applied to various printers such as LED printer heads and thermal heads, and display devices such as plasma displays. The present invention relates to a multi-output current supply integrated circuit having a number of bits of a multi-gradation current output that enables correction of the gray scale current, and a drive control device that can use the same.

[0002]

2. Description of the Related Art A conventional LED printer driving circuit is shown in FIG.
As shown in FIG. 7, transmission and reception of various signals to and from the main frame 1 such as a computer that generates data signals and the like, and the LED printer head driving integrated circuit 3 and the correction code storage ROM 4 are executed based on the data signals and the like. Connected to the microprocessor 5 and the field effect transistors (FETs) of the output transistor array unit 6 of the LED printer head driving integrated circuit 3 in a one-to-one correspondence.
(Light emitting diode) and a LED array integrated circuit 7 having a large number of bits, and has a function of correcting variations in the amount of light emission of each LED.

When a data signal for one line printing is transmitted from the main frame 1 to the microprocessor 5, the microprocessor 5 transmits a control signal to the correction code storage ROM 4 and transmits the correction code data as reference data in the ROM 4. The correction data signal obtained by taking in and correcting the data for the one-line printing for each bit is indicated by an LED.
Shift register section 8 of integrated circuit 3 for driving printer head
For the least significant digit flip-flop (F / F). Here, the correction control is performed by correcting data for one line printing over three latch cycles so that printing on one LED (corresponding to one dot) is sequentially completed in three bits in a time-division manner. Are sequentially converted to.

For example, assuming that the light emission intensity of the leftmost LED in the LED array integrated circuit 7 shown in FIG. 17 is the lowest value as compared with the other LEDs, the correction control of the light emission time is as follows. It is done. At the address corresponding to the leftmost LED in the correction code storage ROM 4, for example, a correction code corresponding to the value 7 is stored in advance. When one-line data including data to be turned on from the main frame 1 to the left end LED is input to the microprocessor 5, the microprocessor 5 stores the control signal in the correction code storage ROM 4.
And a correction code data signal for one line including the correction code of the left end LED as a value 7 is taken in, and a serial 3-bit digital signal is sent to the shift register 8 as a correction data signal in response to the latch signal. Here, the printing process of the first line will be described with reference to FIG. 18. The data signal of the first line is converted into _{first to} third correction data signals l _{1 to} l ₃ in a block manner. First, when the first correction data signals l ₁ in synchronization with the clock signal are all stored in the shift register unit 8, of the first synchronization with the latch signal L ₁ from the microprocessor 5 correction data signals l ₁ Is taken into the latch array unit 9. Here, since bits corresponding to the first left LED of the correction data signals l ₁ is at the H level (active control level), the left end of the latch circuits by the latch signal L _l (L
AT) is maintained at the H level. With delivery of the first latch signal L _l, the microprocessor 5 sends an enable signal having a pulse width 4t to the output control circuit section 10. The output control circuit section 10 is composed of an array of an AND gate and a voltage level shift circuit (shown simply as AND in FIG. 17). The left end AND gate in the transmission period of the enable signal having a pulse width of 4t is the left end of the transistor array section 6. The ON control signal is continuously transmitted to the field effect transistor (FET). The left FET by the ON control signal is closed, the driving current is supplied from the power supply V _SS to the left end LED. Thereby, the left end LED emits light for a time 4t. During the transmission period of the enable signal having the pulse width of 4t, the second correction data signal l
₂ has already been sent to the shift register unit 8, and the correction data signal l ₂ in synchronization with the next latch signal L ₂ is taken into the latch circuit (LAT). At this time, the left end latch circuit (LAT) is the left end LE of the correction data signal l ₂
Since the bit corresponding to D is at the H level, the bit is also maintained at the H level. With delivery of the latch signal L _2,
An enable signal having a pulse width of 2t is sent to the output control circuit unit 10. This enable signal turns on the left end FET, and the left end LED emits light for a time 2t. In yet also sending period of the enable signal having a pulse width 2t, third correction data signals l ₃ has already been sent to the shift register unit 8, the latch signal L ₃ is corrected data signal l ₃ taken into the latch circuit It is. At this time, the left end latch circuit (LAT) is also kept at the H level. Next, along with the transmission of the third latch signal L ₃ , an enable signal having a pulse width t is transmitted to the output control circuit 10. This turns on the leftmost FET and causes the leftmost LED to emit light for a time t.

As described above, the enable signal has a pulse width of 4
The pulse is formed of triple pulses of t, 2t, and t, and each pulse is transmitted to the output control circuit unit 10 in synchronization with the latch signal. The data signal is internally converted into three consecutive correction data signals l _l , l ₂ and l ₃ so as to match the three consecutive pulses. In the above example, the left end LED intermittently participates in the total light emission time 7t (= 4t + 2t + t), but the correction data signals l ₁ , l ₂ , l ₃ generated by the correction code data stored in the correction code storage ROM 4. Therefore, in one-line printing, the total light emission time of each LED becomes seven stages.

[0006]

The above-described integrated circuit for driving a LED printer head has uneven printing caused by variations in light emission intensity of each LED and variations in current capacity (ON resistance) of each FET in the output transistor array unit itself. In order to eliminate (light amount unevenness or density unevenness), the total light emission amount is corrected to a standard amount by controlling the light emission time of each LED for a longer or shorter time. That is, FE takes three latch cycles.
The ON time of T is adjusted in seven steps, but one-line printing requires a printing period of three latch cycles.
Shorter latch cycles require shorter clock cycles, but have limitations. In order to increase the number of bits for one-line printing and to print in a short time, it is extremely difficult to cope with the above-described pulse width control time correction. Further, it is necessary to internally generate three consecutive correction data signals each time one line is printed so as to correspond to different pulse widths of the enable signal. Was accompanied.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problem, and an object of the present invention is not to equalize variations in the output intensity of a driven element such as an LED by adjusting the length of output time, but to make each driven One-line printing or display by controlling the current value to be supplied to each element to increase or decrease the output intensity of each driven element directly, while keeping the output time of each element constant Another object of the present invention is to provide a novel multi-output current supply integrated circuit that realizes a simplified configuration or control of a microprocessor or the like in addition to a reduction in the time required for the operation, and a drive control device for a large number of elements using the same.

[0008]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problem, an integrated circuit for driving an LED printer head having a large number of switching means for interrupting current supply from a power supply to each driven element such as an LED. In the multi-output current supply integrated circuit according to the present invention, the means taken by the present invention is a switching means corresponding to the driven element in a one-to-one correspondence, wherein a parallel connection of N unit switching parts having substantially the same current capacity as each other. As a current synthesis circuit.

The N unit switching units are divided into n groups, the number of unit switching units belonging to the i-th group is set to 2 ⁱ⁻¹ , and the switching control of all the unit switching units belonging to the i-th group is performed. The common input is connected to the i-th digit of the n-bit digital control signal. Here, n is a positive number equal to or less than N,

[0010]

(Equation 2)

The following relational expression holds.

The configuration example of the unit switching section may be a single field-effect transistor (FET) or a parallel connection of a plurality of adjacent field-effect transistors. It is desirable that the layout of the N unit switching units formed as the semiconductor integrated circuit has a parallel displacement array structure in which the unit switching units have the same shape and the same pitch. This parallel movement direction can be the channel length direction or channel width direction of the field effect transistor.

In the above-mentioned parallel-translation array structure of a large number of transistors, variations in transistor current capacity (ON resistance) due to the wafer process are inevitably manifested, but the correspondence between unit switching units and their group classification is optimized. This makes it possible to prevent a so-called level drop of the output current. As one of the measures, the unit transistor units belonging to the first group are positioned at the center of the parallel displacement array structure, and the unit switching units of the first group are set as the axis of symmetry. The unit switching units at positions away from each other by n → n−1 → n → n−2 → n → ... → n → 2 → n →.
... → n → n−2 → n → n−1 → n Correspond with each digit of the n-bit digital control signal so as to take a symmetrical group pattern in the following order.

On the other hand, another example of the configuration of the unit switching section is a parallel connection circuit of two or more field-effect transistors positioned symmetrically, and the field-effect transistors of the unit transistor sections belonging to different groups are connected to each other. A contiguous distributed array format is employed.

In this arrangement type, it can be considered that each group has a plurality of field-effect transistors branching in a tree shape at a hierarchical lower level. The type transistors are formed in a parallel-moving array structure having the same shape and the same pitch in one direction. Of course, the parallel movement arrangement direction can be set in the channel length direction or the channel width direction.

As described above, when viewed at the group level, that is, when viewed from the digital input side, in the transistor array having the tree structure, different measures are taken to prevent the level drop of the output current different from the above case. That is, the center of gravity (the average position of the unit switching unit) of two or more field-effect transistors belonging to the first group is placed at the center of the parallel displacement array, and the center of gravity is set as the axis of symmetry, and from the axis of symmetry to both ends of the array. In the direction away from each other, the center of gravity (average position) of two or more field-effect transistors in the unit transistor section belonging to the same group is n → n−1 → n → n−2 → n →. n → 2 → n → ・
... → n → n−2 → n → n−1 → n Correspond to each digit of the n-bit digital control signal so as to take a symmetrical group pattern in the following order.

Each of the switching means has a plurality of unit switching units having substantially the same current capacity.
In addition, one or two offset field-effect transistor units connected in parallel to these parallel connection units are provided.
The above is provided.

Further, a drive control device for a plurality of driven elements whose output intensity monotonously changes in accordance with the supplied current value, the drive control device including the multi-output current supply integrated circuit according to the above configuration is realized. The additional means includes a data latch means for receiving a data signal for driving a plurality of driven elements and latching the data signal, and a correction means for correcting the data signal and the data signal latched by the data latch means. And a corrected data generating means for generating a corrected data signal based on these data signals, and the corrected data signal is supplied to the current supply integrated circuit. Used as a control signal in the circuit. Of course, the drive control device according to this configuration can be realized as a semiconductor integrated circuit. Still further, in addition to the configuration of the drive control device, the external signal generation unit includes a data signal generation unit that generates a data signal for driving the plurality of driven elements, and an external signal generation unit that corrects the data signal. And a correction data signal generating means for generating a correction data signal used for

[0019]

According to the multi-output current supply integrated circuit having such a configuration, each driven element is connected to a current combiner in which N unit switching units are connected in parallel.
The output current composite value is not constant, and the N unit switching units are simultaneously turned on / off simultaneously, so that N output current values can be discretely obtained. Therefore,
Since the current supply value to a driven element such as one LED can be increased or decreased in N steps (N + 1 steps when the current supply value is zero), the active periods of all the driven elements are fixed. Meanwhile, the current supply value to each driven element can be individually given so that the output capability of the element matches the standard value, and the variation in the capacity between the driven elements and the variation in the current capacity between the switching means can be reduced. The output variation between driven elements based on the above can be corrected. Conversely, in one-line printing or one-line display, the density of a specific dot can be made different from that of other dots, and independent control of gradation printing or display for each dot becomes possible.

Of course, it is also possible to connect a switching control input to each of the N unit switching units to independently control each unit switching unit. In such a case, however, the control signal line of one switching means is connected Since there are N lines, there is no room for space in the circuit configuration and the semiconductor layout. Therefore, in order to minimize the number of control signal lines, the N unit switching units are divided into N groups, and the number of unit switching units belonging to the i-th group is reduced to 2 units.
a ^i-1, with a common switching control input of the unit switching unit belonging to the same group, to connect its input to the i-th digit of the n-bit digital control signal. In such a case, the relational expression of 2 ⁿ -1 = N holds, but N is an odd number, and the number of control signal greens is n (<< N). A practical integrated circuit can be realized by minimizing the number of control signal lines while having the multi-tone output.

The unit switching section has a current capacity as a quantization unit of the output current. The configuration of the unit switching section may be a single field-effect transistor.
A parallel connection circuit of a plurality of field effect transistors adjacent to each other may be used. Normally, the unit switching section will be constituted by a single field-effect transistor. However, when a quantization unit (corresponding to resolution) of an output current cannot be obtained by one field-effect transistor due to a semiconductor layout. Can also occur. In such a case, the total current capacity reaches the quantization unit of the output current by connecting a plurality of field effect transistors having a small element occupying area in parallel.

The output pads corresponding to each switching means on a one-to-one basis are usually arranged in a row, but it is necessary to incorporate each switching means within the output pad pitch. In such a case, the N unit switching units have the same shape and a parallel movement arrangement structure with the same pitch in one direction, so that the current capacities of the unit switching units are substantially equal to each other, and the switching is performed within the output pad pitch. The means can be accommodated successfully.

Here, if the current capacities of the unit switching units are substantially equal to each other, the output current value monotonically increases with respect to the digital value of the n-bit digital control signal.
What guarantees the equality of the current capacity of the unit switching unit will be to make the built-in shape and size the same. However, even in the N array structure of the unit switching unit, variations in the manufacturing process are inevitable. Occur. For example, when a gate electrode is formed by photolithography, the shape of the gate electrode of each transistor varies. Variations in the shape of the gate electrode inevitably lead to variations in the current capacity (or on-resistance) of each switching unit. Even if the N unit switching units have the same shape in the array structure, this cannot completely guarantee the equality of the current capacity. Therefore, it is necessary to consider the variation of the current capacity between the unit switching units. Experience has shown that the variability characteristics that can occur here generally exhibit monotonicity in the array. In a case where the current capacity of the unit switching section monotonically increases from one end to the other end in the array, when the N unit switching sections are sequentially distributed from the first group to the n-th group from the one end to the other end, n bits. When the digital control signal is continuously carried (when adjacent bits are carried at the same time), there is a possibility that the output current value does not monotonously increase but drops instead (so-called level drop). , N unit switching units are connected in parallel by a current combining circuit, that is, a current output type digital / analog converter (D
AC) may not function properly. Therefore, when a single unit switching unit belonging to the first group is positioned at the center of the parallel movement array, N
Among the unit switching units, the current capacity of the first group of unit switching units has an average current value (median value). For the unit switching units other than the central unit switching unit, the group to which the unit switching units located at positions away from the symmetric axis by one by one toward both ends of the array is defined as a unit switching unit of the first group. n → n-1 → n
→ n-2 → n → ・ ・ ・ → n → 2 → n → ・ ・ ・ → n → n-
In the case of 2 → n → n−1 → n, the current capacity of the unit switching unit for each group is equal to the above average current value. Therefore, the linearity between the digital value of the n-bit digital control signal and the output current value is guaranteed. Even if there is a linear gradient of the variation of the current capacity in the arrangement direction, the linearity of the output current with respect to the digital value is ensured. According to the correspondence between the unit switching units and the groups, even if there is not a linear gradient of the current capacity in the array direction but a monotonic gradient close thereto, at least the monotonicity of the input digital value and the output current value is A current synthesizing circuit as a DAC that is guaranteed and does not have a level drop can be realized, so that the yield can be improved.

The configuration of each unit switching unit described above is either a single field-effect transistor or a parallel connection circuit of a plurality of field-effect transistors adjacent to each other. A parallel connection circuit of a plurality of non-adjacent field effect transistors may be used. That is, the unit switching units belonging to the same group are a parallel connection circuit composed of two or more field-effect transistors arranged symmetrically, and the field-effect transistors of the unit switching units belonging to different groups are adjacent to each other. Format is acceptable.

The fact that the mutual arrangement of the field-effect transistors, which are constituent elements of the unit switching section, is substantially problematic is related to the variation in the current capacity caused by the above-described transistor manufacturing process. The advantage of disposing the transistors of the unit switching unit belonging to the same group in a distributed manner with the transistors belonging to the other group adjacent to each other is as follows.
Specifically, the following group pattern may be adopted. Here, in the case where the unit switching section includes a plurality of transistors, the problem of the variation in the current capacity can be easily discussed by introducing the concept of the center of gravity (average position or equivalent position) on the layout of the plurality of transistors. That is, the center of gravity (average position or equivalent position) of two or more field-effect transistors belonging to the first group is determined at the center of the parallel displacement array, and the center of gravity is set as the axis of symmetry, and one is located from the axis of symmetry to both ends of the array. In the direction away from each other, the center of gravity of two or more field-effect transistors in the unit transistor unit belonging to the same group is n → n−1 → n → n−2 → n →... → n → 2 → n →・
··· → n → n−2 → n → n−1 → n When arranged so as to form a group pattern, the transistors in each unit switching unit have a variation in current capacity, but are dispersed in the arrangement direction. Position, so that compared to the case where a plurality of transistors are adjacent to each other,
Variations between the unit switching units can be suppressed. In particular, the variation in the unit switching unit itself can be reduced even with respect to the variation distribution of the current capacity that is poled near the center point of the transistor array, so that the linearity between the digital input and the output current is greatly improved.

The switching means, which is a parallel connection of the N unit switching units, can provide an output current in N stages. However, in order to enable further fine correction of the output current, the number of unit switching units must be reduced. Instead of increasing the number, one or more offset field-effect transistors having a relatively large current capacity are provided. In other words, when an offset field-effect transistor is provided, it is assumed that it is used for all driven elements, and the number of unit switching units to be operated to correct each output is set based on the assumption. Is done.

[0027]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment in which a multi-output current supply integrated circuit according to the present invention is applied to an LED printer driving circuit will be described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of an LED printer driving circuit.

The main frame 1 is composed of a computer for sending data signals and the like to the microprocessor 11. The microprocessor 11 stores the correction code RO
A control signal is sent to an M (read only memory) 12, and correction code data is taken in from the control signal.
The data signal, the latch signal, the correction data signal, and the enable signal are sent to the LED printer head driving integrated circuit 13. The LED printer head driving integrated circuit 13 includes:
A data shift register unit 14 for directly inputting a one-line print data signal supplied from the main frame 1 via the microprocessor 11 in synchronization with a first clock signal supplied from the microprocessor 11,
A latch circuit array section 15 which fetches and temporarily holds the contents of each flip-flop (F / F) of the data shift register section 14 in synchronization with the latch signal, and directly outputs the correction data signal in synchronization with the second clock signal. A shift register unit 16 for correction data for parallel conversion, an output transistor control circuit unit 17 for outputting a gate signal based on the 4-bit digital signal and the enable signal generated by the register unit 16, and each gate signal And an output transistor section 18 having switching circuits 18-1 to 18-m that are switching-controlled.

The switching circuits 18-1 to 18-m of the output transistor section 18 in the LED printer head driving integrated circuit 13 and the LEDs 19-1 to 19-m of the LED array integrated circuit 19 are connected one to one. and which, each LED emits light, extinction in the current supply and interruption of the power supply V _SS by Tsugidan operation of the switching circuit. In addition,
Reference numeral 20 denotes a photosensitive drum which is closely opposed to the LED array integrated circuit 19, and reference numeral 2 denotes a main power supply.

FIG. 2 is a block diagram showing the configuration of the LED printer head driving integrated circuit 13 in FIG.

The data shift register section 14 includes m D shift registers.
Flip-flops 14-1 to 14-m, and the first clock signal 14a
Each time it is added, it shifts the binary serial data taken in via the data terminal 14b, and the data for one line printing is converted from serial to parallel. The latch circuit array unit 15 includes a D flip-flop latch circuit (LA).
T) 15-1 to 15-m, and the latch terminal 15a
The contents of each digit of the shift register unit 14 are temporarily held by the latch synchronizing signal. The correction data shift register section 16 is composed of 4m D flip-flops,
The correction data of the serial signal of 4 m digits in binary inputted to the correction data terminal 16b is shifted one by one by the second clock inputted to the second clock terminal 16a.
The correction data shift register section 16 has m partial shift registers (SR) each of which has four stages of D flip-flops as one unit. Each partial shift register corrects the emission intensity of the corresponding LED. (For example, B ₁₄ , B ₁₃ , B ₁₂ , B ₁₁ ). The output transistor control circuit unit 17 has m control and level shift circuits as one circuit unit, and each control and level shift circuit outputs data (for example, data (e.g., data) output from each latch circuit of the latch circuit array unit 15. D _il ) and 4-bit parallel correction data (for example, B ₁₄ , B ₁₃ , B ₁₂ , B) output from the partial shift register of the correction data shift register unit 16.
_ll ), and the corresponding current synthesizing circuit described later is synchronized with the enable signal input to the enable terminal 17a.
Transmits a bit parallel gate control signal.

FIG. 3 is a circuit diagram showing the control of the output transistor control circuit 17 and the level shift circuit 17-1 in FIG. Note that other control and level shift circuits 1
The circuit configurations of 7-2 to 17-m are the same.

The control and level shift circuit 17-1 comprises a logic control circuit section 21-1 and a level shift circuit 22-1. The data signal D in this embodiment is H
The level is a print command, the L level is a non-print command, and the enable signal is a H level for a print period, and the L level is a non-print period. LED corresponding to this control and level shift circuit 17-1
To set 19-1 to either an on-state or an off state, the logic control circuit unit 21-1, NAND gates inputting an enable signal and a data signal D _il 21-
There is provided a print mode determination circuit 21-1c composed of 1a and an inverter 21-1b. Further, it receives the 4-bit parallel signals B ₁₄ , B ₁₃ , B ₁₂ , and B _{11 of the} correction data and the print mode signal output from the print mode determination circuit 21-1c, so-called a digital-to-analog converter of a current synthesis circuit described later. A NAND gate 21-1d for logically creating a 4-bit output signal of the DAC (DAC) and an inverter 21-1e for inverting the print mode signal are provided.
Control and the level shift circuit 17-1 offset gate control voltage OS _l and DAC gate control voltage S _14,
In order to obtain S ₁₃ , S ₁₂ , and S ₁₁ , five level shift circuits having the same configuration are used. Each of the level shift circuits includes an inverter 21-1e or a NAND gate 21.
Inverter 22-1a for inverting the output signal of -1d
When the transmission gate T _M and, the transmission gate T external source voltage output during off _M V _SS to transmit the external tag section gate bias voltage V _GG as a control input the inverted output of the output signal and the inverter 22-1b P-channel MOSFET 22 for forced determination
-1c.

The print mode signal output serving as the logic voltage level of the printing mode decision circuit 21-1c is converted into the external gate bias voltage V _GG and the offset control signal OS _l varying between the external source voltage V _SS. The NAND gate 21-1D DAC control signal output is also the same voltage level of the _{S 14, S 13, S 12} , is converted to S _ll.

FIG. 4 is a circuit diagram showing a configuration of the current combining circuit in FIG.

The current synthesizing circuit as each switching means in this embodiment is composed of a digital / analog conversion circuit and an offset field effect transistor.
The current synthesizing circuit 18-1 shown in FIG. 4 has fifteen P-channel field effect transistors F _T1 to F _T1 having substantially the same current capacity.
A current output type digital / analog conversion circuit 18-1a as a parallel connection of _T15 and a single offset P-channel field effect transistor F _OS1 occupying almost one third of the total current capacity connected in parallel with this. Become. This semiconductor structure of the current combining circuit 18-1 will be described later, the control signals S 1 one number is of _ll transistor having a gate signal (F _T8), a control signal S ₁₂ transistor having a gate signal (F _T4, F the number of _T12) is two, the control signal S ₁₃ a transistor having a gate signal _{(F T2, F T6, F} Tl0, F T14)
The number four, and the control signal S ₁₄ a transistor having a gate signal _{(F T1, F T3, F} T5, F T7, F T9 F T11, F
_T13 , F _T15 ) is eight. That is, the control signal S _ll is a transistor F _T8 is turned on when the L-level, the control signal S ₁₂ is a transistor F _T4 and F _T12 is turned on when the L-level, and when the control signal S ₁₃ is at the L level transistors F _T2, F _T6, F _T10 and F _T14 are oN state, further when the control signal S ₁₄ is L level, the transistors _{F Tl, F T3, F T5} , F T7, F T9, F T11, F
_T13 and F _T15 are turned on.

Next, the operation of the above embodiment will be described with reference to FIG.

When the power supply 2 of the LED printer is turned on prior to the printing operation, first, the microprocessor 11 sends a control signal to the correction data storage ROM 12, whereby the correction data storage ROM 12 transfers the control signal to the microprocessor 11.
, A correction code data signal is sent. Then, the microprocessor 11 sends the correction code data signal to the correction data shift register 16 together with the second clock signal. Here, the correction code data signal is a serial digital signal of 4 m bits, where one line printing is m dots, of which four serial bits correspond to correction data of one dot printing. The transmission period of the correction data signal and the second clock signal is only a fixed period after the power supply 2 is turned on, and once they are transmitted, the correction data will not be transmitted again until the power supply is turned off. The serial digital signal of 4 m bits is sequentially supplied to the lowermost D flip-flop (F / F) of the shift register 16 for correction data every second clock.
F). The 4 m-bit serial digital signals are all stored in the correction data shift register 16 by the 4 m second clock pulses. Thereafter, since the microprocessor 11 does not transmit the second clock pulse, the shift register 16 for correction data itself does not perform the shift operation, and the correction data, which is a serial digital signal of 4 m bits, is directly stored in the shift register unit 1 for correction data.
6 is held. Here, the output of the partial shift register 16-1 of the correction data shift register 16 is the first digit B _ll , the second digit B ₁₂ , the third digit B ₁₃ , and the fourth digit B ₁₄ .
The bit signal (corresponding to one dot correction data signal) is maintained.

When the operation of setting the correction data signal in the correction data shift register 16 is completed, the data signal is supplied to the data shift register 14 via the microprocessor 11 together with the generation of the first clock signal. Now one line printing data to the i-th row of the data D _i, the data D _i is stored in the shift register portion 14 parts data by m first clock. When the latch signal _Li is sent from the microprocessor 11 and supplied to the latch circuit array unit 15, the latch circuits 15-1 to 15-m of the latch circuit array unit 15 correspond to the data shift register unit 14. captures the D output of the flip-flop 14-1 to 14-m (data D _i) holds it time. That is, the latch circuits 15-1 to 15-
The output of m is set to data D _{i1 to} D _im .

Here, the operation of this embodiment will be described focusing on the printing operation of the LED 19-1. Next, when the enable signal is H
Level, the level of the data signal _{Dil changes} to LE.
The presence or absence of printing of D19-1 is determined. That is, when the data signal _Dil is at the H level, the print mode determination circuit 21
The output of -1c becomes H level, when the data signal D _il is at L level becomes the output thereof to L level. Circuit 21-1
When the output of c is at the H level, it means the print mode period, the transmission T _M of the offset transistor is closed, and the gate bias voltage V _GG is changed to the signal OS _l.
Is supplied to the offset P-channel field-effect transistor F _OSl to _close the field-effect transistor F _OSl . The correction data signal is supplied to the control and level shifting circuit 17-1 as _{B 14, B 13, B 12} , B ll.
For example, in the at H-level data signal B ₁₄ Here, when the data signal B _13, B _12, B _ll is at L level, the signal S ₁₄ is the gate bias voltage V _GG, and the signal S _13, S _12, S _ll
Becomes the source voltage V _SS . Thereby, the DAC 18-1
out of the transistors a, the transistors F _Tl , F _T3 , F
_T5 , F _T7 , F _T9 , F _Tll , F _T13 , and F _T15 are off. Here the current capacity of the offset P-channel field effect transistor F _OS1 and i _OS, when the current capacity of each transistor of DAC18-1a and i _O, if only the signal S ₁₄ is set in the gate bias voltage V _GG , the current value supplied to LED19-1 via the output terminal O _l is i
_OS + 8 _iO . That is, the 4-bit signals S ₁₄ , S ₁₃ , S ₁₂ ,
Assuming that the supply current value to the LED 19-1 is I depending on S _ll ,

[0042]

## EQU3 ## The following equation holds: i _OS ≤i≤i _OS + 15i _O (1)

As described above, since the current value i that can be supplied to one dot (one LED) can be changed in an increasing or decreasing manner, the current value i corresponds to the supply current value so as to correct the light emission intensity of the LED to be supplied. By storing the correction code data in the correction data storage ROM 12 in advance, all L
Since the emission intensity of the ED is corrected to a standard value, this prevents printing unevenness.

Since this uneven printing correction changes the supply current to each LED in an increasing or decreasing manner, one line printing is performed for each latch cycle. Therefore, the printing speed can be increased. That is, speedup three times as much as that of the conventional printer head is realized. In addition, the correction data signal is stored once in the correction data shift register unit 16 once without directly regenerating the data signal internally, and the supply current value for each LED is set thereafter. Therefore, simplification of the program of the microprocessor 11 and simplification of control are achieved. Further, independent gray-scale control for each dot in one-line printing is possible.

The significance of the addition of the offset P-channel field effect transistor is that the variation in the light emission intensity of the LED is generally expected to be about ± 20%. Of course, LE
Even if there is variation for each D, the emission intensity itself of each LED is almost directly proportional to the supply current. Therefore, if an offset transistor F _OSl that supplies a minimum required current is provided for each LED, only about 20% of the emission intensity is additively corrected by the DAC 18-1a. DA
In this embodiment, the variation in the light emission intensity of the LED was reduced to about ± 1% by supplying the current of 16 gradations of C.

FIG. 6 is a schematic diagram showing a circuit layout in a semiconductor chip of the integrated circuit for driving the LED printer head shown in FIG.

This integrated circuit chip has a required input logic section 50 and m D flip-flops 14-1 to 14-.
shift register unit 14 and latch circuit array unit 15 in which m and latch circuits 15-1 to 15-m are arranged
And m partial shift registers 16-1 to 16-m and m control and level shift circuits 17-1 to 17-m
Data shift register section 16 and output transistor control circuit section 17 in which m are arranged, and m current combining circuits 1
Output transistor section 18 in which 8-1 to 18-m are arranged
When the output terminal O ₁ ~ O _m pad region 34 having an array of _p corresponding to the current combining circuit 18-1 to 18-m, are divided generally into.

FIG. 7 is a plan view showing a semiconductor structure of the current combining circuit shown in FIG.

DAC 18-1a of current synthesis circuit 18-1
Of the field-effect transistors F _{Tl to} F
_T15 is formed in the same shape at the same pitch in one direction. That is, slender polysilicon gate G ₁ ~G ₁₅ of each transistor are arrayed at equal intervals. Except immediately below the polysilicon gates G _{1 to} G ₁₅ , the active regions 30 extend in the arrangement direction thereof. The formation of the active region 30 is realized by self-alignment by ion implantation using the polysilicon gates G _{1 to} G ₁₅ as a mask.
The channel length of each transistor is the polysilicon gate G _l
The width dimension of ~G _15, the channel width is given by the width of the active region 30. On the other hand, the polysilicon gate G _OS1 forming the offset P-channel field effect transistor F _OS1 is formed in a strip shape along the arrangement direction of the transistors F _{T1 to} F _T15 . The active region 31 of the transistor F _OS1 extends along the polysilicon gate G _OS1 in the direction in which the transistors F _{T1 to} F _T15 are arranged.
Source electrode wiring 3 to which source bias voltage V _SS is applied
Reference numeral 2 denotes a common electrode wiring portion 32a which makes conductive contact with the P-type source region of the offset active region 31 through a large number of contact holes h having the same pitch, and eight source electrodes of the same pitch branched from the common electrode wiring portion. And a portion 32b. The drain electrode wiring 33, common to contact the conductive via multiple contact hole h of the same pitch in a rectangular shape and connected to the Bonding pads 34 _p1 P-type drain region of the offset for the active region 31 as the output terminal O _l An electrode wiring portion 33a and eight drain electrode portions 33b of the same pitch branched in a comb-like shape from the electrode wiring portion 33a
It is composed of One end of the offset polysilicon gate G _OS1 is in conductive contact with the offset gate wiring 34 to which the offset gate signal _OSl is to enter via a contact hole h. The polysilicon gate G ₈ of the central transistor F _T8 is connected to the first gate line 35 to receive the gate signal S ₁₁ by transistors F _T4 and F _T4 .
_T12 polysilicon gate G ₄ of, G ₁₂ to the second gate line 36 to receive a gate signal S _12, the transistors F _T2,
The polysilicon gates G ₂ , G ₆ , G of F _T6 , F _T10 , F _T14
10, G ₁₄ the third gate line 37 to receive a gate signal S _13, further transistors _{F T1, F T3, F T5} , F T7, F
_{T9, F Tll, F T13,} F T15 of the polysilicon gate G _l, G
_{3, G 5, G 7,} G 9, G ll, G 13, G 15 is the gate signal S ₁₄
Are respectively connected to the fourth gate wirings 38 to be input.

More specifically, the first to fourth gate wirings 35 to 3
8 and the connection structure of each transistor will be described. The connection structure of the central transistor F _T8 and the first gate wiring 35 is shown in FIG.
This is the structure shown in FIG. That is, the transistor F _T8 is
It has a channel region ch sandwiched between a P-type source region and a drain region diffusedly formed in an N-type semiconductor substrate, and a polysilicon gate G ₈ formed on the substrate surface via a gate oxide film 39. the first layer wiring g ₈ via the interlayer insulating film 40 is formed on the polysilicon gate G ₈ is formed,
In this case, the polysilicon gate G ₈ is in conductive contact via the contact hole h, and is in conductive contact with the first gate wire 35 as a second layer wire on the interlayer insulating film 41 via another contact hole h. . Polysilicon gate G ₇ of the transistor F _T7 adjacent to FIG. 7 shows the right transistor F _T8, as shown in FIG. 8 (b), an interlayer insulating film 40
The first layer wiring g ₇ above in contact conductive through the contact hole h, first layer wiring g ₇ is conductively connected to the fourth gate line 38 as a second layer wiring through a contact hole h I have. Also, the polysilicon gate G ₆ of the transistor _{FT 6} is connected to the third gate wiring 37 of the second layer wiring via the contact hole h, the first layer wiring g ₆ and the contact hole h as shown in FIG. 8C. are further also the polysilicon gate G ₄ of transistors F _T4 8
As shown in (d), the contact hole h and the first layer wiring g
₄ and the contact hole h are connected to the second gate wiring 36 of the second layer wiring. In addition, 42 is a protective film.

Here, the first to fourth gate wirings 35 to 38
Connection relationship (signal S _ll to S ₁₄₎ and transistor F _Tl to F _T15 are shown in Table 1 listed below.

[0052]

[Table 1]

[0053] That is, the transistor connected to the first gate line 35 to receive the first digit of the signal S _ll of 4-bit parallel signals in Toranjita F _T8, it is located in the center of the transistor array structure. Also connected transistor to the second gate line 36 to receive the second digit of the signal S ₁₂ of 4-bit parallel signals by the transistors F _T4 and F _T12,
The two transistors F _T4 and F _T12 are arranged symmetrically with respect to the center transistor F _T8 . Further 4 third digit transistors connected to the third gate line to receive a signal S ₁₃ of the bit parallel signal transistors F _T2,
F _T6 , F _T10 and F _T14 , of which the transistors F _T6 and F _T6
T10 is symmetrically arranged with respect to the center transistor _FT8 , and transistors _FT2 and _FT14 are also symmetrically arranged with respect to the center transistor _FT8 . Furthermore the transistors connected to the fourth gate wiring to receive the signal S ₁₄ of the fourth digit of the 4-bit parallel signals Toranjita F _Tl, F _T3, F
_T5 , F _T7 , F _T9 , F _Tll , F _T13 , and F _T15 , where the transistors F _Tl and F _T15 , the transistors F _T3 and F _T13 , the transistors F _T5 and F _Tll , and the transistors F _T7 and F _T9 are respectively central. in Sekimago symmetrical arrangement with respect to the transistor F _T8. While such a first gate signal S ₁₁ receives transistor array center, meaning placing the other transistors symmetrically is as follows.

When the transistors F _{Tl to} F _T15 are formed in the same shape and at the same pitch, the current capacity of each transistor is expected to be substantially the same. However, in the actual semiconductor manufacturing process, for example, the plasma etching of each of the polysilicon gates G _{1 to} G ₁₅ does not completely have the same shape, and variations in current capacity inevitably occur due to alignment accuracy such as mask shift. I do. It has been empirically found that the variation distribution of the current capacity has a substantially monotonic property in the transistor array direction. Here, the discussion will proceed assuming that there is a linear gradient. As shown in FIG. 9, it is assumed that the current capacity of the transistors F _{T1 to} F _T15 decreases linearly from one end to the other end of the array. And the transistor F _Tl is the first gate signal S _ll, the transistors F _T2 to F _T3 second gate signal S _12, the transistors F _T4 to F _T7 third gate signal S _13, and transistor F _T9 to F _T15 There is to be turned on / off controlled by the fourth gate signal S _14. That is, it is assumed that transistors connected to each digit signal of the 4-bit parallel signal are adjacent to each other. In such a connection relationship, the 4-bit parallel signals (S ₁₄ , S ₁₃ , S
₁₂ , S ₁₁ ) when the output current value changes monotonically, considering that the transistor is a P-channel transistor, the gate signal is binary 1 when the gate signal is low and binary when the gate signal is high. If it is set to 0, the 4-bit parallel signal changes from 0001 to 1111. During the period from 0001 to 0111, the output current value monotonically increases as shown in FIG. However, the output current value at the time of 1000 takes a lower value than that at the time of 0111, and here the monotonic increase property is broken. In other words, the maximum level drop of the output current value occurs at the time when three consecutive carry occurs. The example shown in FIG. 9 shows a case where the gradient of the current capacity of the transistor is relatively large.
The output current value at 001 and 1010 is also lower than that at 0111.

As described above, the variation in the current capacity of the transistor causes a drop in the level of the output current value of the DAC, and the monotonicity is locally impaired. Here, the tolerance of the variation in the current capacity of the transistor that suppresses the level drop of the output current will be quantitatively considered. The current characteristic variation characteristic line shown in FIG.

[0056]

[Number 4] _{I N = I O - △ I} · N put the ... (2). Where I _O is a constant, N is an order from the left end of the transistor array, and ΔI is a change in current capacity between adjacent pitches. For example, the current capacity of the transistor F _Tl is

[0057]

[Equation 5] I _l = I _O − △ I (3) where the current capacity of the transistor F _T15 is

[0058]

[6] I ₁₅ = I _O -15 △ is given by I ··· (4). In a 4-bit parallel human-powered DAC, the most danger of level drop is 0111-10.
00 is the transition point. Therefore, a condition under which the level drop does not occur is given by the following equation.

[0059]

(Equation 7)

That is,

[0061]

[Expression 8] ΔI <I _O / 64 ···
(6) That is, unless the change value ΔI of the current capacity between adjacent transistors is less than 1.5% (≒ 1/64 × 100) of the current capacity of the adjacent transistor,
The output current level drops. Needless to say, in order to allow a multi-bit DAC having four bits or more and functioning properly without malfunction, the change value must be smaller than the above-mentioned%. However, such a change value is inevitably generated in the manufacturing process. Even if the process control is strict, it is inevitably generated in a wear unit or a chip unit.

Therefore, in this embodiment, as described above, the transistor F having the first digit of 4 bits as the gate input _Sll is used.
A connection structure is adopted in which _T8 is placed at the center of the array and transistors having the same digit as the second digit or more as gate inputs are symmetrically arranged. In this connection structure, of course, variations in the current capacity of the transistors inevitably occur in the manufacturing process. However, as shown in FIG. 10, if the current capacity of the central transistor F _T8 is i, the gate input As the signal increases monotonically, the output current monotonically increases in units of the current value i. That is, the transistor is turned on with respect to the second gate signal S ₁₂ is F _T4 and F _T12, the total current value that is output from them is 2i. The transistor which is turned on by the third gate signal S ₁₃ is F _Tl and F _T15, F _T3 and F _T13, FT ₅ and F _T11, and an F _T7 and F _T9, the total current value that is output from them with 8i is there. The current capacity of the pair of transistors at the left-right symmetrical position turned on by each gate signal takes a change value of ± △ i with respect to the current capacity i of the transistor _{FT8 at} the center of the array.
Since the change value of Δi is canceled out conveniently, it always becomes 2i which is twice the current capacity i. That is, according to the connection structure as described above, the variation due to the manufacturing process of the current capacity between the transistors can be eliminated or reduced.
The linearity or monotonicity of the output current applied to the input signal is guaranteed.

The variation characteristics of the current capacity have been considered on the assumption that there is linearity. Although this is valid in many cases, a more generalized variation characteristic is considered to be a monotone curve of a quadratic curve having no extreme value between both ends in the transistor arrangement direction. . In such a case, as shown in FIG.
Although the linearity of the output current is slightly impaired, at least monotonicity is guaranteed. Even if a DAC having this characteristic is used, by changing the correction data signal, that is, the gate signal,
It goes without saying that correction of the light emission intensity of the LED is easily realized.

FIG. 12 is a circuit diagram showing a connection relationship between another field effect transistor array and a gate signal.

In the field effect transistor array constituting the DAC, 30 transistors _FT1 to _FT30 are formed as a parallel displacement array having the same shape and the same pitch in one direction. In this arrangement, the gates of a pair of adjacent transistors are connected. That is, in this sequence:
(F _Tl , F _T2 ), (F _T3 , F _T4 ), (F _T5 , F _T6 ),
(F _T7 , F _T8 ), (F _T9 , F _T10 ), (F _Tll ,
F _T12 ), (F _Tl3 , F _Tl4 ), (F _T15 , F _Tl6 ), (F
_T17 , _FT18 ), ( _FT19 , _FT20 ), ( _FT21 , _FT22 ),
(F _T23 , F _T24 ), (F _T25 , F _T26 ), (F _T27 ,
The set of F _T28 ) and (F _T29 , F _T30 ) respectively functions as a unit switching unit that waits for a current capacity twice the current capacity of the transistor. The set (F _T15 , F _T16 ) located at the center receives the gate signal _Sll . This center set ( _FT15 , F
Each set _T16) symmetrically thereto as a symmetrical axis is the input gate signal _{S 12, S 13, S 14} . That is, the set (F
_T13 , F _T14 ) and (F _T17 , F _T18 ) are _added to the gate signal S ₁₄ ,
The pairs (F _Tll , F _T12 ) and (F _T19 , F _T20 ) are gate signals S
_13, the set (F _T9, F _T10), the (F _T21, F _T22) is the gate signal S _14, the set _{(F T7, F T8),} (F T23, F T24) to the gate signal S _12, the set ( _FT5 , _FT6 ), ( _FT25 , _FT26 )
The gate signal S _14, the set _{(F T3, F T4),} (F T27, F
_T28) to the gate signal S _13, the set (F _T1, F _T2),
(F _T29 , F _T30 ) are connected to the gate signal S ₁₄ , respectively. Even if it is not a single transistor but a unit transistor unit having a plurality of adjacent transistors as one unit,
The DAC function is substantially the same as the circuit configuration shown in FIG.
However, by increasing the number of transistors instead of shortening the channel width due to the transistor array configuration,
Even when the distance between the output pad and the pitch is narrow, the degree of freedom to form the DAC in a limited space increases. The output current of the DAC shown in FIG. 12 has a linear characteristic as shown in FIG. Note that three or more transistors may be set as one set.

FIG. 14 is a circuit diagram showing a connection relationship between another field effect transistor array and a gate signal.

Also in this DAC, 30 transistors F _{T1 to} F _T30 are formed in a parallel movement array having the same shape and the same pitch in one direction. Also in this arrangement, a pair of transistors functions as a unit switching unit, but is different from the connection relation between the transistor arrangement and the gate signal shown in FIG. 12, except for the transistors F _T15 and F _T16 at the center of the arrangement. Transistors do not form a unit switching unit as a set, and adjacent transistors input gate signals of different digits. FIG.
The numbers shown in Katsuko in 4 reveal digit number of the gate signal, but the transistor F _T15, F _T16 located in SEQ center gate signals S _14, the transistors F _T14, F _T17 gate signal S ₁₃ , The transistors F _T13 and F _{T18 receive} the gate signal S
₁₄ , the transistors F _T12 and F _{T19 output} the gate signal S ₁₂ ,
The transistors F _T11, F _T20 gate signals S _14, the transistors F _T10, F _T21 gate signals S _13, the transistors F _T9, F _T22 is a gate signal S _14, the transistor F _T8,
F _T23 is a gate signal S _ll, the transistors F _T7, F _T24 gate signals S _14, the transistors F _T6, F _T25 is a gate signal S _13, the transistors F _T5, F _T26 gate signals S
_14, transistors F _T4, F _T27 is a gate signal S _12,
The transistors F _T3, F _T28 gate signals S _14, the transistors F _T2, F _T29 is a gate signal S _13, the transistors F _Tl, F _T30 is a gate signal S _14, respectively input. The above pairs are arranged symmetrically with respect to the center of gravity (average position) of the central transistors F _T15 and F _T16 . In order to clarify the connection relationship between the transistor arrangement and the gate signal, the concept of the center of gravity will be extended. As shown in FIG. 15, the transistor arrangements (F _{Tl to} F _T30 ) are arranged in one direction at the same pitch P, and the position of each transistor is determined by the digit number (1 to 4) of the gate signal input thereto. It is shown in. A pair of transistors (F
The center of gravity (parallel position) of ( _T8 , F _T23 ) is at the center of the transistor array length. When the distance between the transistors F _T8 and F _T23 is calculated by shifting the center of gravity of a pair of transistors while shifting 15P one by one, the number of centers of gravity is 15, and the order of the digit number to which each center of gravity belongs is 4 → 3 → 4. → 2 → 4 → 3 → 4 → 1 →
4 → 3 → 4 → 2 → 4 → 3 → 4. This order pattern is the same as the embodiment shown in FIG. The significance of such a connection relationship is that the variation characteristics of the transistor current capacity do not have a substantially uniform gradient over the length of the transistor array, and monotonicity of the output current is guaranteed even when an extreme value is obtained in the middle. That's why. For example, as shown in FIG. 16, when considering the case where the variation characteristic of the transistor current capacity has a minimum value substantially at the center of the transistor array length, the transistors _FT8 and _FT23 inputting the first digit have a distance of 15P.
, The sum of the current capacities is closer to the sum of the variation characteristic average values. Because there is no gap in the sampling of variation characteristics,
This is because the dispersion characteristic values tend to be summed over a wider sampling interval. Of course, if the number of transistors having the first digit as an input is not only two, ie, F _T8 and F _T23 , but also a large number of transistors, a monotonous output current characteristic can be obtained with high accuracy even for various variations. Therefore, improvement in the yield of DAC is further expected.

[0068]

As described above, the present invention provides a current combining circuit in which N unit switching units having substantially the same current capacity are connected in parallel as switching means corresponding to driven elements on a one-to-one basis. Because it is provided
The following effects are obtained.

Since the N unit switching units can be simultaneously turned on / off simultaneously, the current supplied to the driven element is not a constant value but has discrete N-stage values. Therefore, even if there is a variation in the output value between the driven elements, the supply current can be increased or decreased, so that the variation in the output value of all the driven elements can be corrected with high accuracy within a fixed time. became. As a result, printing or display in a short time is achieved, re-generation of the correction data signal is eliminated, and simplification of the circuit configuration is also realized. Conversely, tone control for each dot in one-line printing or display can be realized independently.

Further, while dividing the N unit switching units into n groups and setting the number of unit switching units belonging to the ith group to 2 ⁱ⁻¹ , all unit switching units belonging to the ith group Is connected to the first digit of the n-bit digital control signal, the number of control signal lines can be minimized, and space can be saved in circuit configuration and semiconductor layout.
Therefore, a practical integrated circuit can be achieved by reducing the chip size.

Further, the unit switching units belonging to the first group are placed at the center of the transistor translation array, and this is set as a symmetry axis, and at a position away from the symmetry axis to both ends of the array one by one, n → n−1 → n → n-2 → n → ... →
When the unit switching units are arranged in a group pattern in the order of n → 2 → n →... n → n−2 → n → n−1 → n, the variation of each current capacity in the arrangement direction is reduced. Even when exhibiting a linear gradient, the total current capacity of the unit switching units in each group is equal to the product of the current capacity (average current value) of the central unit switching unit and the number of unit switching units. The output current value shows highly accurate linearity with respect to the digital value of the bit digital control signal. For this reason, a drop in the level of the output current value that occurs at the time of successive carry of digital values is effectively prevented. Therefore, an improvement in the yield of the integrated circuit is achieved.

In a case where the unit switching section is configured by two or more transistors, and transistors belonging to different groups are adjacent to each other and transistors belonging to the same group are separated from each other, a transistor arrangement form is adopted. The center of gravity (average position) of two or more transistors belonging to the first group is placed at the center, and the center of gravity is set as a symmetry axis in a direction away from the axis to both ends of the array one by one,
The center of gravity of two or more transistors belonging to the same group is n → n−1 → n → n−2 → n →.
.., N → n−2 → n → n−1, the current capacity of each unit switching unit is separated within the array range. It becomes the sum of the current capacities of the arranged transistors, and the current capacity is sampled more widely from the variation distribution of the transistor current capacity.Therefore, the arrangement is not limited to the case where the variation distribution has a linear gradient, for example, an array. The linearity between the digital input and the output current is reliably shown even for a variation distribution having an extreme value near the center point.

In the case where the offset transistor is provided, further fine correction of the output current to the driven element can be performed.

[Brief description of the drawings]

FIG. 1 shows an integrated circuit for supplying multiple outputs according to the present invention.
FIG. 3 is a block diagram showing an embodiment applied to a D printer driving circuit.

FIG. 2 is a block diagram showing in detail an integrated circuit for driving an LED printer head in the embodiment.

FIG. 3 is a circuit diagram showing a control and level shift circuit in the embodiment in detail;

FIG. 4 is a circuit diagram showing a current combining circuit in the embodiment.

FIG. 5 is a timing chart of each signal for explaining the operation of the embodiment.

FIG. 6 is a schematic plan view showing a chip layout of the LED printer head driving integrated circuit in the embodiment.

FIG. 7 is a plan view showing a semiconductor structure of the current combining circuit in the embodiment.

8 (a), (b), (c) and (d) are VIIIa-VIII'a line, VIIIb-VIII'b line and VIII line in FIG. 7, respectively.
It is the cutting figure cut | disconnected along c-VIII 'c line and VIIId-VIII' d line.

FIG. 9 shows the linear variation characteristics of the current capacity of the arranged transistors and the output current with respect to the digital input signal under the general connection relation of the transistor to the gate signal input line for the digital-to-analog converter (DAC). It is a graph which shows a characteristic.

FIG. 10 is a graph showing a linear variation characteristic of a current capacity of arranged transistors and a linear characteristic of an output current with respect to a digital input signal in the DAC according to the embodiment.

FIG. 11 is a graph showing a monotonic variation characteristic of a current capacity of arranged transistors and a monotonic characteristic of an output current with respect to a digital input signal in the DAC according to the embodiment.

FIG. 12 is a circuit diagram showing a configuration example of another DAC in the embodiment.

FIG. 13 is a graph showing a linear variation characteristic of a current capacity of arranged transistors and a linear characteristic of an output current with respect to a digital input signal in the same configuration example.

FIG. 14 is a circuit diagram showing a configuration example of another DAC in the embodiment.

FIG. 15 is a schematic diagram for explaining a transistor arrangement pattern in the same configuration example.

FIG. 16 is a graph showing a current capacity variation characteristic having an extreme value near a center point of transistors arranged in the same configuration example, and a monotonic characteristic of an output current with respect to a digital input signal.

FIG. 17 is a block diagram showing a conventional LED printer driving circuit.

FIG. 18 is a timing chart of each signal for explaining the operation of the conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Main frame 2 ... Main power supply 11 ... Microprocessor 12 ... Correction code storage ROM 13 ... LED printer head drive integrated circuit 14 ... Data shift register part 14a ... 1st clock terminal 14b ... Data terminal 14-1 to 14- m: D flip-flop 15: Latch circuit array unit 15-1 to 15-m: Latch circuit 15a: Latch terminal 16: Shift register unit for correction data 16a: Second clock terminal 16b: Correction data terminal 17: Output transistor control Circuit section 17-1 to 17-m Control and level shift circuit 17a Enable terminal 18 Output transistor section 18-1 to 18-m Switching circuit (current synthesis circuit) 18-1a Current output digital / analog conversion circuit (DAC) 19: LED array integrated circuit 19-1 to 1 9-m LED 20 Photosensitive drum 21-1 to 21-m Logical control circuit unit 22-1 to 22-m Level shift circuit unit F _OS1 Offset P-channel field effect transistor F _{T1 to} F _T30 P-channel field-effect transistors G _{1 to} G ₁₅ , G _OS1 ... Polysilicon gates 30, 31... Active area 32... Source electrode wiring 33... Drain electrode wiring 34 _pl . ... second gate wiring 37 ... third gate wiring 38 ... fourth gate wiring 39 ... gate oxide films 40 and 41 ... interlayer insulating film 42 ... protective film 50 ... input logic unit

[Procedure amendment]

[Submission date] January 19, 1999

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Name of invention

[Correction method] Change

[Correction contents]

Patent application title: Integrated circuit for supplying multiple output currents

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (11)

[Claims] 1. A multi-output current supply integrated circuit comprising a plurality of switching means for continuously controlling the current supply from a power supply to each driven element, wherein each switching means has a current capacity almost equal to each other. An integrated circuit for supplying multiple output currents, wherein the integrated circuit is a current combining circuit in which a plurality of unit switching units are connected in parallel. 2. The method according to claim 1, wherein, among the N unit switching units, the number of units belonging to the i-th group having the i-th digit of the n-bit digital control signal as a switching control input is 2 ^{i− One} , [Equation 1] An integrated circuit for supplying multi-output current, characterized in that: 3. The multi-output current supply according to claim 2, wherein each unit switching unit is a single field-effect transistor or a parallel connection circuit of a plurality of field-effect transistors adjacent to each other. For integrated circuits. 4. The integrated circuit for supplying multiple output currents according to claim 3, wherein the N unit switching units are formed in a parallel movement array having the same shape and the same pitch in one direction. . 5. The unit switching unit according to claim 4, wherein a unit switching unit belonging to a first group is located at the center of the translation array, and the unit switching unit of the first group is set as a symmetric axis, and the symmetric axis is set. , The unit switching section at a position away from the array by one end at a time is n → n−1 → n → n−2 →
n → ・ ・ ・ → n → 2 → n → ・ ・ ・ → n → n-2 → n → n
1. A multi-output current supply integrated circuit, wherein a left-right symmetric group pattern is formed in the order of -1 → n. 6. The field effect transistor according to claim 2, wherein each of said unit switching sections is a parallel connection circuit of two or more field effect transistors located symmetrically to each other, wherein said field switching transistors belong to different groups. An integrated circuit for supplying multiple output currents, wherein the integrated circuits are adjacent to each other. 7. A multi-output current supply integrated circuit according to claim 6, wherein all the field effect transistors are formed in a parallel movement array having the same shape and the same pitch in one direction. 8. The method according to claim 7, wherein a center of gravity (average position) of two or more field-effect transistors of the unit transistor unit belonging to the first group is located at the center of the translation array. The center of gravity of two or more field-effect transistors of the unit transistor section belonging to the same group is defined as n → n−1 → n → n− in a direction away from the symmetry axis by one to each end of the array. 2 → n → ・ ・ ・ → n → 2 → n → ・
A multi-output current supply integrated circuit characterized in that a symmetrical group pattern is formed in the order of → n → n−2 → n → n−1 → n. 9. The switching device according to claim 1, wherein each of said switching means has at least one offset field-effect transistor section connected in parallel to said current synthesis circuit. An integrated circuit for supplying multiple output currents. 10. A drive control device for a plurality of driven elements whose output intensity monotonically changes according to a supplied current value, the data control apparatus receiving a data signal for driving the plurality of driven elements, and receiving the data signal. A data latch unit that latches the data signal, receives the data signal latched by the data latch unit and a correction data signal used to correct the data signal, and based on these data signals, generates a corrected data signal. And a current supply unit that generates a multi-level current for driving the driven element, the current supply unit being controlled by the corrected data signal. A plurality of switching means for supplying a multi-level current to the driven element, wherein each of these switching means is substantially the same. A drive control device for a large number of elements, wherein the drive control device is a current combining circuit configured by connecting N unit switching units having the same current capacity in parallel. 11. A drive control device for a plurality of driven elements whose output intensity monotonically changes according to a supplied current value, wherein the data signal generates a data signal for driving the plurality of driven elements. Generating means; correction data signal generating means for generating a correction data signal used to correct the data signal; data latch means for receiving and temporarily storing the data signal; latched by the data latch means Receiving the corrected data signal and the corrected data signal, and generating a corrected data signal based on these data signals; and a controlled element controlled by the corrected data signal, the driven element And current supply means for generating a multi-level current for driving the multi-level current. Current combining circuit comprising a plurality of switching means for supplying a current to the driven element, each of these switching means being connected in parallel with N unit switching units having substantially the same current capacity. A drive control device for a large number of elements, characterized in that: