JPH11274906A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To significantly reduce power consumption of a data output circuit and to save the layout area. SOLUTION: A data output circuit consists of P-channel MOS transistors(TRs) T1, T2, N-channel MOS TRs T3, T4, and inverters Iv1-Iv5. The TRs T1-T4 are connected in series between the point of a power supply voltage Vcc and the point of a ground potential Vss, and a data signal DQ is outputted from a connecting pant between the TRs T2, T3. The TRs T1-T4 are controlled by a control signal HiZ and a data signal DOB from a control circuit. A gate length is halved without changing a gate width of each TR by connecting the TRs T1-T4 in series, and since a gate capacitance is reduced while the characteristics of an electrostatic breakdown strength is ensured and hot carrier effects, the power consumption is considerably reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and, more particularly, to a technology effective when applied to a data output circuit that greatly reduces power consumption.

[0002]

2. Description of the Related Art According to studies by the present inventor, a synchronous DRAM (Dynamic Random A) has been disclosed.
In a semiconductor integrated circuit device such as an access memory, a P-channel MOS (Met) is used as a data output circuit.
CMOS (Complementary MOS) in which an Al Oxide Semiconductor transistor and an N-channel MOS transistor are connected in series.
An output buffer having an inverter configuration is used.

This output buffer is, for example, read /
The control signal and the data signal output from the control circuit at the time of writing or the like are controlled by logic.

As an example describing in detail the output buffer provided in this type of semiconductor integrated circuit device, see, for example, CM published by Nikkan Kogyo Shimbun on September 29, 1987.
OS Device Handbook Editing Committee (ed.), "CMO
S Device Handbook "P136, P137
This document describes a configuration of a CMOS inverter circuit.

[0005]

However, the present inventor has found that the output buffer as described above has the following problems.

That is, a transistor of a CMOS inverter secures characteristics such as an electrostatic breakdown voltage and a hot carrier effect by increasing the gate length, and the gate width increases accordingly, so that the gate capacitance increases. However, there is a problem that power consumption is increased.

Further, a step-down voltage obtained by stepping down an operation power supply voltage by a step-down power supply is supplied to peripheral circuits and a memory array from the viewpoint of low power consumption and high-speed operation. A voltage conversion circuit for converting to an operation power supply voltage is required.

As a result, there are problems such as an increase in chip area, a decrease in operation speed due to voltage conversion, and an increase in power consumption.

An object of the present invention is to provide a semiconductor integrated circuit device capable of significantly reducing the power consumption of a data output circuit and reducing the layout area.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0011]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, in the semiconductor integrated circuit device according to the present invention, the first and second transistors, which are P-channel MOSs connected in series between the output terminal and the power supply voltage, are connected between the output terminal and the reference potential. N channel M connected in series to
A data output driver including third and fourth transistors made of OS is provided.

As a result, the gate length of each of the first to fourth transistors can be reduced to な く without changing the gate width, so that the drivability is reduced while ensuring the characteristics such as the electrostatic withstand voltage and the hot carrier effect. Thus, the gate capacitance driven by the data signal can be reduced.

In the semiconductor integrated circuit device according to the present invention, the first and fourth transistors are driven by a control signal for controlling output of data output, and the second and third transistors are driven by a data signal. Is what is done.

As a result, the capacity of the final stage of data output can be reduced, so that the data output can be speeded up.

Furthermore, the semiconductor integrated circuit device of the present invention
The second and third transistors are driven by a control signal for controlling output of data output, and the first and fourth transistors are driven by a data signal.

Thus, only the second and third transistors connected closest to the I / O terminal are turned on and off based on the data signal, so that the data output can be further speeded up.

Further, according to the semiconductor integrated circuit device of the present invention, there is provided a P-channel MOS connected between an output terminal and a power supply voltage.
And a sixth transistor comprising an N-channel MOS connected in series between the output terminal and a reference potential.
And a data output driver comprising a drive signal level converter for converting the level of a drive signal for driving the fifth transistor into a power supply voltage potential.

Further, according to the semiconductor integrated circuit device of the present invention,
The sixth transistor is driven by a drive signal having the same potential as a data signal, and drive signals of the fifth transistor and the sixth transistor are different.

As a result, the level conversion circuit provided in the preceding stage of the data output driver can be dispensed with, so that the data output can be speeded up and the layout area of the semiconductor chip can be reduced.

Furthermore, the semiconductor integrated circuit device of the present invention
Seventh and eighth transistors composed of P-channel MOSs connected in series between an output terminal and a power supply voltage, and N-channel MOSs connected in series between the output terminal and a reference potential
And a data output driver comprising a ninth and a tenth transistor composed of a transistor and a drive signal level converter for converting a drive signal for driving the ninth transistor into a power supply voltage level.

As a result, the gate length of each of the first to fourth transistors can be reduced to half without changing the gate width, so that the drivability is lowered while ensuring the characteristics such as the electrostatic breakdown voltage and the hot carrier effect. Without reducing the gate capacitance. Further, since the level conversion circuit provided in the preceding stage of the data output driver can be dispensed with, the speed of data output can be increased and the layout area of the semiconductor chip can be reduced.

Further, in the semiconductor integrated circuit device according to the present invention, the seventh and tenth transistors are driven by a control signal for controlling output of data output, and the eighth and ninth transistors are driven by data signals. Is what is done.

Further, the semiconductor integrated circuit device of the present invention
The seventh and eighth transistors are driven by drive signals having the same potential as the data signal, and drive signals of the seventh and eighth transistors are different from those of the ninth and tenth transistors.

As a result, the capacity of the final stage of the data output can be reduced, so that the speed of the data output can be increased.

Further, according to the semiconductor integrated circuit device of the present invention,
The eighth and ninth transistors are driven by a control signal for performing output control of data output, and the seventh and tenth transistors are driven.
Are driven by the data signal.

Thus, only the seventh and tenth transistors connected closest to the I / O terminal are turned on and off based on the data signal, so that the data output can be further speeded up.

As described above, the power consumption of the data output circuit can be significantly reduced without decreasing the drivability while securing the characteristics such as the electrostatic breakdown voltage and the hot carrier effect of the transistor.

[0029]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Embodiment 1) FIG. 1 is a circuit diagram of a data output circuit according to Embodiment 1 of the present invention, FIG. 2 is a circuit diagram of a level conversion circuit, and FIG. 3 is Embodiment 1 of the present invention. 6 is a timing chart of a data output circuit according to the first embodiment.

In the first embodiment, the synchronous D
A data output circuit provided in a semiconductor integrated circuit device such as a RAM includes transistors (first and second transistors) T1 and T2 that are P-channel MOS transistors and transistors (third and third transistors) that are N-channel MOS transistors.
Fourth transistor) T3, T4, inverters Iv1-
Iv5.

The transistor T1 and the transistor T2 are connected in series, and similarly, the transistor T3 and the transistor T4 are connected in series. Further, the other connection part of the transistor T2 and one connection part of the transistor T3 are connected, and the transistors T1 to T4 are respectively connected in series.

A power supply voltage V _CC, which is an operating voltage of the semiconductor integrated circuit device, is supplied to one connection portion of the transistor T1. The other end of the transistor T4 is connected to the ground potential V _SS is the reference potential.

A connection between the other connection of the transistor T2 connected in series and one connection of the transistor T3 serves as a data output, and is an I / O (output terminal) terminal of the semiconductor integrated circuit device. , And a data signal DQ is output from this I / O terminal. These transistors T1 to T4 constitute a data output driver.

Further, the gate of the transistor T1 has
The output of the inverter Iv1 is connected, and the output of the inverter Iv2 is connected to the gate of the transistor T2. The output of the inverter Iv3 is connected to the gate of the transistor T4, and the gate of the transistor T3 is connected to the output of the inverter Iv4 and the input of the inverter Iv2.

The input of the inverter Iv1 is connected to the output of the inverter Iv5.
5 is also connected to the input of the inverter Iv3.

The input of the inverter Iv4 is connected to receive a control signal HiZ output from the control circuit at the time of reading / writing, for example, and the input of the inverter Iv5 is connected to the data input. The connection is made such that a data signal (data signal) DOB, which is an inverted signal of the above, is input. The data output circuit is controlled by taking the logic of the control signal HiZ and the data signal DOB.

The amplitude of the control signal HiZ and the amplitude of the data signal DOB are the step-down voltage V _PERI which is stepped down from the power supply voltage V _CC and is supplied as an operating power supply to peripheral circuits and the like. Level conversion circuit LC as shown
Is provided before the data output circuit, and the level conversion circuit LC controls the control signal HiZ and the data signal DO.
B is converted to the power supply voltage V _CC amplitude.

Next, the operation of the present embodiment will be described with reference to the timing charts of FIGS.

In FIG. 3, from top to bottom,
The timing of the control signal HiZ output from the control circuit, the data signal DOB which is an inverted signal of the output data, and the data signal DQ output from the I / O terminal are shown.

When no data is output, the control signal HiZ is a Hi signal, and when data is output, the control signal HiZ is a Lo signal.

When the control signal HiZ of the Lo signal is output from the control circuit to the input portion of the inverter Iv4, the Hi signal which is the inverted signal is output from the inverter Iv4 to the gate of the transistor T3 and the input portion of the inverter Iv2. Is done. From the output section of the inverter Iv2, a Lo signal which is an inverted signal thereof is output to the gate of the transistor T2.

When the data signal DOB is a Lo signal, the output of the inverter Iv5 becomes a Hi signal,
v1 and Iv3 are input to the input unit. The outputs of the inverters Iv1 and Iv3 become Lo signals which are inverted signals thereof, and the Lo signals are input to the gates of the transistors T1 and T4.

Therefore, the transistors T1 to T3 are turned on and the transistor T4 is turned off.
A data signal DQ of a Hi signal is output from the I / O terminal.

Next, when the data signal DOB becomes a Hi signal, the output of the inverter Iv5 becomes a Lo signal, so that the outputs of the inverters Iv1 and Iv3 become Hi, respectively.
A signal is input to each gate of the transistors T1 and T4.

Therefore, the transistors T2 to T4 are turned on and the transistor T1 is turned off.
A data signal DQ of a Lo signal is output from the I / O terminal.

Thus, according to the first embodiment, the following effects can be obtained.

(1) Transistors T1 and T2 and transistors T3 and T4 are connected in series to form a CMOS
By configuring the data output circuit of the buffer, the gate length can be reduced to な く without changing the gate width of each transistor, so that the gate capacitance can be reduced.

(2) According to the above (1), it is possible to greatly reduce the low power consumption of the data output circuit without deteriorating the drivability while securing the characteristics such as the electrostatic withstand voltage and the hot carrier effect. it can.

(3) Further, since the capacity of the final stage in the data output circuit can be reduced, the speed of data output can be increased.

(Embodiment 2) FIG. 4 is a circuit diagram of a data output circuit according to Embodiment 2 of the present invention.

In the second embodiment, the data output circuit includes P-channel MOS transistors (first and second transistors) T5 and T6, and N-channel MOS transistors (third and fourth transistors).
Transistors) T7, T8, inverters Iv6 to Iv
10.

The transistor T5 and the transistor T6 are connected in series, and similarly, the transistor T7 and the transistor T8 are connected in series. The other connection of the transistor T6 and one connection of the transistor T7 are connected, and the transistors T5 to T8 are connected in series.

A power supply voltage V _CC, which is an operating voltage of the semiconductor integrated circuit device, is supplied to one connection of the transistor T5, and the other connection of the transistor T8 is connected to the ground potential V _SS .

A connection between the other connection of the transistor T6 connected in series and one connection of the transistor T7 serves as a data output, and is connected to the I / O terminal of the semiconductor integrated circuit device. Data signal DQ is output from this I / O terminal. Then, the transistors T5 to T8
Constitutes a data output driver.

Further, the gate of the transistor T5 has
The output of the inverter Iv6 is connected, and the output of the inverter Iv7 is connected to the gate of the transistor T6.

The output of the inverter Iv8 is connected to the gate of the transistor T7, and the gate of the transistor T8 is connected to the output of the inverter Iv10 and the input of the inverter Iv6.

The input of the inverter Iv6 is connected to the output of the inverter Iv10. Inverter Iv9
Is input to a data signal DO which is an inverted signal of data.
The connection is made so that B is input.

The output of the inverter Iv9 is connected to the respective inputs of the inverters Iv7 and Iv8.
The input portion of the inverter Iv10 is connected so that a control signal HiZ, which is an inverted signal of a control signal output from the control circuit at the time of reading / writing, is input. The data output circuit is controlled by taking the logic of the control signal HiZ and the data signal DOB.

Next, the operation of the data output circuit according to the second embodiment will be described with reference to FIG. The signal timing in this data output circuit is the same as the timing chart in FIG.

When no data is output, the control signal HiZ is a Hi signal, and when data is output, the control signal HiZ is a Lo signal.

The control signal HiZ of the Lo signal is output from the control circuit to the input of the inverter Iv10, and the Hi signal is input to the gate of the transistor T8 and the input of the inverter Iv6. From the inverter Iv6, a Lo signal which is an inverted signal thereof is output to the gate of the transistor T5. Therefore, at the time of data output, the transistors T5 and T8 are always ON.

When the data signal DOB is a Lo signal, the output of the inverter Iv9 becomes a Hi signal,
The outputs of v7 and Iv8 are the inverted signals L
The signal becomes the o signal, and the Lo signal is input to each gate of the transistors T6 and T7.

Since the transistors T5 to T7 are turned on and the transistor T8 is turned off, the I / O
A data signal DQ of a Hi signal is output from the terminal.

Next, when the data signal DOB is a Hi signal, the output of the inverter Iv9 becomes a Lo signal, so that the outputs of the inverters Iv7 and Iv8 become Hi signals and input to the respective gates of the transistors T6 and T7. Is done.

In this case, since the transistors T6 to T8 are turned on and the transistor T5 is turned off, the I / O
A data signal DQ of a Lo signal is output from the terminal.

As a result, in the second embodiment,
The following effects can be obtained.

(1) Each of the transistors T5 to T8
, The gate capacitance of each of which can be halved can be reduced.

(2) According to the above (1), it is possible to significantly reduce the low power consumption of the data output circuit without deteriorating drivability while securing characteristics such as electrostatic withstand voltage and hot carrier effect. it can.

(3) Further, since the capacity of the final stage of the data output can be reduced and the transistors T5 and T8 are normally turned on, the transistors T6 and T7 connected closest to the I / O terminal are based on the data signal DOB. ON, OFF
Therefore, data output can be further speeded up.

(Embodiment 3) FIG. 5 is a circuit diagram of a data output circuit according to Embodiment 3 of the present invention.

In the third embodiment, the data output circuit is a P-channel MOS transistor (fifth transistor) T9, an N-channel MOS transistor (sixth transistor) T10, and a NOR circuit. It is composed of NOR circuits N1 and N2, an inverter (drive signal level converter) Iv11, and an inverter Iv12.

The power supply voltage V _CC is supplied to the inverter Iv11 as an operation power supply, and the NOR circuit Nv
1, N2 and the inverter Iv12 have the power supply voltage V _CC
And a step-down voltage V _{PERI to} be supplied to peripheral circuits and the like as an operation power supply.

Further, the control signal HiZ and the data signal DOB input to the data output circuit are not level-converted and remain at the _reduced voltage V _PERI amplitude.

The transistor T9 and the transistor T10 are connected in series, and the transistors T9 and T10 are connected in series.
The connection portion 10 is a data output portion, which is connected to an I / O terminal of the semiconductor integrated circuit device, and a data signal DQ is output from the I / O terminal. And the transistor T
9, T10 and the inverter Iv11 constitute a data output driver.

The power supply voltage V _CC is supplied to one connection of the transistor T9, and the transistor T10
Is connected to the ground potential V _SS . The gate of the transistor T9 is connected to the inverter Iv11
The output of the NOR circuit N2 is connected to the gate of the transistor T10.

The control signal HiZ is input to one input of the NOR circuit N1, and the data signal DOB is input to the other input. The control signal HiZ is input to one input of the NOR circuit N2, and the output of the inverter Iv12 is connected to the other input. Also, the input portion of the inverter Iv12 includes:
The data signal DOB is input.

The signal for driving the last transistor T9 in the data output circuit is level-converted from the reduced voltage V _PERI amplitude to the power supply voltage V _CC amplitude by the inverter Iv11, and the signal for driving the transistor T10, that is, the NOR circuit N2 Output signal remains at the V _PERI amplitude.

Next, the operation of the data output circuit according to the third embodiment will be described with reference to FIG. The signal timing in this data output circuit is the same as the timing chart in FIG.

First, when data is not output, the control signal HiZ is a Hi signal, and when data is output, the control signal HiZ output from the control circuit is a Lo signal, and the NOR circuit N1, It is input to one input unit of N2.

When data signal DOB is Lo signal, NO
The Lo signal is input to the other input of the R circuit N1, the Hi signal is output from the output of the NOR circuit N1, and the Lo signal inverted by the inverter Iv11 is input to the gate of the transistor 9.

Since the output of the inverter Iv12 is also a Hi signal, the Lo signal is output to the output of the NOR circuit N2, and the Lo signal is input to the gate of the transistor T10. Therefore, the transistor T9 is turned on and the transistor T10 is turned off, so that the data signal DQ output from the I / O terminal becomes a Hi signal.

Next, when the data signal DOB is a Hi signal, a Hi signal is input to the other input of the NOR circuit N1, and a Lo signal is output from the output of the NOR circuit N1. Receives the Hi signal inverted by the inverter Iv11. The Hi signal input to the gate of the transistor T9 is level-converted from the step-down voltage V _PERI to the power supply voltage V _CC by the inverter Iv11.

Since the output of the inverter Iv12 is a Lo signal, a Hi signal is output to the output of the NOR circuit N2 and is input to the gate of the transistor T10. Therefore, the transistor T9 is turned off and the transistor T10 is turned on, so that the data signal DQ output from the I / O terminal is a Lo signal.

Thus, in the third embodiment, the following effects can be obtained.

(1) Since only the gate signal of the transistor T9 is converted from the step-down voltage V _PERI amplitude to the power supply voltage V _CC amplitude by the inverter Iv11, the level conversion circuit provided in the preceding stage of the data output circuit can be omitted.

(2) According to the above (1), the power consumption of the semiconductor integrated circuit device can be greatly reduced, and the area of the semiconductor chip can be reduced.

(3) Further, since only the gate signal of the P-channel MOS transistor T9 is level-converted to the _Vcc amplitude, the power consumption of the semiconductor integrated circuit device can be further reduced.

(Embodiment 4) FIG. 6 is a circuit diagram of a data output circuit according to Embodiment 4 of the present invention.

In the fourth embodiment, the data output circuit includes P-channel MOS transistors (seventh and eighth transistors) T11 and T12, N-channel MOS
(The ninth and tenth transistors) T
13, T14 and inverters (drive signal level conversion circuits) Iv13, Iv14, inverters Iv15 to Iv
17.

The inverters Iv13 and Iv14 are supplied with a power supply voltage V _CC as an operation power supply. The inverters Iv15 to Iv17 step down the power supply voltage V _CC and supply a step-down voltage to be supplied to peripheral circuits and the like as an operation power supply. Voltage V
_PERI is supplied.

The transistors T11 and T12
Are connected in series, and similarly, the transistor T13
And the transistor T14 are connected in series. Then, the other connection part of the transistor T12 and the other connection part of the transistor T13 are connected to form the transistor T1.
1 to T14 are connected in series.

The transistors T13, T14
Since the transistors T15 and T16 are connected in series, the gate length of each transistor is １ ／.

The connection between the transistors T12 and T13 serves as a data output section, and the I / O of the semiconductor integrated circuit device is provided.
Terminal, and a data signal DQ is output from the I / O terminal. These transistors T11 to T1
4 and inverters Iv13 and Iv14 constitute a data output driver.

At one connection of the transistor T11,
The power supply voltage V _CC is supplied, and the other connection of the transistor T14 is connected to the ground potential V _SS . The inverter Iv is connected to the gate of the transistor T11.
Thirteen outputs are connected, and the output of the inverter Iv14 is connected to the gate of the transistor T12.

As described above, the inverters Iv13, Iv
Since the power supply voltage V _CC is supplied only to the power supply 14, only the gate signals of the transistors T11 and T12 are level-converted to the power supply voltage V _CC amplitude.

The gate of the transistor T14 has
The output of the inverter Iv15 is connected, and the input of the inverter Iv14 and the output of the inverter Iv16 are connected to the gate of the transistor T13.

The input of the inverter Iv13 is connected to the input of the inverter Iv15 and the output of the inverter Iv17. A control signal HiZ output from the control circuit is input to an input portion of the inverter Iv16, and a data signal DOB, which is an inverted signal of data, is input to the inverter Iv17.

The control signal HiZ and the data signal DOB input to the data output circuit are not level-converted and remain at the _reduced voltage V _PERI amplitude.

Next, the operation of the data output circuit according to the fourth embodiment will be described with reference to FIG. The signal timing in this data output circuit is the same as the timing chart in FIG.

First, when data is not output, the control signal HiZ is a Hi signal, and when data is output, the control signal HiZ is a Lo signal.

When the control signal HiZ of the Lo signal is output from the control circuit to the input of the inverter Iv16,
The Hi signal is input to the gate of the transistor T13.
The Hi signal is also input to the input section of the inverter Iv14,
The gate of the transistor T12 has the inverted signal Lo.
A signal is input.

When the data signal DOB is a Lo signal, the output of the inverter Iv17 becomes a Hi signal, so that the outputs of the inverters Iv13 and Iv15 become Lo signals, respectively, and are input to the gates of the transistors T11 and T14.

Therefore, the transistors T11 to T13 are turned on and the transistor T14 is turned off.
A data signal DQ of a Hi signal is output from the I / O terminal.

Next, when the data signal DOB becomes a Hi signal, the output of the inverter Iv17 becomes a Lo signal, so that the outputs of the inverters Iv13 and Iv15 become Hi signals, respectively, and the respective gates of the transistors T11 and T14. Is input to The signal for driving the transistor T11 by the inverter Iv13 is a step-down voltage V
_The level is converted from the _PERI amplitude to the power supply voltage V _CC amplitude.

Therefore, since the transistors T12 to T14 are turned on and the transistor T11 is turned off,
A data signal DQ of a Lo signal is output from the I / O terminal.

Thus, according to the fourth embodiment, the following effects can be obtained.

(1) Since the transistors T11 and T12 and the transistors T13 and T14 are connected in series to form a data output circuit of a CMOS buffer, the gate length of each transistor can be reduced to 1/2. The gate capacitance can be significantly reduced.

(2) According to the above (1), it is possible to significantly reduce the low power consumption of the data output circuit without deteriorating drivability while securing characteristics such as electrostatic withstand voltage and hot carrier effect. it can.

(3) Further, the inverters Iv13, Iv
14 makes it possible to eliminate the need for level conversion circuit provided in the preceding stage of the data output circuit by the level conversion to a power supply voltage V _CC amplitude only gate signal of the transistor T11, T12 from the step-down voltage V _PERI amplitude.

(4) According to (3), the power consumption of the semiconductor integrated circuit device can be further reduced, and the area of the semiconductor chip can be reduced.

(5) Further, since the capacity of the final stage in the data output circuit can be reduced, the speed of data output can be increased.

In the fourth embodiment, when data is output, transistors T12 and T13 are always on, and transistors T11 and T13 are turned on by a change in data signal DOB.
Although the data signal DQ is output by turning ON / OFF the 14, for example, of the four transistors connected in series, two transistors connected closest to the I / O terminal are changed based on a change in the data signal. It may be turned on and off.

In this case, as shown in FIG. 7, the data output circuit is a P-channel MOS transistor (seventh,
Eighth transistor) T15, T16, N-channel MO
S transistor (ninth and tenth transistors) T1
7, T18, inverters (drive signal level converters) Iv18, Iv19, inverters Iv20 to Iv2
2.

The transistors T15 to T18 are connected in series, and the transistors T16 and T18 are connected in series.
17 is connected to the I / O terminal, and the data signal D
Q is output. In addition, these transistors T15 to T15
18 and inverters Iv18, Iv19 constitute a data output driver.

Since the transistors T15 and T16 and the transistors T17 and T18 are all connected in series, the gate length of each transistor is 1 / l.
It has a length of two.

The power supply voltage V _CC is supplied to one connection of the transistor T15, and the other connection of the transistor T18 is connected to the ground potential V _SS .

The output of the inverter Iv18 is the gate of the transistor 15, the output of the inverter Iv19 is the gate of the transistor T16, the output of the inverter Iv20 is the gate of the transistor T17, and the inverter Iv2.
2 are connected to the gate of the transistor T18, respectively.

Further, a power supply voltage V _CC is supplied to the inverters Iv18 and Iv19 as an operation power supply, and the gate signals of the transistors T15 and T16 are level-converted to the amplitude of the power supply voltage V _CC .

The output of the inverter Iv21 is connected to the inputs of the inverters Iv19 and Iv20, and the input of the inverter Iv18 is connected to the output of the inverter Iv22.

The input section of the inverter Iv21 has:
A data signal DOB, which is an inverted signal of data, is input,
A control signal DOB output from the control circuit is input to an input portion of the inverter Iv22.

When data is output,
The transistors T16 and T17 are always on, and the transistors T15 and T1 are changed by the change of the data signal DOB.
8 turns ON and OFF, and the data signal DQ is output.

As a result, each transistor T1
Since the gate length of 5 to T18 can be reduced to 1/2, the gate capacitance can be reduced without lowering the drivability while ensuring the characteristics of the electrostatic withstand voltage and the hot carrier effect. Power consumption can be significantly reduced.

[0124] Further, inverter IV18, IV19 by possible transistors T15, T16 of the level conversion circuit provided in the preceding stage of the data output circuit by only converting the level to the supply voltage V _CC amplitude gate signal required, the semiconductor integrated circuit device Power consumption can be reduced, and the area of the semiconductor chip can be reduced.

Further, since the transistors T15 and T18 are normally turned on and the transistors T16 and T17 connected closest to the I / O terminal are turned on and off based on the data signal DOB, the data output is further speeded up. be able to.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the gist of the invention. Needless to say, it can be changed.

[0127]

Advantageous effects obtained by typical ones of the inventions disclosed by the present application will be briefly described as follows.
It is as follows.

(1) According to the present invention, the gate length can be reduced to half without changing the gate width of the first to fourth transistors constituting the data output driver.
The gate capacitance can be reduced while ensuring characteristics such as electrostatic withstand voltage and hot carrier effect.

(2) In the present invention, the power consumption of the semiconductor integrated circuit device can be significantly reduced by the above (1).

(3) Further, in the present invention, the drive signal level converter for driving the fifth transistor provides
Since the level conversion circuit provided in the preceding stage of the data output driver can be dispensed with, the speed of data output can be increased, the layout area of the semiconductor chip can be reduced, and the power consumption can be reduced.

(4) According to the present invention, the seventh to the first
0, the gate length can be reduced to half without changing the gate width, and a level conversion circuit provided in the preceding stage of the data output driver is provided by a drive signal level conversion unit for driving the seventh and eighth transistors. Since it becomes unnecessary, the speed of data output can be increased, the layout area of the semiconductor chip can be reduced, and the power consumption of the semiconductor integrated circuit device can be significantly reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a data output circuit according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram of a level conversion circuit.

FIG. 3 is a timing chart of the data output circuit according to the first embodiment of the present invention.

FIG. 4 is a circuit diagram of a data output circuit according to a second embodiment of the present invention.

FIG. 5 is a circuit diagram of a data output circuit according to a third embodiment of the present invention.

FIG. 6 is a circuit diagram of a data output circuit according to a fourth embodiment of the present invention.

FIG. 7 is a circuit diagram of a data output circuit according to another embodiment of the present invention.

[Explanation of symbols]

T1 transistor (first transistor) T2 transistor (second transistor) T3 transistor (third transistor) T4 transistor (fourth transistor) T5 transistor (first transistor) T6 transistor (second transistor) T7 transistor ( Third transistor) T8 transistor (fourth transistor) T9 transistor (fifth transistor) T10 transistor (sixth transistor) T11 transistor (seventh transistor) T12 transistor (eighth transistor) T13 transistor (ninth transistor) T14 transistor (tenth transistor) T15 transistor (seventh transistor) T16 transistor (eighth transistor) T17 transistor (threeth transistor) T18 Transistor (tenth transistor) Iv1 to Iv10 Inverter Iv11 Inverter (drive signal level converter) Iv12 Inverter (drive signal level converter) Iv13 Inverter (drive signal level converter) Iv14 Inverter (drive signal level converter) ) Iv15 to Iv17 Inverter Iv18 Inverter (drive signal level converter) Iv19 Inverter (drive signal level converter) Iv20 to Iv22 Inverter N1, N2 NOR circuit DQ Data signal HiZ Control signal DOB Data signal (Data signal) V _CC power supply voltage V _SS ground potential V _PERI step-down voltage LC level conversion circuit

Claims (9)

[Claims] 1. A semiconductor device comprising: a first transistor and a second transistor each including a P-channel MOS connected in series between an output terminal and a power supply voltage; and an N-channel MOS connected in series between the output terminal and a reference potential. A semiconductor integrated circuit device provided with a data output driver including third and fourth transistors. 2. The semiconductor integrated circuit device according to claim 1, wherein said first and fourth transistors are driven by a control signal for controlling output of data output.
A semiconductor integrated circuit device, wherein the third transistor is driven by a data signal. 3. The semiconductor integrated circuit device according to claim 1, wherein said second and third transistors are driven by a control signal for controlling output of data output.
A semiconductor integrated circuit device, wherein the fourth transistor is driven by a data signal. 4. A fifth transistor comprising a P-channel MOS connected between an output terminal and a power supply voltage, and a sixth transistor comprising an N-channel MOS connected in series between said output terminal and a reference potential. A semiconductor integrated circuit device, comprising: a data output driver including a transistor and a drive signal level converter for converting a drive signal for driving the fifth transistor to a power supply voltage level. 5. The semiconductor integrated circuit device according to claim 4, wherein said sixth transistor is driven by a drive signal having the same potential as a data signal, and drive signals for said fifth transistor and said sixth transistor are provided. Wherein the semiconductor integrated circuit device is different. 6. A seventh and eighth transistor comprising a P-channel MOS connected in series between an output terminal and a power supply voltage, and an N-channel MOS connected in series between said output terminal and a reference potential. A data output driver comprising: ninth and tenth transistors; and a drive signal level conversion unit for converting a drive signal for driving the ninth and tenth transistors to a power supply voltage level. Semiconductor integrated circuit device. 7. The semiconductor integrated circuit device according to claim 6, wherein said seventh and eighth transistors are driven by a drive signal having the same potential as a data signal, and said seventh and eighth transistors are driven.
Wherein the drive signal of the transistor is different from that of the ninth and tenth transistors. 8. The semiconductor integrated circuit device according to claim 6, wherein said seventh and tenth transistors are driven by a control signal for controlling output of data output.
A semiconductor integrated circuit device, wherein the eighth and ninth transistors are driven by a data signal. 9. The semiconductor integrated circuit device according to claim 6, wherein said eighth and ninth transistors are driven by a control signal for controlling output of data output, and said seventh and tenth transistors are driven by a control signal. A semiconductor integrated circuit device driven by a data signal.