JPH11274870A - High frequency circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a high frequency circuit device equipped with a variable gain function capable of suppressing the degradation of device characteristics by preventing creeping of a high frequency component from an amplifier circuit on a final output stage to an attenuator. SOLUTION: This high frequency circuit device has two stages of attenuators A1 and A2 and two stages of amplifier circuits B1 and B2 arranged at prescribed positions on a chip CP together with respective pads, the attenuators A1 and A2 and the amplifier circuit B1 are connected to the same GND1 and the amplifier circuit B2 on the final output stage is connected to another GND2 independent of the GND1. Thus, since the creeping of high frequency component amplified by the amplifier circuit can be prevented, the degradation of isolation characteristics of the high frequency circuit device is suppressed and improvement in device characteristics can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a high-frequency circuit device, and more particularly to a high-frequency circuit device having a plurality of stages of attenuators and amplifiers.
The present invention relates to a high-frequency circuit device capable of improving device characteristics in a high-frequency circuit having a variable gain function.

[0002]

2. Description of the Related Art Conventionally, a block configuration as shown in FIG. 5 has been known as a high-frequency circuit having a variable gain function. In FIG. 5, A1 and A2 are attenuators having a variable gain function of giving a predetermined gain to a high-frequency input signal, and B1 and B2 receive the signal of the node N whose gain is variably adjusted by the attenuators A1 and A2, This is an amplifier circuit that amplifies signal power at a predetermined amplification degree.

Usually, since the gain variable width obtained by one attenuator is finite, a configuration in which a plurality of attenuators are provided as shown in FIG. 5 is generally employed to realize a desired gain. Also in the amplifier circuit,
Similarly, since the degree of amplification obtained by one amplifier circuit is finite, a configuration having a plurality of stages of amplifier circuits is employed to achieve desired signal amplification.

Further, the attenuator A1 and the amplifier circuit B1 are commonly connected to the same ground voltage GND1.
The attenuator A2 and the amplifier circuit B2 are commonly connected to the same ground voltage GND2. And the input terminal I
A high-frequency signal is sequentially input to the attenuators A1 and A2 via N, and then a high-frequency signal having a desired gain and amplified to a desired power is output from the output terminal OUT via the amplifier circuits B1 and B2. .

Next, a layout configuration of each circuit block shown in FIG. 5 on a chip will be described with reference to FIG. Here, a case where each of the above-described circuit blocks is formed as a monolithic circuit on the same chip CP will be described. As shown in FIG. 6, circuit blocks of attenuators A1 and A2 constituting a high-frequency circuit, and
Amplifying circuits B1 and B2 are formed in a predetermined arrangement on the same chip, and various pads PD1 to PD8 are formed outside these circuit blocks, that is, on the outer peripheral area of the chip.

The pads PD1 to PD8 are used to input / output signals and supply a power supply voltage to / from each circuit block from outside the chip. External pads (pins) provided on a package on which the chip is mounted as described later. Is connected by wire.
Specifically, a high-frequency signal input pad PD1 to which a high-frequency input signal is input, a high-frequency signal output / bias voltage application pad for outputting an amplified high-frequency output signal and applying a bias voltage to an output-stage amplifier circuit PD2
A gain variable control voltage application pad PAD3 to which a control voltage for variably controlling the gains of the attenuators A1 and A2 is applied; a bias voltage application pad PAD4 to apply a bias voltage to an amplifier circuit other than the output stage; and attenuators A1 and A2 GND pads PD5 and PD6 for supplying a ground voltage (GND) to each of
And a ground voltage (GND) to each of the amplifier circuits B1 and B2.
Amplifying circuit GND pads PD7 and PD8 for supplying
Are formed.

Next, the connection relationship between the pads PD1 to PD8 on the chip CP shown in FIG. 6 and the external terminals provided on the package will be described with reference to FIG. Since the chip CP in FIG. 7 has the same configuration as the chip CP shown in FIG. 6, only each PAD involved in connection with an external terminal is shown, and each circuit block is Illustration is omitted.

In FIG. 7, a package PK is provided with external terminals PN1 to PN6, an external terminal PN1 is a high-frequency signal input terminal, an external terminal PN2 is a high-frequency signal output / bias voltage application terminal, and an external terminal PN3 is a variable gain control. The voltage application terminal and the external terminal PN4 are set to function as bias voltage application terminals, and the external terminals PN5 and PN6 are set to function as GND terminals.

The pads PD1 to PD4 are connected to the external terminals PN1 to PD4 in a one-to-one correspondence by wire bonding or the like (L1 to L4), while the pads PD5 and PD7 are connected to a common external terminal PN5. The wiring is connected (L5, L7), and the pads PD6, PD8 are wiring connected to the common external terminal PN6 (L6, L8). The arrangement and connection relationship between the pads on the chip and the external terminals provided on the package are preliminarily arranged close to those important for the circuit characteristics such as input / output signals.
For the power supply voltage such as ND, the G closest to the GND pad
A configuration commonly connected to the ND terminal is generally adopted.

[0010]

In the high-frequency circuit device as described above, the attenuator A1 and the amplifying circuit B
1 GND pads PD5 and PD7 share a common GND terminal P
N5, while the GND pads PD6 and PD8 of the attenuator A2 and the amplifier circuit B2 are connected to another common GND.
Since it is configured to be connected to the terminal PN6, a high-frequency component flows from the amplifying circuit B2 side of the final output stage to the attenuator A2 via the GND terminal PN6, and causes deterioration of device characteristics as described below. Had a problem.

That is, the gain characteristic of the attenuator A2 which receives the sneak of high frequency components from the amplifier circuit B2 is shown in FIG.
As shown in (a), an inflection point X where the gain is significantly increased and decreased occurs in a specific gain variable control voltage Vgc region, and a region where the gain variable control voltage Vgc is low (a voltage region lower than the inflection point). Shows only a constant gain Gain, and no longer shows a variable gain characteristic. In particular, at the inflection point X of the gain change, the specific gain G
There is a problem that the gain variable control voltage Vgc with respect to ain is binary.

Here, the characteristic diagram of FIG. 8A shows a change in gain Gain when the input power value is kept constant and the gain variable control voltage Vgc is changed.
On the other hand, there is a close relationship between the distortion characteristic and the phase characteristic of the high-frequency circuit, and when the high-frequency component wraps around the attenuator A2 from the amplifier circuit B2, the gain variable control voltage Vgc is changed in the amplifier circuit B1. In this case, there are two types of power: normal power input via the attenuators A1 and A2, and power input via the attenuator A2 due to sneak from the amplifier circuit B2.

As described above, the signal 2 input to the amplifier circuit B1 is
Since a phase difference occurs between the two powers, the phase of the input power is distorted, and as shown in FIG. 8B, the distortion characteristic ACP when the gain variable control voltage Vgc is changed deteriorates (FIG. 8B Y) in)). Here, the characteristic diagram of FIG. 8B shows a change in the distortion characteristic ACP when the output power value is kept constant and the variable gain control voltage Vgc is changed.

A specific circuit configuration of such a deterioration of device characteristics due to the sneak of high-frequency components from the amplifier circuit at the final output stage will be described with reference to FIG. FIG.
FIG. 5 shows a specific circuit configuration of each circuit block of the attenuators A1 and A2 and the amplifier circuits B1 and B2 shown in FIG. In FIG. 9, attenuator A
1 includes a resistor R11 and field effect transistors (hereinafter simply referred to as FETs) Q11 and Q12, and an attenuator A2 includes a resistor R21, an FET Q21,
It has Q22.

On the other hand, the amplifier circuit B1 includes resistors R31 and R3.
2, an amplifier circuit B2 includes capacitors C31 and C32, and an FET Q31.
2. It has the capacitors C41 and C42 and the FET Q41. IN is a high-frequency signal input via the external terminal PN1, OUT / Vbi is a high-frequency signal output / applied via the external terminal PN2 and a bias voltage,
gc is a variable gain control voltage applied via the external terminal PN3, Vbi is a bias voltage applied via the external terminal PN4, and GND1 and GND2 are external terminals P, respectively.
This is a ground voltage (GND) applied via N5 and PN6.

Further, INV is an inverter circuit which receives the variable gain control voltage Vgc as an input. In such a circuit configuration, the variable adjustment of the gain is performed by the attenuator A
1, A2 series FETs Q12, Q22 and parallel FET Q1
1, performed by switching of Q21.

That is, the variable gain control voltage Vgc applied through the external terminal PN3 is connected to the series FET Q1.
2, applied to the gate terminal of Q22, and the parallel F of the attenuators A1 and A2 via the inverter circuit INV.
By being applied to the gate terminals of the ETQ11 and Q21, the series FET Q12 and Q22 and the parallel FET Q11,
The amount of the high-frequency signal flowing through Q21 is adjusted, and the gain is variably adjusted.

Here, the start voltage (variable gain control voltage Vgc) at which the gain can be variably adjusted as shown in FIG. 8A is determined by the threshold voltage (Vth) of the parallel FETs Q11 and Q21. The inflection point X as described above occurs near this voltage. For example, an inflection point X occurs around 0.7 to 0.9 V, which is a threshold voltage of a general FET.

As shown in FIG. 8A, the gain characteristic in the circuit configuration shown in FIG. 9 is obtained by changing the variable gain control voltage Vgc and decreasing the gain from the maximum gain region (the inflection point X and the inflection point X). It has been confirmed that the distortion characteristic ACP is deteriorated in the region between the maximum gain and the maximum gain as shown in FIG. That is, as described above, the power input to the amplifier circuit B1 is supplied to the external terminal PN1.
And the series FET Q of the attenuators A1 and A2
12, the normal terminal power applied through Q22 and the external terminal PN to which GND2 is applied by operating the FET Q21 of the attenuator A2 when varying the gain.
6, the amplifier circuit B via the FET Q21
2 and the power due to the high-frequency component wrapping around, and the distortion characteristic ACP deteriorates due to the phase difference between the two (Y in FIG. 8B).

An object of the present invention is to provide a variable gain function which solves the above-mentioned problems, prevents a high frequency component from flowing from an amplifier circuit at the final output stage to an attenuator, and suppresses deterioration of device characteristics. To provide a high-frequency circuit device.

[0021]

In order to achieve the above object, according to the first aspect of the present invention, there is provided a variable gain circuit for providing a gain to an input signal, and amplification of an output from the variable gain circuit. A plurality of stages of amplification circuits to be performed, and among the plurality of stages of amplification circuits, a final output stage amplification circuit is connected to an amplification circuit other than the final output stage and a power supply voltage terminal connected to the gain variable circuit. It is characterized by being connected to different independent power supply voltage terminals.

The invention described in claim 2 is the first invention.
In the high-frequency circuit device described above, the amplifier circuits other than the final output stage and the gain variable circuit are connected to the same power supply voltage terminal. According to a third aspect of the present invention, in the high frequency circuit device according to the first or second aspect, the gain variable circuit and the multi-stage amplifier circuit are provided on a chip in the same package. Features.

Further, the invention described in claim 4 is the third invention.
In the high-frequency circuit device described above, the variable gain circuit and the plurality of stages of amplifying circuits are provided on the same chip. According to a fifth aspect of the present invention, in the high-frequency circuit device according to the first, second, third or fourth aspect, a ground voltage is supplied to the power supply voltage terminal.

Such a connection structure of GND terminals reduces the number of pads on a chip due to the recent reduction in chip size of a semiconductor integrated circuit, and the number of external terminals due to a reduction in the size of a package on which the chip is mounted. And focuses only on the amplifier circuit at the final output stage, which is most affected by the sneak path of high-frequency components and most affects device characteristics.

According to the high-frequency circuit device according to the present invention, the GN to which the amplifier circuit at the final output stage of the high-frequency circuit device is connected
By configuring the D terminal independently of the GND terminal to which the other circuit block is connected, it is possible to prevent the high frequency component amplified by the amplifier circuit from wrapping around, and to reduce the signal reflection to the degree of signal amplification of the high frequency circuit. The device characteristics can be improved without deteriorating the isolation characteristics indicating the degree.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the high-frequency circuit device according to the present invention will be described below with reference to FIGS. In addition, about the structure equivalent to FIG. 5, the same code | symbol is attached | subjected and the description is abbreviate | omitted. As shown in FIG. 1, the high-frequency circuit device of the present embodiment has two-stage attenuators (variable gain circuits) A1 and A2 and two-stage amplifier circuits B1 and B2.
And the attenuators A1, A2 and the amplifier circuit B1 are connected to the same GND1, and the final output stage amplifier circuit B2
Are connected to a separate GND2 independent of GND1.

Each of the circuit blocks A1, A2, B1, and B2 applied to such a high-frequency circuit device is arranged together with each pad at a predetermined position on the chip CP, similarly to the prior art shown in FIG. Have been. That is, the number, type, and arrangement of the circuit blocks and pads are not different from those of the related art (see FIG. 6). Further, the number, type, and arrangement of external terminals provided on the package are not different from those of the related art (see FIG. 7).

Therefore, in the same chip configuration and package configuration as in the prior art, as shown in FIG. 2, the GND pads PD5, PD6 and PD7 on the chip CP are connected to a common external terminal (power supply voltage terminal) PN5. (L
5, L6, L7), and only the GND pad PD8 is connected to an external terminal (power supply voltage terminal) PN6 by wiring (L
The above connection relationship is realized only by changing the combination of the wiring connection between the GND pad and the external terminal, which is referred to as 8).

The connection relationship between the other pads PD1 to PD4 and the external terminals (PN1 to PN4) is the same as in the prior art. Next, a specific example of the circuit configuration of the high-frequency circuit device according to the present embodiment will be described with reference to FIG. FIG. 3 shows the attenuators A1 and A2 and the amplifying circuit B shown in FIG.
Each of the circuit blocks 1 and B2 is shown as a specific circuit configuration, and has substantially the same circuit configuration as that shown in FIG. Therefore, the same components as those in FIG. 9 will be described with the same reference numerals.

As shown in FIG. 3, the attenuators A1, A
2, an output from the inverter INV that receives the variable gain control voltage Vgc as an input,
11, parallel FET Q received at the gate electrode via R21
11 and Q21, and series FETs Q12 and Q22 that receive the variable gain control voltage Vgc at their respective gate electrodes and supply a high-frequency input signal to the source electrode side.

The amplifying circuits B1 and B2 are provided with an FET Q31 which receives a signal voltage supplied from the attenuator A2 via the capacitor C31 and a voltage determined by the resistor R32 at the gate electrode, and a FET C31 to the capacitor C4.
1 and a FET Q41 that receives, at its gate electrode, a signal voltage supplied through the gate electrode 1 and a voltage determined by the resistor R42.

The parallel F of the attenuators A1 and A2
One end of ETQ11, Q21 and FET of amplifier circuit B1
One end of Q31 is connected to a common external terminal PN5,
GND1 is applied via the external terminal PN5. On the other hand, one end of the FET Q41 of the amplifier circuit B2 is connected to the external terminal PN6, and GND2 is applied through the external terminal PN6.

The device characteristics in such a circuit configuration will be described with reference to FIG. According to the above-described circuit configuration, the external terminal PN6 to which the final output stage amplifier circuit B2 is connected and the other circuit blocks A1, A2, B
4 is independent of the external terminal PN5 and connected to different power supply voltages GND2 and GND1, so that high-frequency components from the amplifier circuit B2 are prevented from sneaking into the attenuator A2. As shown in the gain characteristic diagram of (a), at the inflection point of the gain change, the gain G
Ain does not change remarkably up and down, and the phenomenon that the variable gain control voltage Vgc generates two values is prevented.

The power input to the amplifier circuit B1 is:
Since the power due to the high-frequency component flowing from the amplifier circuit B2 via the attenuator A2 is prevented, the external terminal PN1
And the series FET Q of the attenuators A1 and A2
12, since only normal input power is applied via Q22, as shown in FIG. 4B, deterioration of the distortion characteristic ACP due to the phase shift is suppressed, and the distortion characteristic shows substantially linearity. Shows a good tendency.

By the way, in the high-frequency circuit devices shown in the prior art and the present embodiment, the high-frequency component wraps around the attenuators A1 and A2 also from the first-stage amplifier circuit B1, but the high-frequency component by the first-stage amplifier circuit B1 is reduced. ,
Since it is extremely weak compared to the high frequency component amplified by the amplifier circuit B2 at the final output stage, the influence on the device characteristics due to the wraparound is extremely small.

Therefore, in the present invention, in particular, only the GND pad of the amplifier circuit at the final output stage is connected to an external terminal different from other circuit blocks, and a separate ground voltage (GN
By supplying D2), the device characteristics as described above are remarkably improved. In addition,
In the above-described embodiment, in particular, a circuit configuration having a plurality of stages of attenuators and amplifier circuits has been described in detail. However, the present invention is not limited to such a circuit configuration, and a plurality of Needless to say, the present invention can be favorably applied to a circuit device having a circuit block, a multi-stage amplifier circuit in an output portion, and a restriction that the number of external terminals of a package cannot be increased. No, GND pad and external terminal (GND)
This is extremely useful because device characteristics can be improved with a simple configuration in which only the wiring connection between them is changed.

[0037]

As described above, according to the high-frequency circuit device according to the present invention, the GND terminal to which the amplifier circuit of the final output stage of the high-frequency circuit device is connected and the GND terminal to which other circuit blocks are connected. By configuring independently of
Since the sneak of the high frequency component amplified by the amplifier circuit can be prevented, deterioration of the isolation characteristics of the high frequency circuit device can be suppressed, and device characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a high-frequency circuit device according to the present invention.

FIG. 2 is a diagram illustrating a wiring connection example in the high-frequency circuit device according to the present invention.

FIG. 3 is a diagram showing an example of a circuit configuration in a high-frequency circuit device according to the present invention.

FIG. 4 is a diagram showing device characteristics in the high-frequency circuit device according to the present invention.

FIG. 5 is a block diagram showing a high-frequency circuit according to the related art.

FIG. 6 is a diagram showing an example of the arrangement of circuit blocks inside a chip.

FIG. 7 is a diagram illustrating a wiring connection example of a high-frequency circuit according to the related art.

FIG. 8 is a diagram illustrating device characteristics of a high-frequency circuit according to the related art.

FIG. 9 is a diagram illustrating a circuit configuration example of a high-frequency circuit having a variable gain function.

[Explanation of symbols]

 A1, A2 Attenuator B1, B2 Amplifier circuit CP chip PK package PD1-PD8 pad PN1-PN6 External terminal L1-L8 Wiring Vgc Gain variable control voltage Vbi Bias voltage GND1, GND2 Ground voltage

Claims (5)

[Claims] 1. A variable gain circuit that provides a gain to an input signal; and a multi-stage amplifier circuit that amplifies an output from the variable gain circuit. A high-frequency circuit device, wherein the amplifier circuit of the final output stage is connected to an independent power supply voltage terminal different from the power supply voltage terminal connected to the amplifier circuits other than the final output stage and the gain variable circuit. . 2. The high-frequency circuit device according to claim 1, wherein the amplifying circuits other than the final output stage and the gain variable circuit are connected to the same power supply voltage terminal. 3. The high-frequency circuit device according to claim 1, wherein said variable gain circuit and said plurality of stages of amplifier circuits are provided on a chip in the same package. 4. The high-frequency circuit device according to claim 3, wherein said variable gain circuit and said plurality of stages of amplifier circuits are provided on the same chip. 5. The high-frequency circuit device according to claim 1, wherein a ground voltage is supplied to said power supply voltage terminal.