JPH11274514A - Manufacture of thin film transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve characteristics of a thin film transistor used for a liquid crystal display. SOLUTION: A manufacturing step includes a step for forming a gate electrode on a substrate, a step for forming a gate insulating film covering the gate electrode, a step for forming an amorphous silicon layer on the gate insulating film, a step for forming a doped amorphous silicon layer on the amorphous silicon layer, a step for forming a source electrode and a drain electrode on both sides of the amorphous silicon layer on the doped amorphous silicon layer, a step for treating the doped amorphous silicon layer in a dry etching step, and a step for carrying out an oxygen plasma step.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a thin film transistor liquid crystal display.

[0002]

2. Description of the Related Art Recently, a thin film transistor liquid crystal display device, which has been gaining popularity as one of flat panel display devices, uses a hydrogenated amorphous silicon layer as a semiconductor layer of a thin film transistor. An n-type heavily doped amorphous silicon layer is used as a resistance contact layer for reducing the contact resistance with the source and drain electrodes formed in the semiconductor device. In the case of an etch-back type thin film transistor, the doped amorphous silicon layer is usually etched using the source electrode and the drain electrode as a mask, and both the source electrode and the drain electrode are etched in this process. Was.

[0003]

In order to solve such a problem, a doped amorphous silicon layer is etched using a photoresist pattern used for forming a source electrode and a drain electrode as a mask. Alternatively, a method of removing the photoresist pattern later can be used. However, in this case, there is another problem that the characteristics of the thin film transistor are deteriorated because the amorphous silicon layer is affected in the process of removing the cured photoresist pattern.

[0004] The present invention has been made in view of the above,
The purpose is to improve the characteristics of a thin film transistor used for a liquid crystal display device.

[0005]

In order to achieve the above object, the present invention provides a method for performing an oxygen or helium plasma process after dry-etching a doped amorphous silicon layer used as a resistance contact layer of a thin film transistor. I do.

Here, when the data wiring including the source electrode and the drain electrode used as a dry etching mask is made of molybdenum or a molybdenum alloy, a helium plasma process is performed, and when the data wiring is made of aluminum or an aluminum alloy, An oxygen plasma process is performed.

After etching the doped amorphous silicon layer, the helium or oxygen plasma treatment is performed in-situ without changing the vacuum state, thereby deteriorating the characteristics of the thin film transistor. To prevent corrosion of aluminum or aluminum alloy.

When dry-etching the doped amorphous silicon layer, hydrogen halide gas and CF ₄ ,
It is preferable to use at least one gas of CHF ₃ , CHClF ₂ , CH ₃ F and C ₂ F ₆ , especially HCl
It is preferable to use + CF ₄ gas.

When the data wiring is made of molybdenum or a molybdenum alloy, HCl + CF ₄ + O ₂ is used as a dry etching gas to which oxygen is added to prevent the deterioration of the characteristics of the thin film transistor.

[0010] The doped amorphous silicon layer can be etched using a photoresist pattern for forming a source electrode and a drain electrode or a source electrode and a drain electrode as a mask.

[0011]

Embodiments of the present invention will be described below in detail with reference to the drawings.

First, the structure of a thin film transistor substrate according to a first embodiment of the present invention will be described. FIG. 1 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention, and FIGS. 2 to 4 are II-II 'and III-II of FIG.
FIG. 4 is a sectional view taken along lines I ′ and IV-IV ′. Substrate 10
Above the gate line 20 and the gate electrode 2 which is a branch thereof
1, and a gate pattern including a gate pad 22 formed at an end of the gate line 20 is formed.
The gate electrode 21 and the gate pad 22 are composed of lower chromium films 211 and 221 and upper aluminum-neodymium alloy films 212 and 222, respectively, and the upper aluminum-neodymium alloy film 222 of the gate pad portion is removed. . Although not shown in the drawing, the gate line 20 is also formed of a double film of a chromium film and an aluminum-neodymium alloy film. Here, the gate pad 22 transmits an external scanning signal to the gate line 20.

A gate insulating film 30 is formed on the gate patterns 20, 21 and 22.
0 has a contact hole 72 exposing the chromium film 221 under the gate pad 22. A hydrogenated amorphous silicon layer 4 is formed on the gate insulating film 30 above the gate electrode 21.
Amorphous silicon layers 51 and 52 which are heavily doped with 0 and n ⁺ -type impurities and are hydrogenated are formed on both sides of the gate electrode 21.

A data line 60 is also formed vertically on the gate insulating film 30, and a data pad 63 is formed at one end thereof to transmit an image signal from below. A source electrode 61, which is a branch of the data line 60, is formed on the doped amorphous silicon layer 51, and a drain electrode is formed on the doped amorphous silicon layer 52 located on the opposite side of the source electrode 61. An electrode 62 is formed.
Data line 60, source electrode and drain electrode 61, 6
2. The data pattern including the data pad 63 is made of a molybdenum-tungsten alloy film.

The data patterns 60, 61, 62, 63 and the amorphous silicon layer 40 which cannot be covered by the data patterns
A protective film 70 is formed thereon. The protective film 70 has contact holes 72 and 7 exposing the chrome film 221 under the gate pad 22, the drain electrode 62 and the data pad 63.
1 and 73 are respectively formed.

Finally, the protective film 70 is connected to the drain electrode 62 through the contact hole 71 and is connected to the pixel electrode 80 made of ITO and the chrome film 221 under the exposed gate pad 22. A gate pad ITO electrode 81 for transmitting an external signal to the gate line 20 and a data pad ITO electrode 82 connected to the data pad 63 and transmitting an external signal to the data line 60 are formed.

Hereinafter, a method of manufacturing the thin film transistor substrate as shown in FIGS. 1 to 4 will be described. 5A to 8C are cross-sectional views illustrating a method of manufacturing a thin film transistor substrate according to an embodiment of the present invention. Reference numerals A, B, and C in the drawing numbers indicate a thin film transistor portion, a gate pad portion, and a data pad portion, respectively. The manufacturing method presented in this embodiment is a manufacturing method using five masks.

First, as shown in FIGS. 5A to 5C,
Chromium and aluminum-neodymium alloy are sequentially laminated on a transparent insulating substrate 10 and photo-etched using a first mask to form a double-layer gate pattern including a gate line (not shown), a gate electrode 21 and a gate pad 22. To form

The gate pattern can be formed of molybdenum, molybdenum-tungsten alloy, or the like.
It is also possible to form a double film of one of aluminum or an aluminum alloy and one of molybdenum or a molybdenum-tungsten alloy, or a double film of chromium and aluminum.

As shown in FIG. 6A, a gate insulating film 30 made of silicon nitride, a hydrogenated amorphous silicon layer 40, and a hydrogenated amorphous silicon layer heavily doped with n-type impurities. Then, the doped amorphous silicon layer 50 and the amorphous silicon layer 40 are photo-etched using the second mask. At this time, since the gate insulating film 30 is formed over the entire surface, the gate pad portion and the data pad portion are also covered with the gate insulating film 30, as shown in FIGS. 6B and 6C.

As shown in FIGS. 7A to 7C, a metal film such as molybdenum or a molybdenum-tungsten alloy is stacked on the doped amorphous silicon layer 50, and then wet-etched using a third mask. Data line (not shown), source electrode 61 and drain electrode 6
2. A data pattern including the data pad 63 is formed.

The data pattern can be made of various conductive materials such as chromium, tantalum, aluminum, and aluminum alloy, and can be formed of a double film combining chromium and molybdenum or one of molybdenum alloys. is there.

Next, source / drain electrodes 61, 62
Using the mask as a mask, the exposed doped amorphous silicon layer 50 is plasma dry-etched to separate both sides around the gate electrode 21, while the doped amorphous silicon layers 51 on both sides are The amorphous silicon layer 40 between 52 is exposed.

At this time, when the data pattern is formed using aluminum or an aluminum alloy, the exposed gate insulating film 30 and the data patterns 60, 61, 62,
63 and doped amorphous silicon layer 50
In order to control the etching rate for the doped amorphous silicon layer 50 and the amorphous silicon layer 40, a fluoride gas (SF ₆ ,
A mixed gas of CF ₄ or the like and a chloride gas (HCl, Cl ₂ or the like) is used. However, when such a gas, especially a chloride gas, is used, when the doped amorphous silicon layer is etched, the surface of the aluminum or aluminum alloy is exposed, so that the chloride gas remains or contacts. Corrosion of aluminum or aluminum alloy increases the possibility of disconnection of the wiring. In order to solve such problems, it is preferable to apply an oxygen plasma process.

FIG. 9 is a table showing the corrosion of the wiring made of aluminum or aluminum alloy with respect to the dry etching gas. As shown in FIG. 9, Cl ₂ + SF ₆ , HCl + SF ₆ , and HCl are used as dry etching gases.
When only + CF ₄ is applied, it indicates that corrosion occurs, and as a result of applying oxygen plasma using Cl ₂ + SF ₆ as a dry etching gas, no corrosion occurs.

From these results, it can be seen that when used as a dry etching gas containing a chloride gas, corrosion of aluminum or aluminum alloy can be prevented by performing an oxygen plasma process.
At this time, in the oxygen plasma process, CH ₄ , SF ₆ , C
A gas such as _{2 F 6, CHF 3, C} 2 F 8 can be included trace amounts.

FIGS. 10 and 11 are graphs showing voltage-current characteristics of the thin film transistor when the oxygen plasma process is performed. Here, the electric power when applying the oxygen plasma process is 500, 800, and 1000 watts, respectively.
ts, and the pressures are 400, 600, 800, respectively.
1000 mTorr.

As shown in FIGS. 10 and 11, when the oxygen plasma treatment is performed, the off current Ioff is 0.2 p.
A, the on-state current Ion was measured between 2.0 and 2.2 μA, the breakdown voltage Vth was measured between 3 and 3.7 V, and the slope was measured within the range of 99-101.

Therefore, from the results shown in FIGS. 9 to 11, when the oxygen plasma process is applied, the wiring made of aluminum or an aluminum alloy can be prevented from being corroded and the wiring can be prevented from being disconnected, and the characteristics of the thin film transistor do not deteriorate. It can be seen that good results are measured under the conditions.

As described above, the doped amorphous silicon layer is etched using the data pattern as a mask,
A method of applying an oxygen plasma process to prevent corrosion of aluminum or an aluminum alloy during dry etching is based on a liquid crystal display device employing a planar driving method, that is, a method of forming a substrate on one of two substrates. The present invention is similarly applied to a method for manufacturing a liquid crystal display device that drives liquid crystal using a common electrode and a pixel electrode. Further, the present invention can be similarly applied to a case where a data pattern is formed by a double film containing aluminum or an aluminum alloy. Here, the oxygen plasma process is performed in-situ (in-sit
u).

Further, the data pattern may be made of molybdenum or
When formed using a molybdenum-tungsten alloy,
Etching the doped amorphous silicon layer 50
For dry etching is molybdenum or molybdenum
N-tungsten alloy film is easily etched,
The etching rate will be 100 ° / min or less.
Thus, the etching gas must be selected. Halo
Hydrogen gas and CF _Four, CHF_Three, CHClF_Two, CH_Three
F and C_TwoF₆At least one of the gases
And especially CF_FourIt is preferable to use + HCl gas.

FIG. 12 is a table showing the volatilization and sublimation temperatures of the refractory metal halide under normal pressure, and FIG. 13 is a diagram showing a method of manufacturing a thin film transistor according to the first embodiment of the present invention. 4 is a table showing an etching rate of a tungsten alloy. FIG.
What is indicated by s in 2 is the sublimation temperature.

In the step of etching the doped amorphous silicon layer using the source / drain electrodes as masks, the doped hydrogenated amorphous silicon (n ⁺ aS
i: H) and hydrogenated amorphous silicon (intrinsic a-Si: H)
In order to ensure a sufficient selectivity with respect to a gate insulating film made of silicon nitride or the like, which is a lower film of the amorphous silicon layer, while ensuring a sufficient etching rate with respect to the fluoride gas (SF ₆ , CF ₄ Etc.) and chloride gas (HCl,
Must be used a mixed gas of Cl _2, etc.). However, as shown in FIG. 12, WF ₆ , which is a halogen compound of molybdenum or tungsten, which is a chemically resistant metal,
WCl ₆ , MoF ₆ , MoCl ₅ or WOF ₄ , WOCl ₄ , MoOF ₄ , MoOCl ₄ which is a halogen oxide compound
Since the evaporation temperature and sublimation temperature are low, a considerable amount of molybdenum-tungsten alloy film is simultaneously etched during the etching of amorphous silicon. Phenomena such as generation of foreign substances (particles) occur. On the other hand, silicon halide SiF ₄ , Si
The volatilization temperature of Cl ₄ is −85 ° C. and 60 ° C., which is very low. In the case of aluminum halide AlF ₃ and AlCl ₃ , the sublimation temperature is as high as 1290 ° C. and 180 ° C.

As shown in FIG. 13, when HCl + SF ₆ is used as a dry etching gas, 200 to 61
Data pattern 6 at an etching rate of about 0 ° / min
A large amount of molybdenum alloys 1 and 62 are etched,
150 to 320 ° / min when using l ₂ + SF ₆
Expressed the etching rate of the order.

Hydrogenated amorphous silicon can form a highly volatile substance in both the fluorine and chlorine plasma processes. However, as shown in FIG. 12, in the case of a molybdenum-tungsten alloy, fluoride MoF ₆ , MoOF ₄ ,
The volatilization temperature of WF ₆ and WOF ₄ is low, but chloride MoC
Since the volatilization temperatures of l ₅ , MoOCl ₄ , WCl ₆ , and WOCl ₄ are relatively high, they are weak to plasma processes using mainly fluorine compounds (especially SF ₆ ). Further, as shown in FIG. 13, a molybdenum - represents the tendency of the etching amount increases slightly when the tungsten content increases in tungsten alloy, which is tungsten hexafluoride WF ₆
Is lower than that of molybdenum fluoride MoF ₆ , which is consistent with the general expectation that the etch rate will increase as the tungsten content increases. SF ₆ + HCl compared to the case using SF ₆ + Cl ₂ gas
The etching amount in the case of using a gas is slightly smaller, because the HCl gas has a lower Cl ion generation rate than Cl ₂ . However, when SF ₆ gas is used as a source of fluorine ions, polymerization is not easily performed.
In each case, the molybdenum-tungsten alloy is etched more.

On the other hand, when CF ₄ + HCl gas is used,
The etching amount of the molybdenum-tungsten alloy can be reduced. FIG. 14 is a graph showing an etching rate of a molybdenum-tungsten alloy when CF ₄ + HCl gas is used. The etching conditions at this time were a pressure of 80 Pascal and a power of 800 watts, and CF ₄ + H
The flow rate of the Cl gas is 500 sccm.

As shown in FIG. 14, when HCl + CF ₄ is used as a dry etching gas, 15 to 80 ° C.
Data pattern 61 at an etching rate of about
62 molybdenum alloys were etched.

When these results are compared with FIG.
Cl + SF₆Or Cl_Two+ SF₆Than when using
It can be seen that a small amount is always etched. this is
HCl gas H is the main component of molybdenum-tungsten alloy
When the concentration of fluorine as an etching component is reduced,
In addition, a fluorocarbon polymer film [-(CF)
_n-] By enhancing the polymerization effect
That is, the etching rate is reduced. Also general
To CF_FourIf you use SF₆Compared to using gas
Slow etching rate. This is because such ionizing strips
By CF_FourSF compared to gas₆Free fluorine with more gas
By generating ions, fluorine ions under the same conditions
This is considered to be due to the difference in the concentration of Especially H
Formation of fluorocarbon polymer film when mixed with Cl gas
Is enhanced to lower the etching rate,
Molybdenum that etches at a carbon ratio (F / C)
In the case of Ngustene alloy, the etching rate sharply decreases
I do. Therefore, CF_FourWhen using + HCl gas,
Significant reduction in etching amount of butene-tungsten alloy
can do.

FIGS. 15 to 17 show CF as shown in FIG.
_{When the} amorphous silicon layer doped with ₄ + HCl gas was dry-etched, the etching rate and the uniformity according to the pressure, power, and flow rate were shown.

FIG. 15 is a graph in which the etching amount and the uniformity are measured while changing the pressure. The etching amount gradually increases with the increase in the pressure, and the uniformity greatly increases under the pressure of 800 mTorr. I understand.

As shown in FIG. 16, even when the power is increased, the etching amount gradually increases,
It can be seen that the uniformity is best when watts of power are used.

As shown in FIG. 17, when the flow rate of the CF ₄ + HCl gas is increased, the uniformity increases, and the flow rate becomes 60%.
This indicates that the etching amount becomes maximum at 0 sccm.

From the above results, even when a molybdenum-tungsten alloy is used as the data wiring under the condition of using CF ₄ + HCl gas, molybdenum-tungsten used as a mask during etching of doped amorphous silicon. 50% etching amount of alloy film
The following can be held.

FIG. 18 is a graph showing characteristics of a thin film transistor obtained by etching an amorphous silicon layer doped with CF ₄ + HCl gas. At a gate voltage of −5 V, the off-state current indicates 10 pA or more, and at a gate voltage of 20 V, the on-state current indicates a value of 4 μA or more. As a result, the current characteristics in the on state are good, but the current characteristics in the off state cannot provide satisfactory results. However, when the hydrogen plasma process is performed before depositing the protective film, the current characteristics in the off state can be recovered. This is because after the doped amorphous silicon layer is etched, a conductive layer is formed on the surface of the channel by ion diffusion of molybdenum or tungsten metal, formation of silicide, and redeposition of metal etching by-products. It is presumed that the interface characteristics of the channel portion were improved by being formed within several to several tens of millimeters and then being removed or diluted when performing the hydrogen plasma process.

Before depositing the protective film, the in-situ (in-s
Better results are obtained when performing a helium plasma step in itu).

FIG. 19 is a graph showing voltage-current characteristics of the thin film transistor when the helium plasma process is performed. As shown in FIG. 19, when the helium plasma treatment is performed, the same degree of Ioff improvement effect as when the hydrogen plasma treatment is performed can be obtained. That is, the Ioff current was reduced to 1 pA or less. In addition, when the helium plasma treatment was performed, a decrease in Ion characteristics that occurred when the hydrogen plasma treatment was performed did not appear. This is a condition in which HCl + CF ₄ gas is used to protect a metal wiring while forming a large amount of a carbon polymer and to etch a silicon film using fluorine radicals. It is impossible to prevent the characteristics of the thin film transistor from deteriorating. To this end, the polymer solidified during etching must be weakened and then removed through a cleaning process and an annealing process. The results shown in FIG. 19 confirm this fact, and FIG.
The type and amount of the compound confirmed immediately after etching under the etching conditions using + CF ₄ gas are shown. As can be seen from FIG. 20, Mo ions occupy the largest amount, and MoO, M
Compounds such as oH and MoC are detected. Such compounds serve to protect the wiring while being generated and volatilized, thereby reducing the amount of etching and causing a phenomenon that the characteristics of the thin film transistor are deteriorated by such compounds.

The above-mentioned method, that is, the hydrogen or helium plasma treatment method is a step which is performed secondarily in order to prevent a characteristic deterioration of the thin film transistor after performing the dry etching step. However, the degradation of the characteristics of the thin film transistor can be prevented only by the dry etching process. At this time, the dry etching gas is a gas obtained by mixing a chlorine-based gas, a fluorine-based gas, and oxygen,
More preferably, HCl + CF ₄ + O ₂ gas is used. This will be described in detail.

FIG. 21 and FIG. 22 show molybdenum-oxide when the step of dry-etching the amorphous silicon layer doped with HCl + CF ₄ gas is repeatedly performed.
4 is a graph showing an etching amount of a tungsten alloy and an etching rate of an amorphous silicon layer. FIG. 21 corresponds to FIG.
This is a result of performing the test at a higher pressure than in the case of (1).

Here, the abscissa indicates the number of times dry etching was performed, the results of 15 measurements, the right side of the ordinate indicates the etching rate of the amorphous silicon layer, and the left side of the ordinate indicates molybdenum-tungsten. The amount of etching of the alloy is indicated by resistance.

As shown in FIGS. 21 and 22, by repeatedly performing the dry etching several times, the etching rate of the amorphous silicon layer is reduced, and the etching amount of the molybdenum-tungsten alloy is reduced. Is determined to be lower. This is because when dry etching is performed, a large amount of polymer is formed and a compound containing molybdenum is formed. Is prevented from being etched. At this time, a conductive film is formed by redeposition of a by-product of metal etching. As shown in FIG. 22, when the pressure is lowered, the polymer is discharged more smoothly than when the pressure is high,
The etching rate of the amorphous silicon layer is 700 ° / min.
As described above, it is shown that the case is improved as compared with the case of FIG. However, the molybdenum-containing compound is not removed even under the condition of low pressure, so that the thin-film transistor Ioff
The properties could not be improved. HCl to improve this
Oxygen was added to the + CF ₄ gas.

FIGS. 23 to 26 show that when oxygen is added to HCl + CF ₄ gas, the amorphous silicon layer and the molybdenum
4 is a graph and a chart in which the etching amount of a tungsten alloy is measured. 23 and 24 show that HCl is 200 scc.
m and CF ₄ are 50 sccm. FIGS. 25 and 26 show HCl at 200 sccm and CF _{4 at} 200 sccm.
m. Here, the pressure is 400 mTorr, the power is 800 watts, the time is the same under the same conditions of 60 sec, and the amount of oxygen is 20 to 5 in the range of 0 to 100 sccm.
The etching ratio and etching amount of each of 0 and 100 sccm were measured.

First, as shown in FIGS. 23 and 24,
589 and 650 ° when the oxygen amount is 20 sccm
/ Min, 50 and 100 sccm
When the etching rate was increased, the etching rate of the amorphous silicon layer and the etching rate of the molybdenum-tungsten alloy showed a large difference from each other, indicating that the etching selectivity increased.
Here, since the etching rate is indicated by a negative value,
It can be seen that a large amount of polymer is formed. Through this,
It can be seen that as the amount of oxygen gas increases, the etching selectivity between the amorphous silicon layer and the molybdenum-tungsten alloy improves.

Hereinafter, as shown in FIGS. 25 and 26,
It can be seen that even when the CF ₄ gas is increased to 200 sccm, the etching selectivity between amorphous silicon and molybdenum-tungsten alloy is improved, and when the amount of oxygen is increased, the etching amount of molybdenum-tungsten is increased. It was shown to decrease. Oxygen amount is 1
It can be seen that a large amount of polymer is formed when the flow rate is 00 sccm.

After all, the amount of oxygen is in the range of 100 sccm or less.
And CF_FourBy adjusting the amount of gas, amorphous
Silicon and molybdenum or molybdenum-tungsten
It can be seen that a good etching selectivity of the alloy can be obtained.
You. At this time, the flow rate of oxygen is CF _FourLess than 1/5 of the flow rate
Preferably it is.

FIGS. 27 and 28 are graphs showing characteristics of a thin film transistor when HCl + CF ₄ + O ₂ is used as a dry etching gas. Here, the pressure is 40
0 mTorr, power 800 watts, HCl 200 s
ccm, CF ₄ is 200 sccm, O ₂ is 100 sccm
Hereinafter, the test was performed under the condition of 80 sec.

As shown in FIGS. 27 and 28, Iof
The worst value of the f characteristic is measured when the helium plasma treatment is performed and oxygen is not added, and is the best when oxygen is added. Ion characteristics are also good when oxygen is added, and the threshold voltage is the highest.

FIG. 29 shows the amount of etching of the molybdenum-tungsten alloy and the etching of the amorphous silicon layer when the process of dry-etching the amorphous silicon layer doped with HCl + CF ₄ + O ₂ gas is repeatedly performed. It is the graph which showed the speed.

Here, the abscissa indicates the number of times the dry etching has progressed, and the result of 15 measurements is shown. The right side of the ordinate is the etching rate of the amorphous silicon layer, and the left side of the ordinate is molybdenum-tungsten. The amount of etching of the alloy is indicated by resistance.

As shown in FIG. 29, HCl + CF ₄ +
When performing dry etching using O ₂ gas,
The resistance of molybdenum-tungsten alloy and the etching rate of amorphous silicon are different each time. This is shown in FIG.
1 and 22 are significantly different.

Through these results, HCl + CF ₄ +
When performing dry etching using O ₂ gas,
The characteristics of the thin film transistor can be improved by one dry process without performing additional plasma treatment. In addition, it is possible to prevent a decrease in the etching rate of amorphous silicon and the etching amount of molybdenum or molybdenum alloy, which occur as the number of steps increases.

Next, as shown in FIGS. 8A to 8C,
After the protection layer 70 is stacked, the contact hole 71 for exposing the drain electrode 62 is formed by photo-etching with the insulating layer 30 using a fourth mask, and the gate pad 22 and the data pad 63 are also exposed. At this time, the aluminum-neodymium alloy film 222 in the upper layer of the gate pad 22 is not suitable as a material for the pad and is removed together to expose the lower chromium film 221.

Finally, as shown in FIG. 2 to FIG.
TO is laminated and dry-etched using a fifth mask to form a pixel electrode 80 connected to the drain electrode 62 through the contact hole 71, and an ITO electrode for a gate pad connected to the gate pad 22 and the data pad 63, respectively. 81 and a data pad ITO electrode 82 are formed.

If the upper layer of the gate pad 22 is formed of a molybdenum alloy film, it is not necessary to remove the upper layer of the gate pad.

Unlike the first embodiment of the present invention, the helium plasma process may be performed after the doped amorphous silicon layer is etched using the photoresist pattern as a mask and the photoresist pattern is removed. It is. A second embodiment of the present invention provides such a manufacturing method.

FIG. 30 is a sectional view showing a method of manufacturing a thin film transistor according to a second embodiment of the present invention. In the second embodiment of the present invention, as shown in FIG. 30, data patterns 610 and 620 are formed by patterning a metal film made of a molybdenum alloy by a wet etching method using a photoresist 900 as a mask. Next, in order to prevent the data patterns 610 and 620 from being etched, the doped amorphous silicon layer 500 is etched using the photoresist 900 as a mask without removing the photoresist 900 to form a dry etching gas. It was used HCl + SF _6.

Here, since the photoresist 900 was not removed, the molybdenum alloy of the source / drain electrodes 610 and 620 was not etched, but one side face between the source / drain electrodes 610 and 620 separated on both sides was removed. The part is etched and the source / drain electrode 61
A non-linear pattern is formed between the 0, 620 and the underlying amorphous silicon layer.

In such a manufacturing method, an ashing step using an oxygen gas is added in order to remove the photoresist 900 which has been hardened by dry etching, and an in-situ step is performed after the ashing step. The helium plasma process is performed in-situ.

FIG. 31 is a table showing the results of experiments using various conditions in order to compare the etching amount of the doped amorphous silicon layer, and FIG. 32 shows the results under the same conditions as in FIG. EDS of formed thin film transistor
(Electric data systeem) shows test results. EDS
The test was performed on the electrical characteristics after panel manufacture, that is, TF
Ioff, Ion, Vth, and Grad of the characteristics of T
event, resistance, capacitance, etc.
group) to evaluate the characteristics and performance of the panel, where Ioff indicates the amount of current flowing to the drain when a gate voltage of -5V and a source / drain voltage of 10V are applied. Is smaller, and Ion indicates the amount of current flowing to the drain when a gate voltage of 20 V and a source / drain voltage of 10 V are applied. The larger the value, the more advantageous. Vth is a threshold voltage, and Gradient indicates the slope of a straight line for obtaining the threshold voltage. The electron mobility can be calculated based on these values, and FIG. 33 is a table showing this.

As shown in FIG. 31, condition 1 is a case where the photoresist on the data pattern is removed first, the doped amorphous silicon layer is etched, and a helium plasma process is performed. At this time, the doped amorphous silicon layer was etched by 1,283 °. Condition 2 and Condition 3 are similar to Condition 1, in which the photoresist is removed first, and then the doped amorphous silicon layer is etched using CF ₄ + HCl gas.
Either an ashing process is performed to check whether the characteristics of the thin film transistor are changed by the ashing (condition 2), or a helium plasma process is performed in-situ after the ashing (condition 3). In each case, the etching amount of the doped amorphous silicon layer was 1,289 °.

Conditions 4 to 6 all relate to the case where the doped amorphous silicon layer is etched using this photoresist pattern as a mask while the photoresist pattern provided for forming the data pattern is left. is there. Condition 4 is a case where the doped amorphous silicon layer is etched, and the ash process using oxygen gas is performed without performing the helium plasma process. The silicon layer was etched to about 1,154 to 1,167 °. Condition 5 is a case in which the doped amorphous silicon layer is etched using CF ₄ + HCl gas, and is ashed and then a hydrogen plasma process is performed. The etching amount is 1,166
Was Å. Finally, after etching the doped amorphous silicon layer using CF ₄ + HCl gas, ashing is performed using oxygen gas, and helium plasma treatment is performed in-situ. , 114-1
This indicates that the doped amorphous silicon layer of about 211 ° was etched.

Next, the EDS test results shown in FIG. 32 show that the current in the off state is 1 pA or less in all cases except for the condition 4. The best result is obtained when the on-state current is 4 μA under the condition 6 in which the helium plasma process is performed in-situ. The threshold voltage was 2.48 to 2.5 for the conditions 3 and 6 in which the helium plasma process was performed.
Gradient, which is about 9 and relatively low as compared with other cases, and is a gradient of a straight line for obtaining a threshold voltage, gradually increases from condition 1 to condition 6. The contact resistance is lower in the conditions 1 to 3 where the photoresist is removed first than in the conditions 4 to 6 where the doped amorphous silicon layer is etched using the photoresist as a mask. On the contrary, the resistances of the source / drain wirings are opposite, and the conditions 4 to 6 in which the doped amorphous silicon layer is etched using the photoresist as a mask are compared with the conditions 1 to 3 in which the photoresist is removed first. Low.

The electron mobility can be calculated based on the EDS test result as shown in FIG. The electron mobility is represented by the following equation. Mobility (μfe) = (2 * (Grad) ² *
L) / (W * Cj) Here, L and W indicate the length and width of the channel of the thin film transistor, respectively. As shown in FIG. 33, the width of the gate wiring measured in the inspection after cleaning is 9.231 μm in the conditions 1 to 3, and 9.095 μm in the conditions 4 to 6, and the width of the data wiring is 9.095 μm. Width is 8.847μ
m. Cj indicates the capacitance per unit area. The width and length of the designed channels are 14 μm and 3.5 μm, respectively, and the actually measured width and length of the channels are 12.847 μm and 4.47 μm in the conditions 1 to 3.
653 μm, and 12.8 in the case of the conditions 4 to 6.
70 μm and 4.630 μm.

When the electron mobilities of the conditions 1 to 6 are respectively calculated by using such data and the above-described electron mobility calculation formula, as shown in FIG.
It can be seen that the maximum value appears between 937 and 0.961.
Since this is calculated using the measured value, an error may occur, but the result is similar to the experimental result described above.

[0074]

As described above, after the doped amorphous silicon layer is dry-etched using the data pattern or the photoresist pattern for forming the data pattern as a mask, the helium plasma process is performed in situ. By performing the above, it is possible to prevent the current characteristics in the off state from decreasing while maintaining the current characteristics in the on state of the thin film transistor. In addition, by using HCl + CF ₄ + O ₂ gas as a dry etching gas, the characteristics of the thin film transistor can be improved in one dry etching process without performing an additional plasma process, and a repetitive etching process is performed. However, it is possible to prevent the etching rate of amorphous silicon and the etching amount of molybdenum or molybdenum alloy from decreasing. Further, by performing the oxygen plasma process, it is possible to prevent corrosion of wiring made of aluminum or an aluminum alloy.

[Brief description of the drawings]

FIG. 1 is a layout view of a thin film transistor substrate according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along the line II-II ′ of FIG.

FIG. 3 is a sectional view taken along the line III-III 'of FIG.

FIG. 4 is a sectional view taken along the line IV-IV ′ of FIG. 1;

FIG. 5 is a cross-sectional view illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

FIG. 6 is a sectional view illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

FIG. 7 is a cross-sectional view illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

FIG. 8 is a cross-sectional view illustrating a method of manufacturing a thin film transistor substrate according to a first embodiment of the present invention.

FIG. 9 is a table showing the presence or absence of corrosion of aluminum wiring with respect to a dry etching gas.

FIG. 10 is a graph showing characteristics of a thin film transistor according to power and pressure under oxygen plasma conditions.

FIG. 11 is a graph showing characteristics of a thin film transistor according to power and pressure under oxygen plasma conditions.

FIG. 12 is a table showing the volatilization and sublimation temperatures of refractory metal halides under normal pressure.

FIG. 13 illustrates a method of manufacturing a thin film transistor according to a first embodiment of the present invention.
4 is a chart showing an etching rate of W.

FIG. 14 is a graph illustrating an etching rate of MoW with respect to another dry etching gas in the method of manufacturing a thin film transistor according to the first embodiment of the present invention.

FIG. 15 is a graph showing the MoW etching rate and the uniformity measured by changing the pressure.

FIG. 16 is a graph showing the MoW etching rate and the uniformity measured by changing the power.

FIG. 17 is a graph showing the MoW etching rate and the uniformity measured by changing the flow rate.

FIG. 18 is a graph showing characteristics of a thin film transistor before and after hydrogen plasma processing.

FIG. 19 is a graph showing characteristics of the thin film transistor after the helium plasma treatment.

FIG. 20 is a graph showing types and amounts of ions detected in a process of manufacturing the thin film transistor according to the first embodiment of the present invention.

FIG. 21 illustrates an etching amount of a molybdenum-tungsten alloy and an etching rate of an amorphous silicon layer when a process of dry-etching an amorphous silicon layer doped with HCl + CF ₄ gas is repeatedly performed. It is a graph.

FIG. 22 shows an etching amount of a molybdenum-tungsten alloy and an etching rate of an amorphous silicon layer when a process of dry-etching an amorphous silicon layer doped with HCl + CF ₄ gas is repeatedly performed. It is a graph.

FIG. 23: When oxygen is added to HCl + CF ₄ gas,
4 is a graph and a chart in which the etching amounts of an amorphous silicon layer and a molybdenum-tungsten alloy are measured.

FIG. 24: When oxygen is added to HCl + CF ₄ gas,
4 is a graph and a chart in which the etching amounts of an amorphous silicon layer and a molybdenum-tungsten alloy are measured.

FIG. 25: When oxygen is added to HCl + CF ₄ gas,
4 is a graph and a chart in which the etching amounts of an amorphous silicon layer and a molybdenum-tungsten alloy are measured.

FIG. 26: When oxygen is added to HCl + CF ₄ gas,
4 is a graph and a chart in which the etching amounts of an amorphous silicon layer and a molybdenum-tungsten alloy are measured.

FIG. 27 is a graph showing characteristics of a thin film transistor when HCl + CF ₄ + O ₂ is used as a dry etching gas.

FIG. 28 is a graph showing characteristics of a thin film transistor when HCl + CF ₄ + O ₂ is used as a dry etching gas.

FIG. 29 is a graph showing an etching amount of a molybdenum-tungsten alloy using a gas of HCl + CF ₄ + O ₂ and an etching rate of an amorphous silicon layer.

FIG. 30 is a cross-sectional view illustrating a process of manufacturing a thin film transistor according to a second embodiment of the present invention.

FIG. 31 is a table showing a manufacturing method according to a second embodiment of the present invention and an etching amount of the doped amorphous silicon layer according to the manufacturing method.

FIG. 32 is a table showing an EDS test result of the thin film transistor according to the second embodiment of the present invention.

FIG. 33 is a table showing calculated electron mobilities of a thin film transistor according to a second embodiment of the present invention;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Substrate 20 Gate line 21 Gate electrode 22 Gate pad 30 Gate insulating film 50, 51, 52 Doped amorphous silicon layer 40 Amorphous silicon layer 60 Data line 61 Source electrode 62 Drain electrode 63 Data pad 70 Protective film 71 , 72, 73 Contact hole 80 Pixel electrode 81 ITO electrode for gate pad 82 ITO electrode for data pad 211, 221 Chromium film 212, 222 Aluminum-Neodymium alloy film 900 Fort resist

Claims (21)

[Claims] A step of forming a gate electrode on the substrate; a step of forming a gate insulating film covering the gate electrode; and a step of forming an amorphous silicon layer on the gate insulating film on the gate electrode. Forming a doped amorphous silicon layer on the amorphous silicon layer; and forming source electrodes on both sides of the amorphous silicon layer around the amorphous silicon layer. A method of manufacturing a thin film transistor, comprising: forming a drain electrode; dry etching the doped amorphous silicon layer; and performing an oxygen plasma process. 2. The method of claim 1, wherein the oxygen plasma process is performed in situ after the dry etching step. 3. The method according to claim 2, wherein the source electrode and the drain electrode are formed of a single film of aluminum or an aluminum alloy or a double film containing the same. 4. The method according to claim 3, wherein the pressure in the step of performing the oxygen plasma is 1000 mTorr or less. 5. The method according to claim 4, wherein the power in the step of performing the oxygen plasma process is 1000 watts or less. 6. The method according to claim 5, wherein the etching gas used in the dry etching step includes Cl gas. 7. The thin film transistor according to claim 6, wherein in the step of performing the oxygen plasma process, CH ₄ , SF ₆ , C ₂ F ₆ , CHF ₃ , and C ₂ F ₈ gases can be added. Production method. 8. A step of forming a gate electrode on the substrate, forming a gate insulating film covering the gate electrode, and forming an amorphous silicon layer on the gate insulating film on the gate electrode. Forming a doped amorphous silicon layer on the amorphous silicon layer; forming a source electrode and a drain electrode on the doped amorphous silicon layer; Dry etching the doped silicon layer using HCl + CF ₄ + O ₂ gas using the drain electrode as a mask. 9. The method according to claim 8, wherein the source electrode and the drain electrode are formed of a single film of molybdenum or a molybdenum-tungsten alloy or a double film containing them. 10. The flow rate of said O ₂ is 1/5 of said CF ₄ flow rate.
The method for manufacturing a thin film transistor according to claim 8, wherein: 11. The method according to claim 8, wherein the flow rate of the O ₂ is 100 sccm or less. 12. forming a gate electrode on the substrate, forming a gate insulating film covering the gate electrode, and forming an amorphous silicon layer on the gate insulating film on the gate electrode. Forming a doped amorphous silicon layer on the amorphous silicon layer; and forming source electrodes on both sides of the amorphous silicon layer around the amorphous silicon layer. A method of manufacturing a thin film transistor, comprising: forming a drain electrode; dry etching the doped amorphous silicon layer; and performing a helium plasma process. 13. The helium plasma process is performed in situ after the dry etching step.
3. The method for manufacturing a thin film transistor according to item 1. 14. The method according to claim 13, wherein the source electrode and the drain electrode are formed of molybdenum or a molybdenum-tungsten alloy. 15. The method according to claim 14, wherein in the dry etching step, CF ₄ + HCl is used as an etching gas. 16. A step of forming a gate electrode on a substrate, forming a gate insulating film covering the gate electrode, and forming an amorphous silicon layer on the gate insulating film on the gate electrode. Forming a doped amorphous silicon layer on the amorphous silicon layer; depositing a metal film on the doped amorphous silicon layer; photoresist on the metal film Forming a pattern; forming a source electrode and a drain electrode by etching the metal film using the photoresist pattern as a mask; removing the photoresist pattern; and forming the source electrode and the drain electrode. Performing a dry etching of the doped amorphous silicon layer using the mask as a mask and a helium plasma process. The method of manufacturing the thin film transistor including a floor, a. 17. The helium plasma process is performed in situ after the dry etching step.
3. The method for manufacturing a thin film transistor according to item 1. 18. The method according to claim 17, wherein the source electrode and the drain electrode are formed of molybdenum or a molybdenum-tungsten alloy. 19. A step of forming a gate electrode on a substrate, forming a gate insulating film covering the gate electrode, and forming an amorphous silicon layer on the gate insulating film on the gate electrode. Forming a doped amorphous silicon layer on the amorphous silicon layer; depositing a metal film on the doped amorphous silicon layer; photoresist on the metal film Forming a pattern; forming a source electrode and a drain electrode by etching the metal film using the photoresist pattern as a mask; and forming the doped amorphous silicon using the photoresist pattern as a mask. Dry etching the layer; removing the photoresist pattern; and performing a helium plasma process. The method of manufacturing a thin film transistor including. 20. The helium plasma process is performed in situ after the dry etching step.
3. The method for manufacturing a thin film transistor according to item 1. 21. The method according to claim 20, wherein the source electrode and the drain electrode are formed of molybdenum or a molybdenum-tungsten alloy.