JPH11273393A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize high speed memory access while reducing design cost by comparing an input address with the address of a failure memory cell stored in a address register circuit if arrival of input address is detected at the time of memory access and designating access to any one of a memory cell array or a redundant memory cell depending on the comparison results. SOLUTION: Each row redundant circuit 32- 0, 32- 1, 32- 2, 32- 3 is provided with a circuit for detecting arrival of address. When arrival of a specified address is detected by the address arrival detecting circuit, the row redundant circuit 32- 0, 32- 1, 32- 2, 32- 3 outputs a redundant control signal for designating whether a redundant memory cell is selected or not to a word line driver. The word line driver selects a normal or a redundant word line depending on the redundant control signal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a so-called redundant function, in which, in addition to a normal memory cell array, a redundant memory cell for replacing a defective memory cell in the normal memory cell array is provided.

[0002]

2. Description of the Related Art In recent years, with the advance of semiconductor fine processing technology, high integration of semiconductors has progressed, and large capacity semiconductor memory devices have been put to practical use. On the other hand, as the storage capacity of the memory chip increases, the probability of occurrence of defective memory cells tends to increase, which causes a decrease in the manufacturing yield of the memory chip. For this reason, in order to remedy defective memory cells that cause a reduction in manufacturing yield, a so-called redundant function is provided in which a memory cell capable of replacing a defective memory cell in a circuit is provided in a memory chip in advance, and the defective memory cell is replaced as necessary. Is generally applied to a semiconductor memory device.

The remedy of a defective memory cell is performed for each memory cell or for each memory cell array in one row or one column along a word line or a bit line in a memory array. Further, there is a block-by-block repair method in which a regular memory block including a defective memory cell is replaced by a redundant memory block including the same number of redundant memory cells. As an example, replacement of a memory cell in a row along a word line or a column along a bit line including a defective memory cell in a normal memory cell array registers a defective address in a redundant decoder that selects a spare word line or a spare bit line. It is done by doing. The registration of the address is usually performed by a method such as programming with a laser or electrically blowing a fuse.

FIGS. 5 and 6 show an example of a semiconductor memory device provided with a redundancy function. FIG. 5 is a circuit diagram showing a configuration example of a semiconductor memory device having a row redundancy circuit. As shown, the semiconductor memory device has four memory cell arrays 25_0, 25_1, 25_2, and 25_3. Each memory cell array is composed of, for example, a plurality of memory cells arranged in a matrix. Memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line. The plurality of word lines arranged in parallel are connected to word line drivers 24_0, 24_1, 24_2, and 24_3, respectively. A plurality of bit lines arranged crossing the word lines are connected to a sense amplifier. FIG.
, Word lines, bit lines and sense amplifiers are omitted. Further, in an actual semiconductor memory device, the number of memory cell arrays is not limited to four, and any number of memory cell arrays may be provided as needed.

[0005] Memory cell arrays 25_0, 25_1, 2
In 5_2 and 25_3, in addition to the normal memory cells described above, redundant memory rows each including redundant memory cells are provided.
For example, a plurality of rows are arranged. The redundant memory cells arranged in each redundant memory row are connected to one redundant word line. In FIG. 5, word line drivers 24_0, 24_1, 24_2 and 24_3 are
Each of the memory cell arrays 25_0, 25_1, 25
_2 and 25_3 are provided to drive the word lines and redundant word lines. The redundant word lines are driven by row redundant circuits 22_0 and 22_, respectively.
1, 22_2 and 22_3.

The row decoder 21 outputs a predecode signal PRD for controlling the word line drivers 24_0, 24_1, 24_2 and 24_3 according to a row address ROWADR input from the outside. The predecode signal PRD includes, for example, a plurality of bits, and is output to each word line driver and the address arrival detection circuit 23, respectively. Word line driver 24_
Each of 0, 24_1, 24_2 and 24_3 receives the predecode signal PRD from the row decoder 21, selects one of a plurality of word lines according to the predecode signal PRD, and activates it. For example, since a boosted voltage generated by a booster circuit (not shown) is applied to a selected word line, writing, reading or erasing can be performed on each memory cell connected to the selected word line. .

The memory cell arrays 25_0, 25_1, 2
When defective memory cells are detected in 5_2 and 25_3, the addresses of the defective memory cells are registered in the row redundant circuits 22_0, 22_1, 22_2 and 22_3 by programming. As shown in FIG. 5, the predecode signals PRD from the row decoder 21 correspond to the row redundancy circuits 22_0, 22_1, 22_2 and 2 respectively.
2_3. These row redundant circuits compare the registered address of the defective memory cell with the input predecode signal PRD, and instruct access to the redundant memory cell according to the comparison result.

For example, in the row redundancy circuit 22_0,
As a result of comparing the address of the defective memory cell of the memory cell array 25_0 with the predecode signal PRD,
If they match, the word line driver 24_0
Outputs a control signal instructing access to the redundant memory. The word line driver 24_0 does not select a normal word line according to a control signal from the row redundant circuit 22_0, but selects a redundant word line instead. By this control, when a defective memory cell in the memory cell array is selected by the input address, access to the defective memory cell is prohibited, and access to the redundant memory cell is performed instead. realizable.

FIG. 6 shows a specific configuration example of the row redundancy circuit. As shown, the row redundancy circuit of this example receives a memory enable signal ME and a redundancy enable signal RE, and outputs a redundancy control signal RDE0 for selecting a redundancy word line to a word line driver. As shown, pMO
S transistor Q10 is connected between power supply voltage V _CC and node NDa
And its gate has a redundant enable signal R
E is applied. Before the memory access, the redundancy enable signal RE is held temporarily in the low level, the transistor Q10 is turned on, and node NDa is precharged by the power supply voltage V _CC, a high level, for example, the power supply voltage V _CC or near Retained on level.

The node NDa has a plurality of fuses F0, F
, FN and nMOS transistor Q10_0,
, Q10_N are grounded.
These transistors Q10_0, Q10_1,.
For example, each bit of the predecode signal PRD from the row decoder 21 is input to the gate of 10_N. As described above, when a defective memory cell is detected in the memory cell array, programming is performed according to the address of the defective memory cell. Therefore, the fuses F0, F1,.
A predetermined one of the FNs is disconnected. That is, the address of the defective memory cell is stored in the row redundancy circuit by cutting the fuse in programming.

At the time of memory access, the node N is controlled according to the address of the defective memory cell stored in the fuse circuit and the predecode signal PRD from the row decoder 21.
The level of Da is set, and the level of redundancy control signal RDE0 is set according to the level of node NDa.

When a defective memory cell in the memory cell array is designated by the input address, the level of the node NDa is maintained almost immediately after the precharge. That is, the node NDa is kept at the high level. Therefore, when the memory enable signal ME switches to the high level, the redundancy control signal RDE0 switches from the low level to the high level. In response, the word line driver selects and activates the redundant word line connected to the redundant memory cell instead of the word line connected to the defective memory cell. Conversely, when the input address is an address other than the address registered in the fuse circuit by the above-described programming, the node NDa is discharged through a predetermined fuse and transistor, and thus is held at a low level. In this case, the redundancy control signal RDE0 is kept at a low level, and a normal word line is selected. As described above, the row redundancy circuits 22_0, 22
_1, 22_2, and 22_3 are provided, and programming is performed in accordance with the defective memory cells found in the memory cell arrays 25_0, 25_1, 25_2, and 25_3, so that at the time of memory access, a redundant memory cell is selected instead of the defective memory cell. Therefore, defective memory cells can be relieved, and the yield of semiconductor memory devices can be improved.

[0013]

In the semiconductor memory device having the above-mentioned redundancy function, when the memory is replaced by the redundancy circuit, the operation timing of the redundancy circuit and the normal circuit becomes an important point. I have. For example, when a defective memory cell in a memory cell array is specified by an input address, a redundant control signal for selecting a redundant word line is output by a redundant circuit, and the word line driver selects a redundant word line in response. Conversely, when there is no need to replace the redundant memory, there is no instruction to select a redundant word line, and the word line driver selects a normal word line. The fuse circuit requires time to determine whether or not to select a redundant memory. During this time, the word line driver must be set to a standby state. Also, in a manner similar to the above, when performing column redundancy, the column redundancy circuit needs time to determine whether or not to perform redundancy, during which time a column selection circuit for selecting a bit line waits. Must be set to state.

As shown in FIG. 5, for example, an address arrival detection circuit 23 is provided to control the operation timing of each word line driver. The address arrival detection circuit 23 is provided at the latest position in time, and when detecting that the predecode signal PRD from the row decoder 21 has arrived, the row redundancy circuits 22_0, 22_
1, 22_2 and 22_3, word line driver 24
_0, 24_1, 24_2, and a signal ENB for activating 24_3 are output.

However, in the method of controlling the operation timing by providing the address arrival circuit as described above, extra time is required. As a result, there is a disadvantage that it is difficult to set an optimal timing, which is an obstacle to speeding up memory access.

Further, as one of the conventional means, an optimal timing is set by a circuit simulation. The purpose of this method is to set an optimum operation time in a circuit simulation without using the address arrival detection circuit. In this case, the accuracy largely depends on the accuracy of the simulation file and the accuracy of the transistor model. Further, in this method, it is difficult to make a setting corresponding to a parametric used in the system LSI. The parametric technique automatically generates memories of different sizes according to user requirements. For example, when 1 Mbit to 4 Mbit can be designated, each circuit must be designed. When the address arrival detection circuit is used, the time to be set differs depending on the capacity of the memory, so that the timing must be set for each circuit at the time of circuit design. is there.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to increase the speed of memory access and reduce the design cost of a memory core used in an LSI, thereby facilitating optimal timing setting. It is to provide a semiconductor memory device.

[0018]

In order to achieve the above object, a semiconductor memory device of the present invention has a redundant memory cell in which a defective memory cell in a normal memory cell array is replaced, and registers an address of the defective memory cell. By doing so, a semiconductor memory device that accesses the redundant memory cell instead of the defective memory cell at the time of memory access, an address registration circuit that stores the address of the defective memory cell by the address registration, When the arrival of the input address is detected, the input address is compared with the address of the defective memory cell stored in the address registration circuit, and one of the memory cell array and the redundant memory cell is determined according to the comparison result. And a redundancy control circuit for instructing access to the data.

More specifically, in the semiconductor memory device according to the present invention, a plurality of memory cells are arranged in a matrix, and a plurality of word lines and each word line commonly connected to the memory cells arranged in each row are provided. A memory cell array having a plurality of bits commonly connected to memory cells arranged in a column, and a plurality of redundant memory cells replacing the memory cells form a matrix having at least one row. A redundant memory cell array having at least one commonly connected redundant word line, and an address registration circuit that stores an address of the defective memory cell by address registration when a defective memory cell is detected in the memory cell array. At the time of memory access, when the arrival of the input address is detected, the input address is stored in the address registration circuit. And a redundancy control circuit for instructing access to either the memory cell array or the redundant memory cell array in accordance with the result of the comparison. When access to the cell array is instructed, one of the plurality of word lines is selected according to the input address, a predetermined activation voltage is applied to the selected word line, and the redundancy control is performed. A word line driver for selecting a predetermined redundant word line according to the input address and applying a predetermined activating voltage to the selected redundant word line when access to the redundant memory cell array is instructed by a circuit; .

In the present invention, preferably, the redundancy control circuit includes an address arrival detection circuit for detecting that the input address has arrived, and the defective address stored in the input address and the address registration circuit. A comparison circuit that compares the address of the memory cell; and an output timing control circuit that outputs a comparison result of the comparison circuit according to an output signal of the address arrival detection circuit.

In the present invention, preferably, the comparison circuit has a precharge circuit for setting an output node to a predetermined precharge potential before accessing the memory, and stores the data in the address registration circuit when accessing the memory. The output node is set to either the precharge potential or a common potential different from the precharge potential according to the address of the defective memory cell and the selection signal from the row decoder.

Further, in the present invention, the address registration circuit is connected between a fuse circuit composed of a plurality of fuses commonly connected to the output node and each of the fuse circuits and the common potential. A plurality of transistors each having a gate to which a selection signal from the row decoder is applied, and the address registration is performed by a predetermined fuse of the fuse circuit according to an address of the defective memory cell in the memory cell array. Is performed by fusing.

According to the present invention, in a semiconductor memory device provided with a redundancy function, a regular memory cell array and a redundancy control circuit for selecting the redundant memory cell array are provided, and further, a defective memory cell in the regular memory cell array is provided. Is recorded by the redundant registration circuit. The redundancy control circuit is provided with an address arrival detection circuit for detecting whether or not the redundancy address has reached the redundancy control circuit. When the address arrival detection circuit detects that a predetermined redundancy address has reached at the time of memory access. A comparison result between the address of the defective memory cell registered in the address registration circuit and the input address is output. Access to the normal memory cell array or the redundant memory cell array is determined according to the output comparison result, and the normal memory cell or the redundant memory cell is selected according to the input address, and writing is performed on the selected memory cell. , An operation such as reading or erasing is performed.

For this reason, the result of the redundancy judgment is output at the optimal timing, and the memory cell is accessed according to the output result of the redundancy judgment. Further, in a semiconductor memory device having a plurality of memory cell arrays, a redundant memory cell array and a redundant control circuit are provided for each memory cell array, and each redundant control circuit is provided with an address arrival detection circuit for detecting arrival of an address. In each memory cell array, the redundancy judgment result of the redundancy control circuit is optimally output at the operation timing, respectively,
Since the access to the normal memory cell array or the redundant memory cell array is performed according to the output result, the optimal operation timing can be set in each memory cell array, and the memory access can be speeded up. Also,
When designing a memory core used in a system LSI by the parametric method, a plurality of memory cores are automatically generated, and even when designing with different memory sizes, the optimum operation timing in each memory core can be automatically designed. In addition, it is possible to reduce design man-hours and design costs.

[0025]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device having a redundancy function according to the present invention.
The semiconductor memory device of the present embodiment is, for example, a DRAM (Dy
namic Random Access Memory). This DRAM
Are a row address buffer 1, a row decoder 2, a row redundancy circuit 3, a word line driver 4, a memory cell array 5, a sense amplifier 6, an input / output buffer (I / O buffer) 7, a control circuit 8, a column redundancy circuit 9, and a column. It comprises an address buffer 10, a column decoder 11, and a column switch driver 12.

As shown in the figure, the semiconductor memory device of the present embodiment has a row redundancy circuit 3 for performing control for replacing a normal word line with a redundant word line and a column redundancy circuit for performing control for replacing a normal bit line with a redundant bit line. A circuit 9 is provided for each. By using these redundancy control circuits, when a defective memory cell exists in the memory cell array 5, the address of the defective memory cell is registered in the row redundant circuit 3 and the column redundant circuit 9, respectively, so that the defective memory cell can be replaced at the time of memory access. Access to the redundant memory cell.

The memory cell array 5 in the present embodiment is composed of, for example, a plurality of memory cell arrays. In each memory cell array, a plurality of memory cells are arranged in a matrix, memory cells in the same row are connected to the same word line, and memory cells in the same column are connected to the same bit line. Each of the plurality of word lines is connected to a word line driver 4, and each of the plurality of bit lines is connected to a sense amplifier 6 through a not-shown column switch (column selection gate). The column switch is composed of a plurality of switches arranged for each bit line, and each switch is a column switch driver 1
2 controls the on / off state. When the switch is controlled to the ON state, a corresponding bit line is connected to the sense amplifier 6. That is, the bit line is selected by the column switch driver 12. Further, although not shown in FIG. 5, each memory cell array has
Redundant memory cells that replace defective memory cells in regular memory cells are arranged. The redundant memory cells constitute, for example, a redundant memory cell array. In the redundant memory cell array, redundant memory cells in the same row are connected to the same redundant word line, and redundant memory cells in the same column are connected to the same redundant bit line. I have.

The row address buffer 1 comprises a plurality of externally input row addresses AX0, AX1,.
AXn is held and output to the row decoder 2. The row decoder 2 generates a decode signal for selecting a word line according to a row address from the row address buffer 1,
It is supplied to the row redundancy circuit 3 and the word line driver 4. The row redundancy circuit 3 performs address registration according to the address of a defective memory cell in the memory cell array 5. The address registration is performed, for example, by blowing a predetermined fuse in a fuse circuit provided in the row redundancy circuit 3 with a laser beam or the like. The address of the defective memory cell is stored in the row redundancy circuit 3 by the address registration. When a defective memory cell in the memory cell array 5 is specified at the time of memory access, the decode signal from the row decoder 2 matches the address registered in the row redundancy circuit 3. When detecting the coincidence, the row redundancy circuit 3 outputs to the word line driver 4 a redundancy control signal for selecting the redundancy word line specified by the registered address instead of the regular word line.

The word line driver 4 includes a row decoder 2
And a word line or a redundant word line is selected according to a signal from row redundancy circuit 3. For example, when a normal memory cell is specified by an input address, the word line driver 4 selects a word line connected to the specified memory cell in accordance with a decode signal from the row decoder 2 and selects the selected word. For example, a high voltage generated by a booster circuit (not shown) is applied to the line to activate the word line. On the other hand, when a defective memory cell is designated by the input address, the word line driver 4
In response to the redundant control signal from the CPU, the selected redundant word line is selected and activated without selecting the normal word line.

The column address buffer 10 stores a plurality of externally input column addresses AY0 and AY.
, AYm are output to the column decoder 11. The column decoder 11 includes a column address buffer 1
A column decode signal for selecting a bit line is generated according to the column address starting from 0, and is supplied to the column redundant circuit 9 and the column switch driver 12. In the column redundancy circuit 9, for example, the address is registered in accordance with the address of the defective memory cell in the memory cell array 5, similarly to the row redundancy memory circuit 3. When a defective memory cell in the memory cell array 5 is specified at the time of memory access, the column decode signal from the column decoder 11 and the address registered in the column redundant circuit 9 match. When detecting the coincidence, the column redundancy circuit 9 outputs a column redundancy control signal for causing the column switch driver 12 to select the redundant bit line specified by the registration address instead of the regular bit line.

The column switch driver 12 selects a bit line or a redundant bit line according to a signal from the column decoder 11 and the column redundant circuit 9. As described above, a switch is arranged for each bit line of the memory cell array 5, and each bit line is connected to the sense amplifier 6 via the switch. Similarly, a switch is provided for each redundant bit line, and each redundant bit line is connected to the sense amplifier 6 via the switch. The column switch driver 12 outputs a control signal for controlling the ON / OFF state of each switch. For example, when a normal bit line is selected by the column addresses AY0, AY1,..., AYm, the column switch driver 12
A predetermined switch is controlled to be on according to a column decode signal from the column decoder 11. Therefore, the designated bit line is connected to the sense amplifier 6. on the other hand,
When the bit line to which the defective memory cell is connected is specified by the column address, the column decode signal from the column decoder 11 matches the address registered in the column redundancy circuit 9. When the column redundancy circuit 9 detects the coincidence, the column switch driver 1
2 outputs a column redundancy control signal for selecting a redundant bit line specified by a registered address instead of a regular bit line.

The sense amplifier 6 detects the potential of the selected bit line or redundant bit line, and determines the data stored in the selected memory cell or the redundant memory cell according to the detected potential. The input / output buffer 7 holds data read by the sense amplifier 6 at the time of reading, and outputs the held data to the data buses IO0, IO1,..., IOk. At the time of writing, the input / output buffer 7 holds the write data transferred from the data buses IO0, IO1,..., IOk, and switches the held write data to a switch set to the ON state by the sense amplifier 6 and the column switch driver 12. To the selected bit line or redundant bit line.

As described above, at the time of memory access, the word line specified by the row addresses AX0, AX1,..., AXn is selected, and the column addresses AY0, AY
The bit line specified by Y1,..., AYm is selected. For this reason, the memory cell arranged at the intersection of the selected word line and bit line is set as the selected memory cell, and writing or reading is performed on the selected memory cell. on the other hand,
When the selected memory cell is a defective memory cell, a redundant word line corresponding to the address registered in the row redundant circuit 3 is selected, and a redundant bit line corresponding to the address registered in the column redundant circuit 9 is selected. As a result, a redundant memory cell arranged at the intersection of the selected redundant word line and redundant bit line is selected, and writing and reading are performed on it.

The above-described memory accesses are all performed under the control of the control circuit 8. Control circuit 8
Outputs control signals to respective address buffers and decoders in response to external control signals, for example, a row address center signal RASB (Row Address Strobe) and a column address selection signal CASB (Column Address Strobe). Control behavior. In addition,
"B" in the selection signals RASB and CASB
Indicates low level active.

In this embodiment, a circuit for detecting the arrival of an address is provided in the row redundancy circuit 3 or the column redundancy circuit 9. At the time of memory access, when the arrival of the address is detected, the redundancy control signal is output according to the result of the redundancy judgment, so that the optimal operation timing can be set.

FIGS. 2 to 4 are diagrams for explaining the configuration and operation of the row redundancy circuit. Hereinafter, the configuration and operation of the semiconductor memory device of the present embodiment will be described with reference to these drawings. FIG. 2 shows a configuration of a row address decoder, a word line driver, and a row redundancy circuit in a semiconductor memory device having a plurality of memory cell arrays. As illustrated, a memory device including four memory cell arrays 35_0, 35_1, 35_2, and 35_3 is illustrated here. Each memory cell array has
It has a plurality of memory cells arranged in a matrix, a word line is arranged for each row of the memory cells, and a bit line is arranged for each column. Further, in addition to the regular memory cells, a redundant memory cell array (not shown) is provided. Redundant memory cells in the same row are connected to a redundant word line. Word lines and redundant word lines are provided by word line drivers 34_0, 34_1, and 3 provided for each memory cell array.
4_2 and 34_3. In FIG. 2, the sense amplifier is omitted.

Row redundancy circuits 32_0, 32_ for controlling whether or not to select a redundant word line for each word line driver.
1, 32_2 and 32_3 are provided. The row decoder 31 outputs a predecode signal or a decode signal (hereinafter, simply referred to as a decode signal for simplicity of description) PRD. Note that this decoded signal P
RD is composed of a plurality of bits, and the word line driver 34_
0, 34_1, 34_2, 34_3 and the row redundancy circuits 32_0, 32_1, 32_2, 32_3, respectively.

Each row redundancy circuit 32_0, 32_1, 32
_2 and 32_3, an address arrival detection circuit for detecting arrival of an address is provided. When the arrival of a predetermined address is detected by the address arrival detection circuit, the row redundancy circuits 32_0, 32_1, 32_2, and 32_3 output a redundancy control signal for instructing whether to select a redundancy memory cell to the word line driver. . The word line driver selects either a normal word line or a redundant word line according to the redundancy control signal.

FIG. 3 shows a configuration example of the row redundancy circuit. As shown in the figure, the row redundancy circuit of this example is different from the conventional row redundancy circuit shown in FIG. 6 in that an address arrival detection circuit 41 for detecting the arrival of an address and a redundancy control signal RD.
An output timing control circuit 42 for controlling the output timing of E0 and RDE1 is added. That is, in the present embodiment, an address arrival detection circuit is provided for each row redundancy circuit in the conventional semiconductor memory device shown in FIG. Thus, the arrival of the address is detected for each row redundancy circuit, and the optimum operation timing is determined in accordance with the detection result.

As shown in FIG. 3, the address arrival detection circuit 41 comprises an OR gate OGT1. O
The R gate OGT1 has, for example, four input terminals,
4-bit decoded signals AXiBjB, AXijB, AXiBj, AXij to be detected as reaching the input terminals
Is entered. When any one of these decode signals goes high, the output signal S
AD switches to high level.

The output signal of the address arrival detection circuit 41 is output to the output timing control circuit 42. The output timing control circuit 42 has two AND gates AGT2 and AG
It is constituted by T3. The AND gate AGT2 has a detection signal SAD from the address arrival detection circuit 41,
A signal corresponding to the level of the memory enable signal ME and the node NDa is input to the AND gate AGT3.
The detection signal SAD, the memory enable signal ME, and the inverted signal corresponding to the level of the node NDa are input from the address arrival detection circuit 41.

Transistors Q20, Q20_0, Q20
_1,..., Q20_N and fuses F10, F11,
, F1N, it is detected whether the input address matches the registered address. When a defective memory cell is found in the memory cell array, a predetermined one of the fuses F10, F11,..., F1N is blown according to the address of the defective memory cell, and so-called address registration is performed. Before the memory access, the redundancy enable signal RE is temporarily held at the low level, so that the transistor Q20 is turned on and the node NDa is connected to the power supply voltage V _CC.
, And is held at a high level, for example, the power supply voltage V _CC or a level close thereto.

When a decode signal other than the address registered in the fuse circuit is input, a current path is formed between the node NDa and the ground potential GND via the fuse and the transistor held in the ON state. , The node NDa is discharged, and the ground potential G
ND is held. At this time, the output terminal of the inverter INV1 is kept at a high level. When the detection signal SAD from the address arrival detection circuit 41 rises, the output timing control circuit 42 outputs a low level redundancy control signal RDE0 and a high level redundancy control signal R
DE1 is output.

When the redundancy control signal RDE0 is at a high level, the word line driver selects a redundant word line, and when the redundancy control signal RDE1 is at a high level, the word line driver selects a normal word line. Therefore, in the above-described state, a normal word line is selected by the word line driver.

When a decode signal that matches the address registered in the fuse circuit is input, node NDa is held at a level substantially after precharge. That is, the node NDa is kept at the high level, and the output terminal of the inverter INV1 is kept at the low level. In this case, when the detection signal SAD from the address arrival detection circuit 41 rises, the output timing control circuit 42 outputs the high-level redundancy control signal RDE0 and the low-level redundancy control signal RDE1. Accordingly, a normal word line is not selected by the word line driver, and a redundant word line is selected.

FIG. 4 is a timing chart showing the operation of the row redundancy circuit of this embodiment. As shown in FIGS. 4A and 4B, the memory enable signal ME and the redundancy enable signal RE are switched from a low level to a high level at a predetermined timing. As described above, when the redundancy enable signal RE is held at a low level,
The node NDa of the row redundancy circuit is precharged to a high level.

The input row addresses AX0, AX1,
, AXn, the row decoder outputs a decode signal. As shown in FIGS. 4C and 4D, after a predetermined time has elapsed since the memory enable signal ME and the redundancy enable signal RE are switched to the active (high level) state, each bit of the decode signal is Set to a predetermined level.

When the decode signal does not match the address registered in the fuse circuit by the row redundancy circuit, the redundancy control signal RDE1 is set at the timing set by the address arrival detection circuit 41 as shown in FIG. Are held at a high level, and at this time, the redundancy control signal RDE0 is held at a low level. In response, the word line driver selects the normal word line specified by the decode signal.

On the other hand, when the decode signal matches the address registered in the fuse circuit, the redundancy control signal RDE0 goes high at the timing set by the address arrival detection circuit 41, as shown in FIG. , And at this time, the redundancy control signal RDE1 is held at the low level. In response, the word line driver does not select a normal word line, but selects a redundant word line according to the registered address.

As described above, according to the present embodiment, the redundancy control circuit for controlling the access to the redundant memory is provided with the address arrival detection circuit for detecting the arrival of the address. Address registration is performed by cutting a fuse or the like in accordance with the address of the defective memory cell. At the time of memory access, the input address is compared with the registered address, and the output timing control circuit controls the output timing of the redundant control signal generated according to the address comparison result according to the detection result of the address arrival detection circuit. Therefore, when a plurality of memory cell arrays are provided, it is possible to detect the arrival of the address in each of the redundancy control circuits provided for each memory cell array, and to control the optimal operation timing of the redundancy switching accordingly.

[0051]

As described above, according to the semiconductor memory device of the present invention, the optimum operation timing of the redundancy control circuit can be set, and the operation of the semiconductor memory device having the redundancy function can be set accordingly. Higher speed can be realized. Further, according to the present invention, the circuit design can be simplified, and the design of the memory core used for the system LSI can be automatically designed using the parametric method, even when designing different memory sizes. This has the advantage that the cost can be reduced and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of a semiconductor memory device according to the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of the semiconductor memory device shown in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of a row redundancy circuit in the circuit diagram of FIG. 2;

FIG. 4 is a timing chart showing an operation of the row redundancy circuit shown in FIG. 3;

FIG. 5 is a circuit diagram showing a configuration example of a conventional semiconductor memory device having a redundant function.

6 is a circuit diagram showing a configuration of a row redundancy circuit in the semiconductor memory device shown in FIG.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Row address buffer, 2 ... Row decoder, 3 ... Row redundancy circuit, 4 ... Word line driver, 5 ... Memory cell array, 6 ... Sense amplifier, 7 ... Input / output buffer, 8 ...
Control circuit, 9 column redundancy circuit, 10 column address buffer, 11 column decoder, 12 column switch driver, 21 31 row decoder, 23 address arrival detection circuit, 22_0, 22_1, 22_2, 2
2_3, 32_0, 32_1, 32_2, 32_3... Row redundancy circuit, 24_0, 24_1, 24_2, 24_
3, 34_0, 34_1, 34_2, 34_3 ... word line driver, 25_0, 25_1, 25_2, 25_
3,35_0,35_1,35_2,35_3 ...... memory cell array, 41 ... address arrival detection circuit, 42 ... output timing control circuit, V _CC ... power supply voltage, GND ... ground potential.

Claims (11)

[Claims] 1. A redundant memory cell in which a defective memory cell in a normal memory cell array is replaced. By registering an address of the defective memory cell, the redundant memory cell is replaced with the redundant memory cell at the time of memory access. A semiconductor memory device to be accessed, comprising: an address registration circuit that stores an address of the defective memory cell by the address registration; and an input address and a memory that are stored in the address registration circuit when the arrival of an input address is detected during memory access. And a redundancy control circuit for instructing access to either the memory cell array or the redundant memory cell according to a result of the comparison. 2. The redundancy control circuit compares an address arrival detection circuit for detecting arrival of the input address with an address of the defective memory cell stored in the address registration circuit. 2. The semiconductor memory device according to claim 1, further comprising: a comparison circuit; and an output timing control circuit that outputs a comparison result of the comparison circuit in accordance with an output signal of the address arrival detection circuit. 3. The address arrival detection circuit comprises a logic circuit having a predetermined address signal selected according to the address of the defective memory cell as an input signal, and the output timing control circuit comprises 3. The semiconductor memory device according to claim 2, wherein a comparison result of said comparison circuit is output according to an output signal. 4. The address registration circuit according to claim 1, wherein the address registration is performed by blowing a predetermined fuse in accordance with an address of the defective memory cell in the normal memory cell. 13. The semiconductor memory device according to claim 1. 5. A plurality of memory cells are arranged in a matrix, and are connected in common to a plurality of word lines commonly connected to memory cells arranged in each row and to a plurality of memory cells arranged in each column. A memory cell array having a plurality of bits, and a plurality of redundant memory cells replacing the memory cells form a matrix having at least one row, and at least one redundant word line commonly connected to each redundant memory cell A redundant memory cell array having an address register circuit for storing an address of the defective memory cell by address registration when a defective memory cell is detected in the memory cell array; and Compare the input address with the address of the defective memory cell stored in the address registration circuit A redundancy control circuit for instructing access to either the memory cell array or the redundant memory cell array in accordance with the comparison result; and an input when the redundancy control circuit instructs access to the memory cell array. One word line designated from the plurality of word lines is selected according to the address, a predetermined activation voltage is applied to the selected word line, and access to the redundant memory cell array is instructed by the redundancy control circuit. And a word line driver for selecting a predetermined redundant word line according to the input address and applying a predetermined activation voltage to the selected redundant word line. 6. The redundancy control circuit compares an address arrival detection circuit for detecting the arrival of the input address with an address of the defective memory cell stored in the address registration circuit. 6. The semiconductor memory device according to claim 5, further comprising: a comparison circuit; and an output timing control circuit that outputs a comparison result of the comparison circuit according to an output signal of the address arrival detection circuit. 7. The semiconductor memory device according to claim 5, further comprising a row decoder for outputting a selection signal for selecting said word line and said redundant word line according to an input address. 8. The logic circuit according to claim 1, wherein the redundancy control circuit is a logic circuit having a predetermined selection signal selected from the plurality of selection signals from the row decoder as an input signal in accordance with an address of the defective memory cell. A comparison circuit that compares an address with an address of the defective memory cell stored in the address registration circuit; and an output timing control circuit that outputs a comparison result of the comparison circuit according to an output signal of the logic circuit. 8. The semiconductor memory device according to claim 7, comprising: 9. A comparison circuit having a precharge circuit for setting an output node to a predetermined precharge potential before accessing a memory, wherein at the time of memory access, the defective memory cell stored in the address registration circuit is accessed. 9. The semiconductor memory device according to claim 8, wherein said output node is set to one of said precharge potential and a common potential different from said precharge potential according to an address and said selection signal from said row decoder. 10. An address registration circuit, comprising: a fuse circuit composed of a plurality of fuses commonly connected to the output node; connected between each fuse of the fuse circuit and the common potential; 10. A plurality of transistors to which a selection signal from a row decoder is applied.
The semiconductor memory device according to claim 1. 11. The semiconductor memory device according to claim 10, wherein said address registration is performed by blowing a predetermined fuse of said fuse circuit in accordance with an address of said defective memory cell in said memory cell array.