JPH1127336A - Absolute phase processing synchronization acquisition circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the absolute phase processing synchronization acquisition circuit whose circuit scale is enough to be small. SOLUTION: The absolute phase processing synchronization acquisition circuit is provided with accumulated addition/subtraction averaging circuits 85A, 85B that extracts a bit stream of a frame synchronizing signal from a base band signal demodulated by a demodulation circuit 1 over a frame synchronizing signal period, conducts addition processing when a bit stream of an extracted frame synchronizing signal is logical '1', conducts subtraction processing when the bit stream of the extracted frame synchronizing signal is logical '0', and average the addition subtraction processing results. Then the absolute phase processing synchronization acquisition circuit discriminates a phase of a received signal based on an output of accumulated addition subtraction averaging processing by the accumulated addition/subtraction averaging circuits 85A, 85B to rotate a phase of the demodulated base band signal by a discriminated phase.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an absolute phase synchronization acquisition circuit, and more particularly to a receiver for receiving a digital modulated wave transmitted by a plurality of modulation methods having different C / Ns. The present invention relates to an absolute phase synchronization acquisition circuit that makes a received signal phase angle coincide with a transmitted signal phase angle to make an absolute phase.

[0002]

2. Description of the Related Art A digital modulated wave, for example, 8PSK, transmitted by a plurality of modulation schemes requiring different C / Ns.
Modulation, QPSK modulation, and BPSK modulation are combined for each time, and a broadcast receiver that receives a digitally modulated wave by the hierarchical transmission scheme repeatedly transmitted for each frame is a demodulated baseband signal (hereinafter, referred to as baseband signal). A signal is also referred to as a symbol stream), a frame synchronization signal is captured, a current reception signal phase rotation angle is obtained from a signal point arrangement of the captured frame synchronization signal, and demodulation is performed based on the obtained reception signal phase rotation angle. An absolute phase synchronization acquisition circuit performs absolute phase matching to match the transmission signal phase angle by rotating the baseband signal in the opposite phase.

[0003] A conventional absolute phase synchronization acquisition circuit comprises a demodulation circuit 1, a frame synchronization detection block 2, as shown in FIG.
A frame synchronization signal generator 6, a remapper 7 including a ROM, and a received signal phase detection block 8 are provided. The frame synchronization detection block 2 includes a BPSK demapper 3, synchronization detection circuits 40 to 47, and a frame synchronization circuit 5. The reception signal phase detection block 8 includes a delay circuit 81,
82, a 0 ° / 180 ° phase rotation circuit 83, cumulative addition and averaging circuits 85 and 86, and a reception phase determination circuit 87.

A conventional absolute phase synchronization acquisition circuit shown in FIG. 14 converts the frequency of a received digital modulated wave into a predetermined intermediate frequency, and supplies the frequency-converted intermediate frequency signal to a demodulation circuit 1 for demodulation. From the demodulation circuit 1, for example, a demodulated baseband signal I having a quantization bit number of 8 bits.
(8), Q (8) (the number in parentheses indicates the number of bits, and hereinafter the number of bits is abbreviated and simply referred to as I or Q).

[0005] The baseband signals I (8) and Q (8) are
For example, to capture a BPSK-modulated frame synchronization signal, the BPSK demapper 3 of the frame synchronization detection block 2
And a BPSK demapped bit stream B0 is output. BPSK demapper 3 is, for example, R
OM.

Here, mapping for each modulation scheme on the transmitting side will be described with reference to FIG. FIG.
(A) shows a signal point arrangement when 8PSK is used as a modulation method. The 8PSK modulation method can transmit a 3-bit digital signal (a, b, c) with one symbol, and the combination of bits constituting one symbol is (0, 0, 0).
(0, 0, 1) to (1, 1, 1). These 3-bit digital signals are transmitted on the transmitting side I in FIG.
The signal points are converted into signal point arrangements 0 to 7 on the -Q vector plane, and this conversion is called 8PSK mapping.

In the example shown in FIG. 15A, bit strings (0,
(0,0) in the signal point constellation {0}, the bit string (0,0,
1) in the signal point arrangement {1}, the bit string (0, 1, 1) in the signal point arrangement {2}, the bit string (0, 1, 0) in the signal point arrangement {3}, and the bit string (1, 0). , 0) to signal point arrangement 〃
4}, the bit string (1, 0, 1) is assigned to the signal point arrangement {5}.
The bit string (1, 1, 1) is converted into a signal point arrangement {6}, and the bit string (1, 1, 0) is converted into a signal point arrangement {7}.

FIG. 15B shows a signal point arrangement when QPSK is used as a modulation scheme. In the QPSK modulation scheme, a 2-bit digital signal (d, e) can be transmitted by one symbol, and the symbol The combination of bits to be set is (0,
0), (0, 1), (1, 0), and (1, 1). In the example of FIG. 15B, for example, the bit string (1, 1)
In the signal point arrangement {1}, the bit string (0, 1) in the signal point arrangement {3}, and the bit string (0, 0) in the signal point arrangement {5}.
, The bit string (1, 0) is converted into the signal point arrangement {7}. Note that the relationship between the signal point constellation and the arrangement number for each modulation scheme is the same between the signal point constellation and the arrangement number on the basis of 8PSK.

FIG. 15C shows a signal point arrangement when BPSK is used as a modulation method. In the BPSK modulation method, a 1-bit digital signal (f) is transmitted by one symbol. For the digital signal (f), for example, (1) is converted to a signal point arrangement {0}.
(0) is converted to a signal point arrangement {4}.

Next, the frame synchronization signal will be described.
In the hierarchical transmission method, the frame synchronization signal is transmitted after being subjected to BPSK modulation requiring the lowest C / N. Assuming that the bit stream of the frame synchronization signal composed of 16 bits is (S0, S1,..., S14, S15) and is sequentially transmitted from S0, (0, 0,
0,1,0,0,1,1,0,1,0,1,1,1,
1, 0) or the latter 8 bits are inverted (0, 0,
0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0,
0, 1) are transmitted alternately for each frame. Hereinafter, the bit stream of the frame synchronization signal is referred to as {SYNCCAT}.
Also, the bit stream in which the latter 8 bits are inverted is represented by {n
Also referred to as SYNCCAT @. This bit stream is converted into a signal point constellation {0} or {4} by the BPSK mapping shown in FIG. 15C on the transmitting side, and the converted symbol stream is transmitted.

In order to capture a frame synchronization signal of 16 bits, that is, 16 symbols transmitted by BPSK modulation, contrary to the mapping converted on the transmission side,
It is necessary to convert received symbols into bits by the BPSK demapping shown in FIG. Therefore, as shown in FIG. 16A, {1} when a demodulated signal is received in a hatched area on the received IQ vector plane, and {0} when a demodulated signal is received in a portion without a hatched line. judge. That is, the output is set to {1} or {0} depending on which of the two areas divided by the BPSK determination boundary line shown by the thick line in FIG. 16A, and this is used as the BPSK demapper.

The baseband signals I and Q are input to a BPSK demapper 3 for performing the above-mentioned bit conversion.
The demapper 3 outputs the BPSK-demapped bit stream B0. In this specification, a demapper indicates a circuit for demapping. The bit stream B0 is input to the synchronization detection circuit 40, and the synchronization detection circuit 40 captures a bit stream of a frame synchronization signal from the bit stream B0.

Next, the synchronization detecting circuit 40 will be described with reference to FIG. The bit stream B0 is input to the shift register D15, and is sequentially shifted up to the shift register D0. At the same time, the outputs of the shift registers D15 to D0 are logically inverted with respect to predetermined bits. Is input to In the AND gate 51, the state of the shift registers D15 to D0 (D
, D14, D15) are (0, 0, 0, 1,.
0, 0, 1, 1, 0, 1, 0, 1, 1, 1, 1, 0), the output SYNA0 of the AND gate 51 becomes high potential. In the AND gate 52, (0, 0,
0, 1, 0, 0, 1, 1, 1, 0, 1, 0, 0, 0,
In the case of 0, 1), the output SYNB0 of the AND gate 52 becomes high potential. That is, when SYNCPAT is captured, SYNA0 has a high potential, and when SYNCPAT is captured, SYNCB0 has a high potential.

The outputs SYNA0 and SYNB0 of the synchronization detecting circuit 40 are input to the frame synchronizing circuit 5, and when the frame synchronizing circuit 5 confirms that these inputs are alternately and repeatedly received at fixed frame intervals, the frame synchronizing circuit 5 outputs the frame synchronizing signal. Is determined, and a frame synchronization pulse is output every frame period.

Normally, in a hierarchical transmission system in which a plurality of required modulation systems having different C / Ns are combined for each time and transmitted repeatedly for each frame, header data indicating their multiplexing structure is multiplexed. After it is determined that frame synchronization has been achieved, header data indicating a multiplex configuration is extracted from a timing signal generated by a frame synchronization pulse output from the frame synchronization circuit 5. As a result, processing for each modulation scheme becomes possible only when the frame multiplexing configuration is known.

In other words, the demodulation circuit 1 operates as an 8PSK demodulation circuit until it is determined that the frame is synchronized. Therefore, depending on the phase state of the demodulation carrier reproduced by the carrier regeneration circuit in the demodulation circuit 1, the demodulation circuit 1 may not operate on the receiving side. The I-axis and the Q-axis of the IQ vector plane are compared with those on the transmitting side, and θ = 4
The phase is rotated by 5 ° × n (n = 0 to 7). That is, in FIG. 15C, signal point arrangement {0} for bit {1} and signal point arrangement {0} for bit {0}
4}, the symbol stream of the frame synchronization signal BPSK-mapped has a signal point arrangement {0}, where θ = 0 ° as in the transmitting side, depending on the phase state of the demodulation carrier.
4}, the signal point arrangement {1}, {5} rotated by θ = 45 °, and the signal point arrangement {2}, {6} rotated by θ = 90 °. And so on. There are eight types of demodulated phases of the frame synchronization signal. For this reason, it is necessary to be able to capture a frame synchronization signal that has been demodulated at any phase.

Therefore, the BPSK demapper 3 corresponds to FIG.
Θ = 0 ° (n = 0) and θ = 45 ° (n =
1), θ = 90 ° (n−2),..., Θ = 270 ° (n
= 6), and BPSK demappers 30 to 37 corresponding to a phase rotation of θ = 315 ° (n = 7).

FIG. 16 (b) shows that the symbol stream of the demodulated frame synchronization signal is rotated by a phase of θ = 45 °, bit {1} is in signal point arrangement {1}, and bit {0} is "signal point arrangement}. Fig. 16 shows BPSK demapping for the case of appearing at 5 [deg.] B indicated by a thick line in Fig. 16 (b).
The PSK determination boundary line is a BPSK demapping thick line BP shown in FIG.
It rotates 45 ° counterclockwise with respect to the SK determination boundary line. By using such a BPSK demapper, θ
= 45 ° phase-rotated frame synchronization signal can be stably captured. This output of the BPSK demapper 3 is the output B1 of the BPSK demapper 3 shown in FIG. Hereinafter, B2 to B7 are θ = 45 ° × n (n is an integer of 2 to 7).
Is the output of the BPSK demapper 3 in the case of.

The circuit configuration of the synchronization detection circuits 41 to 47 is the same as that of the synchronization detection circuit 40. By providing the synchronization detection circuits 40 to 47 in this manner, the demodulation circuit 1
Regardless of the phase rotation of the baseband signal due to the phase state of the demodulation carrier reproduced by the carrier reproduction circuit in the above, the frame synchronization signal is captured by at least one or more synchronization detection circuits 40 to 47, and the frame synchronization signal is From the acquired synchronization detection circuit, SYNAn and SYNBn (n = 0 to 7 are integers) are transmitted in accordance with the pattern (SYNCTAP or nSYNCPT) of the captured frame synchronization signal.

FIG. 1 provided in the frame synchronization circuit 5
9 (a) and the OR gates 53, 5 shown in FIG.
4 receives the signals SYNAn and SYNBn, and outputs the OR output SYNA of SYNAn from the OR gate 53;
When it is confirmed that the logical OR output SYNB of the SYNBn from the OR gate 54 is alternately and repeatedly received at regular frame intervals, it is determined that frame synchronization is established, and a frame synchronization pulse is output at each frame period. .

The frame synchronization detection block 2 shown in FIG.
Has described the process from the acquisition of the frame synchronization signal to the output of the frame synchronization pulse from the frame synchronization detection block 2. Next, the absolute phase conversion by calculating the current received signal phase rotation angle from the signal point arrangement of the captured frame synchronization signal and rotating the baseband signal demodulated in reverse phase based on the obtained phase rotation angle will be described. I do.

The symbol stream of the frame synchronization signal which is transmitted after being BPSK-mapped on the transmitting side and demodulated into a baseband signal by the demodulation circuit 1 is demapped by the BPSK demapper 3 to bits {1} or {0}. However, the phase difference between the symbol streams of the respective frame synchronization signals demapped to the bits {1} or {0} is 180 °. Therefore, bit {0}
By rotating the symbol stream of the frame synchronization signal that is demapped to 180 ° by 180 °, a symbol stream that is demapped to all bits {1} is obtained.

Further, by averaging symbol streams demapped to all bits {1}, the arrangement of received signal points with respect to bit {1} of BPSK is obtained. Therefore, the received signal point corresponding to bit {1} of the obtained BPSK and bit {1}
The phase difference from the signal point constellation {0} mapped to the received signal is determined as the received signal phase rotation angle θ, and the entire demodulated baseband signal is subjected to anti-phase rotation so that the absolute phase of the baseband signal is converted. Can be achieved.

Further, a conventional example will be described (FIG. 14).
reference). In response to the frame synchronization pulse output from the frame synchronization circuit 5, the frame synchronization signal generator 6 captures the frame synchronization signal patterns SYNCPAT, nSY.
A bit stream of a frame synchronization signal corresponding to NCPAT is generated.
° / 180 ° is supplied to the phase rotation circuit 83. 0 ° / 1
The 80 ° phase rotation circuit 83 rotates the phase by 180 ° in the case of {0} and the phase rotation in the case of {1} based on the bit {0} or {1} in the supplied bit stream. Output without change.

The timing of the bit stream of the reproduced frame synchronization signal sent from the frame synchronization signal generator 6 and the timing of the symbol stream of the frame synchronization signal are shifted by the delay circuits 81 and 82 to a 0 ° / 180 ° phase rotation circuit 83.
The gates are opened by the frame synchronization signal section signal sent from the frame synchronization signal generator 6 and the symbol streams DI (8) of the frame synchronization signals output from the delay circuits 81 and 82.
DQ (8) is 0 ° when the bit stream is {0}.
In the / 180 ° phase rotation circuit 83, the phase is rotated by 180 ° and sent to the cumulative averaging circuits 85 and 86.

FIG. 20A shows the received signal phase rotation angle θ = 0.
FIG. 20 (b) shows the signal point arrangement of the frame synchronization signal when the symbol streams VI (8) and VQ () are converted by the 0 ° / 180 ° phase rotation circuit 83. 8) shows the signal point arrangement of FIG. The symbol streams VI (8) and VQ (8) are sent to cumulative averaging circuits 85 and 86, respectively, and are added and averaged by the cumulative averaging circuits 85 and 86 in a predetermined section. A
VI (8) and AVQ (8) are output. Here, the averaging of the symbol streams VI (8) and VQ (8) is stable even when a slight phase change or amplitude fluctuation of the received baseband signal due to deterioration of the received C / N occurs. This is so that the signal point arrangement can be obtained.

The received signal points [AVI (8), AVQ (8)] of the BPSK-mapped signal for bit {1} are obtained by the cumulative averaging circuits 85 and 86.
Next, the received signal points [AVI (8), AVQ (8)] are input to a received signal phase determination circuit 87 composed of a ROM.
A 3-bit phase rotation signal RT (3) corresponding to the phase rotation angle is obtained from the received signal phase determination table shown in FIG. {0} to {7} in FIG. 21 indicate decimal numbers based on the phase rotation signal RT (3). For example, the received signal phase rotation angle θ = 0 ° shown in FIG.
In the case of, the phase rotation signal for which the signal points of AVI (8) and AVQ (8) are determined by the received signal phase determination table is 〃
0 °. Therefore, (0, 0, 0) is sent to the phase rotation signal RT (3). When the received signal phase rotation angle θ = 45 °, the phase rotation signal RT
(3) is {1}, and therefore (0, 0, 1) is sent to the phase rotation signal RT (3).

The remapper 7 comprising a ROM receives the phase rotation signal RT (3) and receives the baseband signal I (8),
By rotating the phase of Q (8) according to the phase rotation signal RT (3), absolute phase conversion is achieved.

Next, the operation of the remapper 7 will be described. The remapper 7 constitutes a phase conversion circuit for making the signal point arrangement of the received baseband signal the same as that on the transmitting side. The received signal phase rotation angle θ is calculated in the received signal phase detection block 8, and the phase rotation signal RT (3) corresponding to the received signal phase rotation angle θ is converted to the remapper 7.
Supplied to Here, the phase rotation signal RT (3) is 0 to
The relationship with the phase rotation angle θ is expressed by the following (1)
Defined as shown in the equation.

RT (3) = θ / 45 (1) where θ = n · 45 ° and n is an integer of 0 to 7.

The absolute phase of the baseband signal can be obtained by performing reverse rotation, that is, (-θ) phase rotation with respect to the phase rotation angle θ. Therefore, the remapper 7 rotates the phase of the input baseband signals I and Q by the angle φ (= −θ) according to the following equations (2) and (3), and converts the baseband signals I and Q into the absolute phase. '(8) and Q' (8) (hereinafter also referred to as I 'and Q' with the number of bits omitted).

I ′ = I cos (φ) −Q sin (φ) (2) Q ′ = I sin (φ) + Q cos (φ) (3)

[0033]

However, when using the above-described conventional absolute phase synchronization acquisition circuit, BPSK is used.
A demapper is required, and 64 Kbytes (2 ¹⁶ × 8) is used when a table conversion by ROM is used for the BPSK demapper.
Bit) storage capacity, and further requires a total of 128 registers for eight synchronization detection circuits, a large-scale coincidence detection logic circuit, a remapper, and a ROM table for the remapper. When the conversion is used, there is a problem that the circuit becomes large in scale, for example, a storage capacity of 1 Mbyte (2 ¹⁹ × 16 bits) is required.

An object of the present invention is to provide an absolute phase synchronization acquisition circuit that requires a small circuit scale.

[0035]

An absolute phase synchronization acquisition circuit according to the present invention acquires a frame synchronization signal, detects a reception signal phase rotation angle with respect to a transmission signal phase angle from the acquired frame synchronization signal, and detects the reception signal phase rotation angle. In an absolute phase synchronization acquisition circuit for making the phase angle coincident with the transmission signal phase angle to make an absolute phase, a bit stream of the frame synchronization signal is extracted from the demodulated baseband signal over the frame synchronization signal section, and the extracted frame synchronization signal An accumulative addition / subtraction averaging means for performing an addition process when the bit stream is logical {1} and a subtraction process when the extracted bit stream of the frame synchronization signal is logical {0}, and averaging the addition / subtraction processing result; The phase of the received signal is determined based on the output of the means, and the demodulated baseband signal is rotated by the determined phase. And characterized in that.

According to the absolute phase synchronization acquisition circuit of the present invention, in the absolute phase synchronization acquisition circuit, the bit stream of the frame synchronization signal is extracted from the demodulated baseband signal over the frame synchronization signal section, and the extracted frame is extracted. When the bit stream of the synchronization signal is logic {1}, the addition processing is performed. When the bit stream of the extracted frame synchronization signal is logic {0}, the subtraction processing is performed. The addition / subtraction processing results are averaged, and the cumulative addition / subtraction averaging processing is performed. The phase of the received signal is determined based on the output, and the phase of the demodulated baseband signal is rotated by the determined phase.

Therefore, a table conversion by a storage circuit or a conventionally required 0 ° / 180 ° phase rotation circuit comprising an arithmetic circuit becomes unnecessary, and the circuit scale is reduced. Incidentally, when the 0 ° / 180 ° phase rotation circuit uses table conversion by the storage circuit, the storage capacity of 2 ¹⁶ × 16 bits is reduced, and the circuit scale is reduced.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An absolute phase synchronization acquisition circuit according to the present invention will be described below with reference to an embodiment. FIG. 1 is a block diagram showing a configuration of an absolute phase synchronization acquisition circuit according to an embodiment of the present invention.

An absolute phase synchronization acquisition circuit according to one embodiment of the present invention includes a demodulation circuit 1, a remapper 11 composed of a ROM, a logic conversion circuit 12, and a frame synchronization detection block 2.
A, a frame synchronization signal generator 6, and a received signal phase detection block 8A. Frame synchronization detection block 2A
Are the synchronization detection circuits 40A to 43A, the frame synchronization circuit 5
A, the received signal phase detection block 8A includes delay circuits 81 and 82, and cumulative addition / subtraction averaging circuits 85A and 85A.
6A, a reception signal phase determination circuit 87.

The baseband signals I (8) and Q (8) demodulated in the demodulation circuit 1 are supplied to a remapper 11 to rotate the baseband signals I (8) and Q (8) by θ = 45 °. To be transmitted as baseband signals i (8) and q (8).

First, the remapper 11 will be described. The remapper 11 is composed of a ROM, and performs only the phase rotation of θ = 45 ° on the baseband signals I (8) and Q (8) supplied to the remapper 11 so that the baseband signals i (8) and q
Output as (8).

That is, φ = −45 ° is substituted into the expressions (2) and (3), and the following expressions (4) and (5) are obtained. An expression is obtained.

I (8) = I cos (−45 °) −Q sin (−45 °) (4) q (8) = I sin (−45 °) + Q cos (−45 °) ( 5)

I (8) = I (1 / √2) −Q (−1 / √2) = (1 / √2) (I + Q) (6) q (8) = I (−1 / √) 2) + Q (1 / √2) = (1 / √2) (− I + Q) (7)

That is, in the remapper 11, the input baseband signals I (8) and Q (8) are remapped to baseband signals that are rotated clockwise by 45 °. As described above, since the remapper 11 does not need the phase rotation angle signal RT (3) as an input, the storage capacity of the ROM is 1 compared to the conventional remapper 7.
/ 8.

The phase rotation angle signal RT (3) output from the received signal phase detection block 8A, the baseband signals I (8) and Q (8) demodulated in the demodulation circuit 1 and the base remapped in the remapper 11 The band signals i (8) and q (8) are input to the logic conversion circuit 12.

The logic conversion in the logic conversion circuit 12 to which these are input will be described. 2A, 2B and 3 are truth tables showing the operation of the logic conversion circuit 12. FIG. 2A shows n = even number, that is, θ = 45 ° × n.
(N = 0, 2, 4, 6), and FIG. 2B shows n = odd, that is, θ = 45 ° × n (n =
1, 3, 5, 7), and FIG.
= 45 ° × n (n = 0, 1, 2, 3, 4, 5, 6, 7)
6 is a truth table showing a BPSK demapping output in the case of.

Based on the phase rotation angle signal RT (3), n =
If even, the absolute phased baseband demodulated signal I
'(8) and Q' (8) are input baseband signals I
(8) and Q (8) are logically converted based on the phase rotation angle signal RT (3) according to FIG. For example, when the phase rotation angle signal RT (3) = {000}, since the signal is received in the absolute phase, the baseband signal I ′ (8) = baseband signal I (8), baseband signal Q ′ (8) = This is the baseband signal Q (8). Phase rotation angle signal RT (3)
In the case of = {010}, the phase rotation angle θ is 90 °.
Conventionally, the equations (2) and (3) are used to convert the data into the following equations (8) and (9).

I ′ = I cos (−90 °) −Q sin (−90 °) = Q (8) (8) Q ′ = I sin (−90 °) + Q cos (−90 °) = − I (8) …… (9)

However, this conversion is performed by inverting the sign of the baseband signal I (8) input to the logic conversion circuit 12 and exchanging the baseband signal I (8) with the inverted sign and the baseband signal Q (8). Is easily obtained. Phase rotation angle signal RT (3) = {100}, RT (3) = {110}
Similarly, the case of (1) can be obtained by conversion according to FIG.

Based on the phase rotation angle signal RT (3), n =
When odd, baseband demodulated signal with absolute phase
I ′ (8) and Q ′ (8) perform logical conversion of the input baseband demodulated signals i (8) and q (8) based on the phase rotation angle signal RT (3) according to FIG. 2 (b). Is obtained. For example, when the phase rotation angle signal RT (3) = {001}, the phase rotation angle θ = 45 °, and the baseband signal
I ′ (8) = baseband signal i (8), baseband signal Q ′ (8) = baseband signal q (8), and baseband signal i output from remapper 11
(8) The baseband signal q (8) may be output as it is as the baseband signal I '(8) and the baseband signal Q' (8).

Next, the phase rotation angle signal RT (3) = $ 011
In the case of 〃, the phase rotation angle θ = 135 °. This is equivalent to further performing a phase rotation of the baseband signal i (8) and the baseband signal q (8) with the phase rotation angle θ = 90 ° with respect to the phase rotation angle θ = 45 °. Therefore, it is as shown in the following equations (10) and (11).

I ′ = icos (−90 °) −q sin (−90 °) = q (8) (10) Q ′ = isin (−90 °) + qcos (−90 °) = − i (8) ... (11)

Therefore, the baseband signal i (8) input to the logic conversion circuit 12 is sign-inverted, and the sign-inverted baseband signal i (8) and the baseband signal q
It is easily obtained by replacing (8). The case where the phase rotation angle signal RT (3) = {101} and RT (3) = {111} is similarly obtained by conversion according to FIG. 2B.

The phase rotation angle signal RT (3) based on the phase rotation angle θ and the baseband signal I
(8), Q (8), and the baseband signals i (8) and q (8) remapped by the remapper 11 are subjected to the conversion shown in FIG.
As the SK demapped output, the synchronization detection circuit 40
A, 41A, 42A and 43A.

Here, the logic conversion circuit 12 will be specifically described with reference to FIG. 4, including BPSK demapping. The logic conversion circuit 12 performs the baseband signals I (8), Q (8) and the baseband signals i (8), q which have been subjected to phase rotation with respect to the remapper output θ = 45 ° by the inverters 121 to 124. (8) is inverted and the baseband signals I (8), Q (8), i (8), q (8) and the inverted baseband signals I (8), Q (8), i (8) ,
and q (8) in the multiplexer 125 based on the phase rotation angle signal RT (3), and outputs the selected baseband signal to the output baseband signals I '(8) and Q'.
It is transmitted as (8). This selection is as shown in FIGS. 2A and 2B, and the baseband signal I ′
(8), Q ′ (8) is obtained.

Further, the MSB of I (8) is extracted from the input baseband signal of the multiplexer 125 as shown by the solid line in FIG.
The MSB of (8) is extracted as output B1, and the M of Q (8) is extracted.
The synchronization detection circuits 40A to 4A extract the SB and output it as an output B2, and extract the MSB of q (8) as an output B3.
Send to 3A. Therefore, no special circuit is required for BPSK demapping, and the conventionally required BPSK
The K demapper 3 becomes unnecessary, and the BPSK demapper 3 becomes R
When configured by OM table conversion, the R
The OM becomes unnecessary, and the memory for 2 ¹⁶ × 8 bits can be reduced.

This is apparent from the BPSK demapping shown in FIG. That is, FIG.
In (a), the signal point of the baseband signal is represented by a bit #
The result determined as 1} or bit {0} is equal to the I-axis of the signal point, that is, the MSB of the baseband signal I (8). The determination result when θ = 45 ° shown in FIG. 12B is equal to the MSB of the baseband signal i (8) output from the remapper 11. The same applies to other phase rotation angles, and the BPSK demapper 3 conventionally required as described above can be omitted.

Further, from the input baseband signal of the multiplexer 125, the MSB of the inverted I (8), shown by the broken line in FIG. 4, is extracted as the output B0, and the MSB of the inverted i (8) is extracted. Output B1 and the inverted Q
The MSB of (8) is extracted and output B2, and the inverted q
The MSB of (8) may be extracted and sent to the synchronization detection circuits 40A to 43A as the output B3.

This is because, for the reception phase rotation angle θ, θ =
Output for 0 ° and θ = 180 °, Output for θ = 45 ° and θ = 225 °, θ = 90 ° and θ = 270 °
, And the relationship between the outputs for θ = 135 ° and θ = 315 ° is apparent from the logical inversion relationship.

Next, each of the synchronization detection circuits 40A to 43A will be described with the synchronization detection circuit 40A as a representative. When the synchronization is detected by the synchronization detection circuit, outputs for θ = 0 ° and θ = 180 °, outputs for θ = 45 ° and θ = 225 ° with respect to the reception phase rotation angle θ,
Output for θ = 90 ° and θ = 270 °, and θ = 1
Using the fact that the relationship between outputs at 35 ° and θ = 315 ° is a logical inversion relationship,
The synchronization detection circuit is configured to detect {, {nSYNCPAT} and a bit stream obtained by logically inverting them.

FIG. 5 shows an embodiment of the synchronization detecting circuit 40A, in which shift registers D0 to D15 and shift registers D
15, an AND gate 55 receiving the outputs of D10 and D8, an AND gate 55A receiving the inverted outputs of the shift registers D15, D10 and D8, an AND gate 56 receiving the outputs of the shift registers D14 to D11 and D9, Shift registers D14 to D11 and D9
, An AND gate 57A receiving the outputs of the shift registers D7, D6 and D3, an AND gate 57A receiving the inverted outputs of the shift registers D7, D6 and D3, and a shift register D5. AND gate 58 which receives the outputs of D4 and D2 to D0 as inputs, shift registers D5, D4 and D2
An AND gate 58A having an inverted output of D0 as an input is provided.

The bit stream of the frame synchronization signal that can be captured by the synchronization detection circuit 40A is as described above.
SYNCPAT}, {nSYNCPAT}, and a bit stream (1, 1, 1, 0, 1, 1, 0, 0, 1, 0, 1) of a frame synchronization signal obtained by logically inverting them.
1, 0, 0, 0, 0, 1) and a bit stream (1, 1, 1, 0, 1, 1, 0,
0, 0, 1, 0, 1, 1, 1, 1, 0). The former is {SYNCNPAT}, and the latter is {SYNCPCA}.
Also referred to as T〃.

The last 8 bits of {SYNCPAT} and {n
The last 8 bits of SYNCNPAT are equal, and {n
The last 8 bits of SYNCPAT and {nSYNCPA
The latter 8 bits of T〃 are equal. For this reason, the first eight bits and the second eight bits of the frame synchronization signal are divided, and in the synchronization detection circuit 40A, the outputs RRL0, RFH0, FRH0, FFL0 of the AND gates 55 to 58, the outputs RRH0 of the AND gates 55A to 58A, RFL0, FRL
0 and FFH0 by performing a logical product operation shown in FIG. 6 to obtain a bit stream {SYNCPA} of the frame synchronization signal.
T}, {nSYNCPAT}, {SYNCPAT},
{NSYNCNPAT} is captured.

As described above, based on the AND operation output, FIG.
By performing the logical operation shown in (1), the bit stream of the frame synchronization signal {SYNCPAT}, {nSYNC
PAT〃, 〃SYNCPAT〃, 〃nSYNCNPA
T} can be captured, and as shown in FIG.
AT} and {SYNCNPAT} are ORed to obtain a synchronization detection output SYNA0, and {nSY
By performing a logical sum operation on NCPAT} and {nSYNCNPAT}, a synchronization detection output SYNB0 is obtained.

The same applies to the synchronization detection circuits 41A, 42A, 43A.
3A AND gate outputs RRH1-3, RFL
1 to 3, FRL1 to 3 and FFH1 to 3 by performing the logical product operation and the logical sum operation shown in FIGS. 6 and 7 to obtain the synchronization detection output SYNA1 and the synchronization detection output SYN.
B1, synchronization detection output SYNA2, synchronization detection output SYNB
2. Synchronization detection output SYNA3, synchronization detection output SYNB3
Is obtained.

As described above, the synchronization detection circuit 40A can serve as both the conventional synchronization detection circuits 40 and 44, and θ = 0 ° and θ = 4 output from the logic conversion circuit 12.
Synchronization detection circuit 4 having BPSK demapping outputs B0 to B3 corresponding to 5 °, θ = 90 °, and θ = 135 ° as inputs.
The frame synchronization signals for all the reception phase rotation angles can be captured by the 0A to synchronization detection circuit 43A.

Therefore, the number of synchronization detection circuits required in the related art is reduced by half, and the total number of shift registers is also reduced by half.
And the circuit scale becomes smaller.

The outputs of the synchronization detection circuit 40A to the output of the synchronization detection circuit 43A are connected to OR circuits 61 and 62 shown in FIG.
Sent to the frame synchronization circuit 5A having
(Α = 0 to 3) OR output SYNA and SYNBα
When it is confirmed that the logical sum output SYNB of (α = 0 to 3) is alternately and repeatedly received at regular frame intervals, it is determined that frame synchronization is established, and a frame synchronization pulse is output at each frame period. Is done. This is similar to the conventional case.

Next, the frame synchronization circuit 5A, the frame synchronization signal generator 6, and the received signal phase detection block 8A will be described. Demodulated baseband signal I
(8) and Q (8) are supplied to the reception signal phase detection block 8A to detect the phase rotation angle signal RT (3).

The frame synchronization signal generator 6 receives the frame synchronization pulse output from the frame synchronization circuit 5A,
The reproduction frame synchronization signal and the frame synchronization signal section signal are supplied to the reception signal phase detection block 8A.

The symbol stream of the frame synchronization signal in the baseband signals I (8) and Q (8) demodulated via the delay circuits 81 and 82 is added to the cumulative addition / subtraction averaging circuit 85.
A, 86A, and the cumulative addition / subtraction averaging circuits 85A, 85A
The input timing at 6A is delayed by delay circuits 81 and 82 so as to match the input timing with the reproduced frame synchronization signal output from the frame synchronization signal generator 6, and the frame synchronization output from the frame synchronization signal generator 6 Cumulative addition / subtraction averaging circuit 85 according to signal section signal
A, 86A input gates are opened and delay circuit 8
The symbol streams DI (8) and DQ (8) of the frame synchronizing signal output from 1, 82 are subjected to addition / subtraction processing in cumulative addition / subtraction averaging circuits 85A, 86A.

In the addition / subtraction processing in the cumulative addition / subtraction averaging circuits 85A and 86A, addition processing is performed when the bit stream is {1}, and subtraction processing is performed when the bit stream is {0}. Is done,
Averaged reception point signals AVI (8), AVQ
(8) is output from the cumulative addition / subtraction averaging circuits 85A and 86A.

The reception point signals AVI (8) and AVQ (8) output from the cumulative addition / subtraction averaging circuits 85A and 86A are R
The signal is input to a received signal phase determination circuit 87 composed of an OM.
A 3-bit phase rotation angle signal RT (3) corresponding to the phase rotation angle of the reception signal is output to the logic conversion circuit 12 according to the reception phase determination table. The operation of the subsequent stage from the logic conversion circuit 12 receiving the phase rotation angle signal RT (3) is as described above.

Here, in the received signal phase detection block 8A, 0 ° / 1
80 ° phase rotation circuit 83 and cumulative averaging circuit 85,
In place of 86, cumulative addition and averaging circuits 85A and 86A are used. This means that the 180 ° phase rotation, which is the operation of the 0 ° / 180 ° phase rotation circuit 83, is equal to the sign inversion in each axis. Therefore, the cumulative addition in each axis of the received symbol rotated by 180 ° in phase is equal to the cumulative subtraction in each axis.

Therefore, the 0 ° / 180 ° phase rotation circuit 8
3 and the cumulative addition and averaging circuits 85 and 86 can be replaced with cumulative addition and subtraction and averaging circuits 85A and 86A. For example, 0
When the ° / 180 ° phase rotation circuit 83 is configured by a conversion table using a ROM, the storage capacity of 128 kbytes (= 2 ¹⁶ × 16 bits) can be reduced. Therefore, the received signal phase detection block 8A may be used instead of the received signal phase detection block 8 in the conventional absolute phase synchronization acquisition circuit shown in FIG. 14, and in this case, the phase rotation of 0 ° / 180 ° is also possible. When the circuit 83 is configured by a conversion table using a ROM, the storage capacity of 128 Kbytes can be reduced.

In the absolute phase synchronization acquisition circuit according to the embodiment of the present invention, the remapper 11 converts the baseband signals i (8) and q (8) to θ.
Although the case where the phase rotation is performed for the case of = 45 ° is illustrated, the phase rotation of θ = 135 °, θ = 225 °, and θ = 315 ° may be performed.

In this case, in the logic conversion circuit 12 for obtaining the BPSK demapping output, the logic conversion circuit 1
2, when n = odd, that is, θ = 45 ° × n
In the case of (n = 1, 3, 5, 7), the conversion shown in FIG. 2A is left as it is, and when the phase is rotated by θ = 135 ° instead of FIG. 9) is performed, and when the phase is rotated by θ = 225 °, the logical conversion shown in FIG. 9B is performed. When the phase is rotated by θ = 315 °, the result is shown in FIG. 9C. The logic conversion is performed, and instead of the logic conversion shown in FIG. 3, the logic conversion shown in FIG. 9A, FIG. 9B, or FIG.
0 (b) or the logical conversion of FIG. 10 (c) may be performed.

Next, a description will be given of a first modification of the absolute phase synchronization acquisition circuit according to the embodiment of the present invention. FIG. 11 is a block diagram showing a configuration of a first modification of the absolute phase synchronization acquisition circuit according to one embodiment of the present invention.

A first modification of the absolute phase synchronization acquisition circuit according to the embodiment of the present invention is a frame synchronization detection block 2 in the conventional absolute phase synchronization acquisition circuit shown in FIG.
Is replaced with a frame synchronization detection block 2 '. Other configurations are the same as those of the conventional absolute phase synchronization acquisition circuit.

The frame synchronization detection block 2 '
As a K demapper, a BPSK demapper 30 shown in FIG.
The output B0 of the BPSK demapper 3A composed of 31 and 32,
B1, B2, and B3 are specially supplied to the synchronization detection circuits 40A, 41A, 42A, and 43A having the configuration shown in FIG. 5 and performing the logical operations in FIGS. The outputs SYNA0 and SYNB0, the outputs SYNA1 and SYNB1 of the synchronization detection circuit 41A, the outputs SYNA2 and SYNB2 of the synchronization detection circuit 42A, and the outputs SYNA3 and SYNB3 of the synchronization detection circuit 43A,
Frame synchronization detection circuit 5 provided with OR circuit shown in FIG.
A.

In the first modification of the absolute phase synchronization acquisition circuit according to the embodiment of the present invention configured as described above, in the frame synchronization detection block 2 ', the demodulated baseband signal I (8) , BPSK in response to Q (8)
The BPSK demapping is performed by the demapper 3A to obtain outputs B0, B1, B2, and B3, and the outputs SYNAα, SYNAα, and B4 are obtained by the synchronization detection circuits 40A to 43A in the same manner as the absolute phase synchronization acquisition circuit according to the embodiment of the present invention. SYN
Bα is obtained and sent to the frame synchronization circuit 5A, and the frame synchronization circuit 5A outputs a frame synchronization pulse.

According to the first modification of the absolute phase synchronization acquisition circuit according to the embodiment of the present invention, the size of the BPSK demapper 3A is only half the size of the BPSK demapper 3, and the size of the synchronization detection circuit is further reduced. The numbers are synchronous detection circuits 40A-4
With 4 of 3A, the scale is 1 / compared to the conventional case.
2 is enough.

Next, a description will be given of a second modification of the absolute phase synchronization acquisition circuit according to the embodiment of the present invention. FIG. 13 is a block diagram showing a configuration of a second modification of the absolute phase synchronization acquisition circuit according to one embodiment of the present invention.

A second modification of the absolute phase synchronization acquisition circuit according to the embodiment of the present invention is a frame synchronization detection block in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention shown in FIG. A frame synchronization detection block 2A 'is used in place of 2A. Note that the reception signal phase detection block remains unchanged.

The frame synchronization detection block 2A 'uses conventional synchronization detection circuits 40 to 47 instead of the synchronization detection circuits 40A to 43A. From the logic conversion circuit 12 shown in FIG. 6, the MSB of the inverted I (8), the MSB of the inverted i (8), the MSB of the inverted Q (8), and the inverted q (8) shown by the broken lines in FIG. ) Are taken out and output as B4, B5, B6, and B7 and sent to the synchronization detection circuits 40 to 47, respectively.
Output from SYNA0 to SYNA7, SYNB0 to SY
The NB 7 is transmitted to the frame synchronization circuit 5.

B generated by the logic conversion circuit 12A
Frame synchronization is detected based on outputs B0 to B7 which are PSK demapping outputs. In this case, the conventionally required BPSK demapper 3 is unnecessary, and the logic conversion circuit 12A having a simple configuration and a small scale is sufficient, so that the scale of the absolute phase synchronization acquisition circuit can be reduced.

[0088]

As described above, according to the absolute phase synchronization acquisition circuit according to the present invention, the circuit scale can be greatly reduced, and the chip area can be effectively reduced when the absolute phase synchronization acquisition circuit is formed into an IC. The effect that it can be used is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an absolute phase synchronization acquisition circuit according to an embodiment of the present invention.

FIG. 2 is a diagram showing a truth table of a logic conversion circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention;

FIG. 3 is a diagram showing a truth table of a logic conversion circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention;

FIG. 4 is a block diagram illustrating a configuration of a logic conversion circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention.

FIG. 5 is a block diagram showing a partial configuration of a synchronization detection circuit in the absolute phase synchronization acquisition circuit according to one embodiment of the present invention.

FIG. 6 is a diagram showing a truth table of a logical operation performed by the synchronization detection circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention.

FIG. 7 is a diagram showing a truth table of a logical operation performed by the synchronization detection circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention.

FIG. 8 is a block diagram showing a partial configuration of a frame synchronization circuit in the absolute phase synchronization acquisition circuit according to one embodiment of the present invention.

FIG. 9 is a diagram showing a truth table of a logic conversion circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention;

FIG. 10 is a diagram showing a truth table of a logic conversion circuit in the absolute phase synchronization acquisition circuit according to the embodiment of the present invention.

FIG. 11 is a block diagram showing a configuration of a first modification of the absolute phase synchronization acquisition circuit according to one embodiment of the present invention;

FIG. 12 is a block diagram showing a configuration of a BPSK demapper in a first modification of the absolute phase synchronization acquisition circuit according to one embodiment of the present invention;

FIG. 13 is a block diagram showing a configuration of a first modification of the absolute phase synchronization acquisition circuit according to one embodiment of the present invention;

FIG. 14 is a block diagram showing a configuration of a conventional absolute phase synchronization acquisition circuit.

FIG. 15 is a signal point arrangement diagram for explaining BPSK mapping;

FIG. 16 is an explanatory diagram provided for explanation of BPSK demapping;

FIG. 17 is a block diagram illustrating a configuration of a part of a synchronization detection circuit in a conventional absolute phase synchronization acquisition circuit.

FIG. 18 shows a BP in a conventional absolute phase synchronization acquisition circuit.
It is a block diagram which shows the structure of SK demapper.

FIG. 19 is a block diagram showing a partial configuration of a frame synchronization circuit in a conventional absolute phase synchronization acquisition circuit.

FIG. 20 shows 0 ° in a conventional absolute phase synchronization acquisition circuit.
FIG. 10 is a signal point arrangement diagram of a frame synchronization signal after passing through a / 180 ° phase rotation circuit.

FIG. 21 is a diagram provided for explanation of a reception phase determination table.

[Explanation of symbols]

 Reference Signs List 1 demodulation circuit 2A frame synchronization detection block 3 and 3A BPSK demapper 40-47, 40A-43A synchronization detection circuit 5 and 5A frame synchronization circuit 6 frame synchronization signal generation circuit 7 and 11 remapper 8 and 8A reception signal phase detection block 12 logical conversion Circuits 85A and 86A Cumulative addition / subtraction averaging circuit 87 Received signal phase determination circuit 125 Multiplexer 121-124 Inverter

Claims (1)

[Claims] An absolute method for acquiring a frame synchronization signal, detecting a reception signal phase rotation angle with respect to a transmission signal phase angle from the acquired frame synchronization signal, and making the reception signal phase angle coincide with the transmission signal phase angle to form an absolute phase. In the phase synchronization acquisition circuit, a bit stream of the frame synchronization signal is extracted from the demodulated baseband signal over the frame synchronization signal section, and when the extracted bit stream of the frame synchronization signal is logic {1}, an addition process is performed. When the bit stream of the synchronizing signal is logical {0}, subtraction processing is performed, and accumulative addition / subtraction averaging processing means for averaging the addition / subtraction processing result is provided. An absolute phase synchronization acquisition circuit that rotates the phase of a demodulated baseband signal by an amount.