JPH11273247A - Simulator for recording medium driver - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simply and accurately evaluate under actually installed conditions the characteristic of a single driver suitable for a medium, a read/write-head, and the like by means of a simulator for a recording medium driver. SOLUTION: A simulator for a recording medium driver has a pseudo signal input means 31, an output data collecting means, a control means 36, and an evaluating means 37, wherein a recording medium driver 30 having a reading circuit for demodulating a medium reading signal and/or a writing circuit for modulating and outputting medium writing data is evaluated by varying a driver characteristic and inputting a pseudo signal. Further, a data setting file 34 in which setting data for setting the driver characteristic is filed in a prescribed form corresponding to this driver is provided, and the control means 36 transfers setting data to a driver referring to the file and performs simulation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a simulator for a recording medium driver, for example, a hard disk drive (HDD).

In recent years, writing circuits and reading circuits for media such as hard disks have been integrated into ICs.
The characteristics of each circuit can be set from outside so as to be compatible with the medium type, read / write speed, and the like. Then, the driver (hereinafter, IC,
Or module)), input a pseudo signal according to the characteristics of the head and the like, measure the error rate, evaluate the developed IC, evaluate the characteristic setting conditions for specific head and other device conditions, etc. It is carried out.

[0003] This evaluation system uses a personal computer (PC) as a control device, and is composed of an arbitrary waveform generator for generating a pseudo read signal, a pattern generator for generating a timing signal and a write signal, a logic analyzer for capturing an output signal, and the like. However, it takes a long time to set the characteristics to evaluate with various characteristics of the IC, the evaluation may be incorrect when influenced by noise, the memory capacity for data collection is insufficient, or the actual head characteristics are required. There are various problems, for example, it is difficult to easily obtain such a nonlinear pseudo signal. Therefore, there is a need for a recording medium driver simulator device that solves the above problems.

[0004]

2. Description of the Related Art FIG. 12 is a diagram showing an example of an HDD driver circuit, and FIG. 13 is a diagram showing a configuration of a conventional simulator.

FIG. 12 shows an example of a read / write circuit for a magnetic disk. FIG. 12- (1) is a circuit block diagram for demodulating a read signal from a read head to NRZ data. (2) shows a circuit block diagram until the NRZ write data is modulated into a write signal to the write head.

As shown in FIG. 12- (1), the read circuit includes an AGC circuit, a pre-filter circuit, a sample holder circuit, an equalizer circuit, a maximum likelihood detection circuit, a decoder, an S /
It is composed of a P conversion circuit and the like, and converts an analog signal read by a read head into NRZ data.

On the other hand, the write circuit comprises a P / S conversion circuit, an encoder, a precoder, a write precompetition circuit, a direct write control circuit, a write FF, etc.
The Z write data is converted into a write signal to the write head.

The read circuit and the write circuit have a P / S
A conversion circuit and an S / P conversion circuit, an encoder and a decoder are integrated, and the NRZ bus is configured bidirectionally.
Each is made into an IC and is made into a module as a driver.

FIG. 13 shows an example of a configuration for simulating a module in which the above-described read circuit and write circuit are integrated by function (read function is read circuit module 1a, write function is write circuit module 1b). .

The simulator includes a personal computer PC 2 as a control device, and an arbitrary waveform generator 1 for generating a read pseudo signal.
1, a pattern generator 12 that generates timing signals such as write NRZ data and gate signals, a logic analyzer 9 that captures and records output data along with an acquisition time, and a DC power supply, and are connected by a GPIB bus.

When simulating the read function,
First, characteristic data is set in a plurality of internal registers (hereinafter, registers) 10a. The setting for the register 10a is, for example, AG
There are dozens of items such as setting of the pull-in time for C, and setting of the frequency for the equivalent filter, and these settings are set by the operator inputting from the PC2. When this setting is completed, the simulation is ready and the pattern generator
12 to output a read gate signal to set the module to the read state, and to the arbitrary waveform generator 11, for example, P
A CM signal is output to output a read dummy signal.

The read circuit module 1a includes a register 10a
The characteristic is set based on the data set in (1), and the received pseudo signal is demodulated based on the set characteristic, and NRZ data is output. Lead circuit module 1a
Outputs the read clock Rclock together with the output data, so that the logic analyzer 9 synchronizes with this clock, fetches the output data with the rising of the read gate signal as a start signal, and logs the data together with the time data in the internal memory.

In this manner, the PC 2 stores the register 10a
To the logic analyzer 9 by sequentially changing the data setting to the register setting, generating a pseudo signal for reading a series of block data having various combinations of bit strings in the arbitrary waveform generator 11 with a certain gap for each register setting. The error rate is verified by comparing the obtained data with the expected value, and the optimum register setting data for the waveform of the input pseudo signal is obtained.

The output waveform of the arbitrary waveform generator 11 is determined by a medium, a head, and the like used. Similarly, for the simulation of the write function, the characteristic data is set in the register 10b, and the pattern generator 12
More various NRZ pattern data is input, and the output write data (WD) is collected and compared with an expected value to evaluate the write circuit module 1b. However, in this case, since no clock is output, the collection mode of the logic analyzer 9 is changed, the write data WD is collected by edge detection, and the data is identified at a clock interval set in advance by the user on the PC.

[0015]

As described above,
The characteristics of the recording medium driver are set according to the device conditions, for example, the head, medium, and the like to be used. However, since the setting data is determined by the above-described simulation, a more precise simulation is required. Similarly, it is necessary to rigorously evaluate newly developed modules.

However, since the driver to be simulated inputs data from an external circuit or collects data in the external circuit, there is a possibility that precise simulation may be hindered, which is different from the apparatus conditions. This is for example
In order to perform a simulation, it is necessary to set several tens of items of data. However, it takes time to set by an operator's operation input, and data may not be set correctly due to the influence of noise or the like. , The memory capacity of the logic analyzer is insufficient unless only valid data is collected, the read signal is generally non-linear, and it is extremely difficult to generate a pseudo signal according to the actual situation.
If unnecessary data is collected, it is difficult to discriminate between block data.If output data is not output together with the clock, data is collected by edge detection. is there.

An object of the present invention is to provide a simulator for a recording medium driver capable of accurately performing a simulation by a simple method in view of the above problems.

[0018]

In order to solve the above-mentioned problems, the present invention is configured as follows as shown in the principle diagram of the present invention in FIG. (1) First invention The first invention has a reading circuit for demodulating a medium reading signal, comprising a pseudo signal input means 31, an output data collecting means 40, a control means 36, and an evaluating means 37, and / or Recording medium driver having write circuit for modulating and writing medium write data
30 is a simulator device of the recording medium driver 30 for inputting a pseudo signal while changing driver characteristics, obtaining output data, and comparing the output data with an expected output value for evaluation, wherein the driver characteristics are set. A data setting file 34 in which setting data to be performed is filed in a predetermined format corresponding to the driver 30 is provided. The control means 36 transfers the setting data to the driver 30 while referring to the file 34, and performs a simulation.

As described above, the setting data for setting the driver characteristics is stored in the data setting file 34 in a data format corresponding to the driver, and the driver characteristics are set while referring to the file 34 to perform the simulation. The time required to set data in the simulation is greatly reduced, and simulation efficiency can be improved. (2) Second invention According to the second invention, in the first invention, a buffer means 35 is provided between the control means 36 and the recording medium driver 30, and the impedance is set to a high impedance except during the data setting period. The means 36 and the recording medium driver 30 are insulated.

As described above, since the control means 36 and the recording medium driver 30 are insulated from each other except for the time for transmitting the setting data, noise caused by the transmitting device, the line, etc. is removed, and the setting mistake is greatly reduced. Be reduced. (3) Third invention A third invention is a reading circuit which includes a pseudo signal input means 31, an output data collecting means 40, a control means 36, and an evaluation means 37, and demodulates a medium read signal and / or Recording medium driver having write circuit for modulating and writing medium write data
30 is a simulator device of the recording medium driver 30 for inputting a pseudo signal while changing driver characteristics, obtaining output data, and comparing the output data with an output expected value to evaluate the output data. Based on the output read clock and a predetermined timing signal, a capture clock generating means 39 is provided for generating a clock for capturing output data in data block units, and the output data collecting means 40 includes a clock output from the capture clock generating means 39. Collect output data based on

As described above, unnecessary data is removed, so that the memory capacity of the output data collecting means 40 (such as a logic analyzer) is saved, and simulation efficiency is improved. (4) Fourth Invention A fourth invention is a reading circuit which has a pseudo signal input means 31, an output data collecting means 40, a control means 36, and an evaluation means 37, and which demodulates a medium read signal and / or Recording medium driver having write circuit for modulating and writing medium write data
30 is a simulator device of a recording medium driver 30 for obtaining output data by inputting a pseudo signal while changing driver characteristics, comparing the output data with an expected output value, and evaluating the output data. A conversion table file 33 for converting a pseudo signal into a waveform corresponding to the characteristics of the medium reading head is provided.
, A pseudo signal corresponding to the medium reading head is input.

As described above, a pseudo signal of an ideal waveform can be converted into an actual pseudo signal by the conversion table file 33, and a simulation can be performed in accordance with device conditions. (5) Fifth invention A fifth invention is a reading circuit which has a pseudo signal input means 31, an output data collecting means 40, a control means 36, and an evaluation means 37, and which demodulates a medium read signal and / or Recording medium driver having write circuit for modulating and writing medium write data
30 is a simulator device of the recording medium driver 30 for inputting a pseudo signal while changing driver characteristics, obtaining output data, comparing the output data with an expected output value, and evaluating the output data. The predetermined pattern data is inserted, and the evaluation unit 37 searches the output data collected by the output data collection unit 40 for the pattern data and recognizes the beginning of the output data. (6) Sixth invention A sixth invention is a reading circuit for demodulating a medium reading signal, comprising a pseudo signal input means 31, an output data collecting means 40, a control means 36, and an evaluating means 37, and / or Recording medium driver having write circuit for modulating and writing medium write data
30 is a simulator device of the recording medium driver 30 which inputs a pseudo signal while changing the driver characteristics, detects and obtains output data by detecting a change point thereof, and compares and evaluates the output data with an expected output value. A data rate detector 38 is provided for determining a time distribution between output data change points and determining a data rate of the data, and analyzes collected output data based on the detected data rate.

As described above, even when the output data is not output together with the clock, the output data can be correctly read.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings. Note that the same reference numerals represent the same object throughout the drawings.

FIG. 2 is a block diagram of one embodiment, FIG. 3 is a diagram showing an example of a register setting file, FIG. 4 is a diagram showing an example of a buffer circuit, FIG. 5 is a time chart of FIG. 4, and FIG. 7, FIG. 7 is a diagram showing an example of a fetched clock generation circuit, FIG. 8 is a time chart of FIG. 7, FIG. 9 is a diagram showing an example of a head recognition method of fetched data, FIG. FIG. 11 is an explanatory diagram of correction.

Hereinafter, the simulator of the HDD driver will be described. FIG. 2 is a configuration diagram of the simulator. The means shown by broken lines in the figure are means necessary for performing a read simulation, and the other parts are common to the write simulation.

In FIG. 2, reference numeral 11 denotes an arbitrary waveform generator, which has a digital-to-analog conversion function, converts a PCM signal output from the pseudo signal generator 5 of the PC 2 into an analog signal, and outputs a read pseudo signal.

Numeral 1 is a module of a driver to be simulated, which comprises a read circuit and a write circuit. The module 1 has a configuration as shown in FIG. When WG is input, it is set to the light mode,
Performs a read operation and a write operation, respectively.

Reference numeral 12 denotes a pattern generator which outputs a read gate signal RG based on an instruction from the PC 2 when setting the module 1 to the read mode, and outputs a capture timing signal to be described later. When the module 1 is set to the write mode, a write gate signal WG is output. In the write mode, NRZ pattern data is output at the same time as instructed by PC2.

Reference numeral 2 denotes a personal computer PC for controlling and evaluating the simulator, which includes a register setting file 3a (corresponding to the data setting file 34 in FIG. 1) and a conversion table file 3b, which will be described later, and input data and corresponding output data expected. A file such as a data output data expected value file 3c comparing the values, a data setting unit 4 for setting data in the register 10 of the module 1, and a conversion table file 3b
And a data rate detecting section 6 for determining a data rate of data collected in the write mode.

Numeral 7 denotes a buffer circuit which sets the output impedance to a high impedance (Hi-Z) by a gate signal output from the PC 2 during a period other than transmitting data set in the register 10, and connects the PC 2 and the module 1 to each other. Insulate.

Reference numeral 9 denotes a logic analyzer which fetches output data from the module 1 in synchronization with a fetch clock and stores it in an internal memory. Alternatively, the change point of the output data is recorded as time data. Reference numeral 8 denotes a capture clock generation circuit, which generates a clock for capturing valid data in data block units from a read clock in accordance with a capture timing signal.

For example, when a simulation of the read function is performed by the simulator having the above configuration, the simulation is performed in the following procedure. In the case of the read simulation, the first register setting of the module 1 is first performed by the simulation start instruction. The data setting unit 4 reads the setting data from the register setting file 3a and outputs the specified data to the buffer circuit 7 in the specified data format.

The buffer circuit 7 gates the register setting data with a gate signal output simultaneously from the PC 2 and outputs it to the module 1. When the register setting is completed, the read gate signal RG is output from the pattern generator 12 in accordance with the instruction from the PC 2, and the module 1 enters the read mode. Subsequently, PC2 receives a digital pseudo signal (PC
M) is output to the arbitrary waveform generator 11, and the arbitrary waveform generator 11 converts the digital signal into an analog signal, and outputs the analog signal to the read signal input terminal of the module 1 as a read pseudo signal. As a result, the read circuit of the module 1 demodulates the read pseudo signal into NRZ data and outputs it to the NRZ data bus together with the read clock Rclock.

The read clock Rclock output together with the NRZ data is generated as a capture clock by the capture clock generation circuit 8 and input to the logic analyzer 9. As a result, the logic analyzer 9 collects the NRZ data output from the module 1 in synchronization with the fetch clock and stores the NRZ data together with the time data in its own memory.

The read pseudo signal is composed of a plurality of block signals in which different bit data are combined, and is input at a predetermined gap interval. The block signal is
For example, the input data of the output data expected value file 3c is read out in the order of storage, converted into a PCM data sequence of an ideal waveform, and the one converted to an actual waveform by the conversion table file 3b is used.

When data collection is completed for a series of block data in this manner, the register 10 is reset and the next simulation similar to the above-described processing is performed.
In the case of the write simulation, since a series of NRZ pattern data for writing specified by the PC 2 is output from the pattern generator 12 after the above-described register setting, the write circuit of the module 1 performs processing such as encoding, and then performs the WD terminal Output the write data WD. In this case, since the read clock Rclock is not output, the logic analyzer 9 detects the edge of the write data WD and records the time data.

After the output data is collected by the logic analyzer 9 as described above, the evaluation unit 20 of the PC 2 performs an evaluation process. In this process, the head of the collected output data is recognized, and the expected value in the output data expected value file 3c is compared with the corresponding output data to evaluate the performance based on an error rate or the like. At this time, for the write data, the data obtained by obtaining the data rate by the data rate detection unit 6 is identified.

The read / write simulation is performed as described above. The details of the invention will be described below. FIG. 3 shows the contents of the register setting file 3a. Here, [FF: FF: FF on the first line of the file 3a
F] is a line representing the description format of the following item in FIG.
After the line, [Address:
Data] is specified. According to the first row, the data of the second and subsequent rows are as follows: Address length: 8 bits, Data length: 8 bits Address: MBS Fast, Data: LSB
Fast Address: + (High active) Data: + (High active) Other signal polarities (clock, gate):-(Low)
Active) Transfer method: Parallel. Based on these data, the register setting data is output by the data setting unit 4 together with the clock and the gate signal.

FIG. 4 shows an example of a buffer circuit, in which a gate 7a is provided for each signal line, and the output of the gate 7a is controlled by a gate signal except during the period when input data (register setting data) is output. Becomes high impedance (Hi-z). As a result, PC2 and module 1
Are isolated from each other, so that the influence of noise due to unnecessary data is reduced. FIG. 5 is a timing chart of FIG. 4. In the gate signal, unnecessary data except for a short period before and after valid data (input data) is removed by the gate signal, and the register setting data (output data) is removed. Is input to the module 1. As a result, the register setting data from which unnecessary data has been removed is input to the I / O port in the module 1, and the erroneous setting due to noise is smaller than when input data is cut off by a gate signal inside the module. Can be even better prevented.

FIG. 6 shows an example of data acquisition. In this figure, a capture gate signal indicating only the necessary data portion is created separately from the read gate signal, and the read gate signal and the read clock Rclock output from the module 1 are generated.
And, the output is input as Rclock to the logic analyzer 9 as the capture section clock. Since only the necessary data portion is output as Rclock, unnecessary data such as gap portions is not taken in.
The internal memory of the logic analyzer 9 can be saved.

However, in such a case, since the logic analyzer 9 does not normally recognize the end of the read gate signal RG, the logic analyzer 9 recognizes the boundary with the next data block unless the data in the gap portion is taken in. There is a risk that the next block cannot be confused as continuous data.

As a countermeasure, there is a method in which the end of the read clock is delayed by several clocks from the fetch timing signal. FIG. 7 shows an example of this circuit.
17, the trailing edge of the fetch timing signal is delayed by two clocks (2D) as shown in FIG. This makes it possible to recognize between data blocks. The delay time is not limited to two clocks, but may be any length as long as a data block can be identified.

FIG. 9 shows another method for identifying a data block. This method uses SB at the beginning of the data.
A (Synchro Byte) pattern is added, and the head of the data is recognized by comparing the expected output value with the collected data. FF 1111111 as SB pattern
If this bit is set to 1, the data acquisition gate is enabled a few bytes before and the acquired data is
And recognizes the subsequent data as data.

Next, in the write simulation, when the write data WD is taken into the logic analyzer 9, Rc
Since lock is not output, only the change point of output data is recognized and logged. In this case, the data rate detector 6
Detects the data rate by statistically processing the time interval between the change points. FIG. 10 shows statistics of the time intervals of the acquired data. If the time of the first peak value is T, 1 / T is the data rate of this data. To be more precise, T1, T2, and T3 maintain an integral multiple relationship, and 1 / T at which the error with respect to each peak value is Min is defined as the data rate.

As described above, when the change point of the output data is logged, the data rate can be accurately calculated by the statistical processing of the time interval, and the module 1 can be accurately evaluated.

FIG. 11 shows a method of correcting a pseudo signal used in a read simulation. A correspondence table of X values and Y values as a table shown in (a) is used as a transfer characteristic file and read by the pseudo signal generation unit 5 so that the characteristics of the actual magnetic recording system can be added.
In the embodiment, the conversion table shown in (b)
In response to the input of the ideal waveform as shown in FIG. In addition,
The samples between (b) and (b) are complemented by a straight line or a curve approximation.

As described above, register setting data of the module to be simulated can be input simply and with noise removed, and only valid output data can be taken in a data block identifiable manner to save memory capacity. , The pseudo signal can be made closer to the actual signal. As a result, it is possible to easily perform a precise simulation based on the actual situation.

[0049]

As described above, according to the present invention,
File setting data to automatically set the characteristics of the module to be simulated, input a large number of setting data while eliminating noise, capture only valid output data, save memory capacity, generate pseudo input signals By approaching the signal, the simulation is performed precisely.When collecting data at the changing point of the log data, the data rate is accurately measured and statistically recognized by the statistical processing of the collected data. Since it has means to easily identify the head, etc.,
The simulation of the recording medium driver (read / write circuit) and the simulation for obtaining the setting data of the driver characteristics according to the device conditions can be easily and precisely performed.

[Brief description of the drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a configuration diagram of an embodiment.

FIG. 3 is a diagram showing an example of a register setting file.

FIG. 4 is a diagram illustrating an example of a buffer circuit.

FIG. 5 is a time chart of FIG. 4;

FIG. 6 is a diagram showing an example of data acquisition;

FIG. 7 is a diagram illustrating an example of a capture clock generation circuit;

FIG. 8 is a time chart of FIG. 7;

FIG. 9 is a diagram illustrating an example of a method of recognizing the head of captured data.

FIG. 10 is an explanatory diagram of a data rate determination method.

FIG. 11 is an explanatory diagram of correction.

FIG. 12 illustrates an example of an HDD driver circuit.

FIG. 13 is a configuration diagram of a conventional simulator.

[Explanation of symbols]

1 Module 2 PC 3 File 3a Register setting file 3b Conversion table file 3c Output data expected value file 4 Data setting unit 5 Pseudo signal generation unit 6 Data rate detection unit 7 Buffer circuit 7a Gate 8 Capture clock generation circuit 9 Logic analyzer 10 Register 10a , 10b register 11 arbitrary waveform generator 12 pattern generator 15,18 NAND circuit 16,17 D / FF 19 AND circuit 20 output data expected value file 30 recording medium driver 31 signal input means 32 internal register 33 conversion table file 34 data setting file 35 Buffer means 36 Control means 37 Evaluation means 38 Data rate detection means 39 Acquisition clock generation means 40 Output data collection means

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Yasuhiko Takahashi 4-1-1, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture Inside Fujitsu Limited (72) Inventor Kazunari Matsumoto 4-chome, Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa No. 1 in Fujitsu Limited

Claims (6)

[Claims] 1. A read circuit for demodulating a medium read signal and / or a write circuit for modulating and writing medium write data, comprising a pseudo signal input means, an output data collection means, a control means, and an evaluation means. A recording medium driver having a circuit, a simulation device of a recording medium driver that inputs a pseudo signal while changing driver characteristics, obtains output data, and compares the output data with an expected output value to evaluate the output data; Providing a data setting file in which setting data for setting driver characteristics is filed in a predetermined format corresponding to the driver, wherein the control means transfers the setting data to the driver while referring to the file and performs a simulation. A simulator device for a recording medium driver. 2. A buffer means is provided between the control means and the recording medium driver, and the output of the buffer means is set to a high impedance during a period other than a data setting period, so that a buffer means is provided between the control means and the recording medium driver. 2. The simulator device for a recording medium driver according to claim 1, wherein the recording medium driver is insulated. 3. A read circuit for demodulating a medium read signal and / or a write for modulating and writing medium write data, comprising a pseudo signal input means, an output data collecting means, a control means, and an evaluation means. A recording medium driver having a circuit, a pseudo-signal being input while changing driver characteristics, obtaining output data, and comparing the output data with an expected output value to evaluate the recording medium driver; A capture clock generator for generating a clock for capturing output data in data block units based on a read clock output from the recording medium driver and a predetermined timing signal is provided, and the output data collection means outputs the clock from the capture clock generator. A recording medium driver simulator for collecting output data based on a clock to be output. 4. A reading circuit having a pseudo signal input means, an output data collecting means, a control means, and an evaluation means, and a reading circuit for demodulating a medium read signal and / or a write for modulating and writing medium write data. A recording medium driver having a circuit, a pseudo-signal being input while changing driver characteristics, obtaining output data, and comparing the output data with an expected output value to evaluate the recording medium driver; A conversion table file is provided for converting a pseudo signal to the reading circuit into a waveform corresponding to the characteristics of the medium read head, and the pseudo signal input means refers to the conversion table file and inputs a pseudo signal corresponding to the medium read head. A recording device driver simulator device, characterized in that: 5. A read circuit which includes a pseudo signal input means, an output data collection means, a control means, and an evaluation means, and modulates a read circuit for demodulating a medium read signal and / or a medium write data and outputs the data. A simulation apparatus for a recording medium driver for evaluating a recording medium driver having a circuit by inputting a pseudo signal while changing driver characteristics, obtaining output data, and comparing the output data with an expected output value. A recording medium wherein predetermined pattern data is inserted at the beginning of a signal, and said evaluation means recognizes the beginning of output data by searching for said pattern data in output data collected by said data collection means. Driver simulator device. 6. A read circuit for demodulating a medium read signal and / or a write circuit for modulating and writing medium write data, comprising pseudo signal input means, output data collection means, control means, and evaluation means. A recording medium driver for evaluating a recording medium driver having a circuit by inputting a pseudo signal while changing driver characteristics, detecting and acquiring output data at a change point thereof, and comparing the output data with an expected output value. The simulator device according to claim 1, further comprising: a data rate detection unit that determines a data rate of the output data by determining a time distribution between change points of the output data, and analyzes data collected based on the data rate. Simulator device for recording media driver.