JPH11272629A - Data processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the data processor of small heat generation or a small temperature fluctuation width capable of a high speed data processing arithmetic operation. SOLUTION: Plural processors capable of low power consumption mode control are used as parallel processors and slave processors 311, 321, 331 and 341 capable of the low power consumption mode control are controlled to a low power consumption mode when a data processing arithmetic operation is not required. When the data arithmetic operation is required, the slave processors 311 or the like are separately controlled to the low power consumption mode when the respective slave processors 311, 321, 331 and 341 do not perform the arithmetic operation and the time when the slave processors perform an arithmetic operation redundantly with each other is reduced. Thus, absolute heat generation is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to industrial equipment which requires data processing of so-called images such as defect inspection, image recognition, image alignment, image observation, imaging, etc., namely, semiconductor inspection equipment, semiconductor manufacturing equipment, and electronic equipment. The present invention relates to a data processing device such as a microscope, an electron beam drawing device, a medical examination device, and a medical diagnostic device.

[0002]

2. Description of the Related Art Examples of the above-mentioned industrial equipment include a semiconductor inspection apparatus and an electron microscope described in JP-A-8-7818, JP-A-7-220077, and JP-A-7-21965. There is. In these semiconductor inspection devices, a shape such as a contact hole or a line pattern is obtained by performing two-dimensional or three-dimensional image processing from an electric signal obtained from an inspection object or the like.

[0003] In addition, medical examination apparatuses and medical diagnosis apparatuses described in literatures (Basic NMR Medicine and Clinical Practice, edited by The Magnetic Resonance Society of Japan, Maruzen, 1991) require that image data obtained from an inspection object be processed. By performing two-dimensional or three-dimensional FFT operation and two-dimensional or three-dimensional image processing, a tomographic image is obtained.

[0004] In these image processing, especially in three-dimensional image processing, the data amount and the amount of calculation are enormous, and
As described above, applications of these devices require so-called real-time performance and high-speed performance such as inspection and diagnosis, and are described in, for example, literature (Electronics, Ohmsha, October 1995 separate volume). As described, the MPU (Micro Processesi
ng Unit), CPU (Central Proc)
essing Unit), RISC (Reduced)
Instruction Set Compute
r), CISC (Complex Instructi)
on Set Computer), DSP (Digi)
For example, a so-called parallel processor architecture in which a plurality of processors called a "tal Signal Processor" or the like are used to increase the arithmetic processing capability is employed.

[0005]

By the way, with the advance of the semiconductor technology, the operating frequency of the above-mentioned parallel processor has recently exceeded 20 MHz, and furthermore, the literature (Electronic Materials, Industrial Research Committee, April 1997) has been published. As described, those exceeding 200 MHz have been put to practical use.

However, as the operating frequency increases, the heat generated by the processor, its peripheral ICs, and the substrate increases approximately in proportion to the operating frequency of the processor. That is, the case of the operating frequency of 20 MHz and the case of 200 MHz
In the case of the operating frequency of z, there is a difference of about 10 times the heat generation amount. In the architecture of a parallel processor using a plurality of these processors, the ambient heat rises because the total heat generation during operation other than the desired image processing operation becomes considerable.

FIG. 6 shows the relationship between the power consumption of the parallel processor and the rise in the ambient temperature as an example. Generally, the ambient temperature rise ΔT (° C.) from the heat source is given by the following equation (1). ΔT = Q / (γ · Cp · V) (1) In the above equation (1), Q is the calorific value of the heat source, and the unit is Kcal / hr. Γ is the specific weight of air, about 1.1 kgf / m ³ , Cp is the specific heat of air, about 0.24 Kcal / kgf · ° C., V is the exhaust capacity of the air cooling fan, and the unit is m ³ / Hr.

[0008] Here, the heat source is set to about 30 W / unit, which is the power consumption of the processor of the above-mentioned document, and the number of units in parallel is set to four units described later. However, in actual use,
The number of parallel processors is not limited to four.

The exhaust capacity of the air-cooling fan is set to about 60 m ³ / hr from an appropriate size that can be incorporated in the image processing apparatus. As described above, although there are parameters that cannot be uniquely determined in the above equation (1), the numerical values can be roughly grasped, and if four processors with power consumption of about 30 W / piece are used, the ambient temperature becomes about 6 It rises by over ℃.

On the other hand, in the above-mentioned industrial equipment, for example, in a semiconductor inspection apparatus, a semiconductor manufacturing apparatus, an electron microscope, an electron beam lithography apparatus, etc., one of the means for improving the yield is ± 1 as one of means for improving the yield as the semiconductor design rule becomes finer. In most cases, it is used in a clean room where the temperature is strictly controlled with an accuracy of about ° C.

That is, the image processing apparatus is required to reduce the absolute heat generation and, if the calculation is such that the heat generation is large, to have an adverse effect on a precision mechanical system such as an electron beam or an optical lens. In order to reduce as much as possible, it is necessary to have at least a processor capable of managing the relationship between the amount of calculation and the heat generation so that the fluctuation range from the rise value can be controlled to an accuracy of about ± 1 ° C. In addition, medical examination devices, medical diagnosis devices, and the like are mostly used in air-conditioned rooms in consideration of patient friendliness.

As described above, in these industrial devices, while high-speed data processing calculations as described above are required, it is necessary to suppress unnecessary heat generation as much as possible or to suppress the temperature fluctuation width as much as possible. Has been
In the prior art, it has not been possible to satisfy the high-speed data processing calculation and the suppression of unnecessary heat generation and the suppression of the temperature fluctuation width.

The present invention has been made in view of the above points, and an object of the present invention is to realize a data processing device capable of performing high-speed data processing calculations and having a small heat generation amount or a small temperature fluctuation range. is there.

[0014]

The present invention is configured as follows to achieve the above object. (1) In a data processing device having a parallel processor in which a plurality of processors that generate heat by calculation are used to increase the calculation processing capacity, at least one of the plurality of processors has low power consumption such as a sleep mode or a standby mode. A data processing device characterized by a processor capable of power mode control.

A processor capable of controlling a low power consumption mode such as a sleep mode or a standby mode consumes low power and can generate a small amount of heat in the low power consumption mode.

(2) Preferably, in the above (1),
During a period in which the data processing operation is unnecessary, the processor capable of controlling the low power consumption mode is controlled to the low power consumption mode.

In industrial equipment, data processing operations are not required for a considerable amount of time. Therefore, if all the processors capable of controlling the low power consumption mode are controlled to the low power consumption mode during this time, the industrial equipment can be used. Calorific value can be reduced.

(3) Preferably, in the above (1) or (2), only the processor that needs to operate among the plurality of processors is operated, and the others are set to the low power consumption mode. The operation is controlled so as to suppress the time for the processor to execute the operation redundantly.

If there is a processor that does not need the operation even during the operation, the amount of heat generated during the operation can be reduced by controlling the processor to the low power consumption mode.

(4) Preferably, in the above (3), it is determined whether or not the temperature of the data processing device is higher than a temperature obtained by adding a predetermined temperature and lower than a temperature obtained by subtracting the predetermined temperature. If the temperature of the data processing device exceeds the temperature obtained by adding the predetermined temperature, the time for a plurality of processors to execute the operation in duplicate is suppressed, and the temperature of the data processing device is reduced to the temperature obtained by subtracting the predetermined temperature. If less than
This increases the time for multiple processors to execute operations in duplicate.

It is determined whether the temperature of the data processing device exceeds or falls below a temperature obtained by adding or subtracting a predetermined temperature.
If control is performed so as to suppress or increase the time during which a plurality of processors execute operations repeatedly, the temperature fluctuation of the data processing device can be reduced and kept within a certain temperature range.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is an overall schematic configuration diagram of an electron microscope apparatus to which a data processing apparatus according to an embodiment of the present invention is applied. Note that the data processing apparatus of the present invention is mounted on the above-described industrial equipment and is disposed in a clean room or a room where air conditioning is controlled, but these figures are omitted here.

In FIG. 1, reference numeral 101 denotes a mirror portion of an electron microscope. An electron beam 103 emitted from an electron gun 102 is converged by an electron lens and irradiated on a sample 105. The intensity of secondary electrons or reflected electrons generated from the surface of the sample 105 by electron beam irradiation is measured by the electron detector 10.
6 and amplified by the amplifier 107.

Reference numeral 104 denotes a deflector for moving the position of the electron beam. The electron beam 103 is raster-scanned on the surface of the sample 105 by a control signal 108 from a control computer 110. After the signal output from the amplifier 107 is A / D converted, the image processing device 109 performs an image processing operation. The data processing device according to the embodiment of the present invention corresponds to this portion. Reference numeral 111 denotes a peripheral device such as a display device that displays the image data and a storage device that records the image data.

The data processing device of the present invention uses a processor capable of low power consumption mode control, that is, a processor capable of stopping operation in accordance with a stop command from a master processor or the like. The power consumption of the processor capable of the low power consumption mode control is about 0.5 W or less / processor. FIG. 6 shows the relationship between the power consumption of the parallel processors and the rise in ambient temperature when the number of parallel processors is four. In actual use, the number of parallel processors is not limited to four.

As shown in FIG. 6, the power consumption is about 0.5 W
With four / less processors, the ambient temperature rises only about 0.1 ° C. On the other hand, when four processors each having the above-described power consumption of about 30 W / piece are used, the ambient temperature increases by about 6 ° C. or more.

By the way, in the above-described industrial equipment, for example, when data is transferred between a higher-level control computer for controlling the image processing operation device and a peripheral device, or when an interface between a higher-level control computer and a user is used, image processing is performed. There is also a considerable amount of time in which calculations are not required.

Therefore, according to the present invention, in the above-described industrial equipment, the data processing operation is not required for a considerable amount of time. During this time, the processors capable of controlling the low power consumption mode are all provided with low power consumption. Mode, and at the time of data processing operation, as described later, only the processors that need to operate among the plurality of processors are operated, and the others are set to the low power consumption mode, and the plurality of processors are overlapped. By controlling the operation so as to suppress the time for executing the calculation, the amount of heat generated by the parallel processor is reduced.

FIG. 2 is a block diagram of the image processing apparatus 109 according to an embodiment of the present invention. In the architecture of a parallel processor that performs high-speed image processing, FIG.
FIG. 11 is a block diagram of an image processing apparatus using a processor capable of performing the above-described low power consumption mode control in which at least one of the processors is generally called a sleep mode or a standby mode.

In FIG. 2, reference numeral 301 denotes a master processor which controls a slave processor which performs image processing operations, and which performs data transfer and command communication with the control computer 110 and the peripheral device 111 shown in FIG. Is a local memory of the master processor 301 that stores the signal data of the image processing and the data after the image processing operation.

Reference numeral 302 denotes a command line, 311 denotes a first slave processor which performs image processing operation capable of controlling a first low power consumption mode, and 312 denotes a first slave processor which can be accessed by the master processor 301 and the first slave processor. 321 is a second slave processor that performs an image processing operation capable of controlling the second low power consumption mode.
Reference numeral 2 denotes a second memory accessible by the master processor 301 and the second slave processor.

Reference numeral 331 denotes a third slave processor for performing image processing operation capable of controlling the third low power consumption mode, 332 denotes a third memory accessible by the master processor 301 and the third slave processor, and 341 denotes a third memory. A fourth low power consumption mode controllable image processing operation controllable fourth slave processor, 342 is a master processor 3
01 and the fourth accessible by the fourth slave processor.
Memory.

As a method of using a parallel processor, for example, in a semiconductor inspection apparatus, a semiconductor manufacturing apparatus, an electron microscope, an electron beam drawing apparatus, etc., a signal obtained by deflecting and scanning an electron beam is divided into a set of rasters. Performing parallel image processing is one example.

As an example, in a medical examination apparatus, a medical diagnostic apparatus, and the like, parallel image processing of digital filtering of an acquired signal and FFT operation is performed.

In this example, the A / D will be described with reference to FIGS.
The signal data corresponding to the n-th frame after the conversion is stored in the local memory 300 of the master processor 301, which is divided into four parts and the slave processors 311 and 32
A control method in which high-speed image processing calculations are performed in 1, 331, and 341 and stored in the local memory 300 of the master processor 301 again will be described as an example.

FIG. 3 shows the slave processors 311, 32
FIG. 4 shows a case where the computation amount of 1, 331 and 341 is relatively small, that is, a case where the data transmission / reception time from the master processor 301 to the slave processor 311 and the like and the computation time of the slave processor 311 and the like are relatively close. This is a case where the operation amount of the slave processor 311 or the like is relatively large, that is, the operation time of the slave processor 311 or the like is relatively longer than the data transmission / reception time from the master processor 301 to the slave processor 311 or the like. Hereinafter, these will be described in order.

In FIG. 3, 1 to 21 are numerical values indicating the order of control, and the control procedure will be described in detail according to the numerical values. In the (n-1) th frame, the four slave processors 311, 321, 331, and 341 are controlled to the low power consumption mode, and the master processor 311
Description will be made assuming that only 01 is operating.

Procedure 1: The master processor 301 transmits desired data from the memory 300 of the master processor 301 to the first memory 312 of the first slave processor 311.

Step 2: The master processor 301 passes the access right of the first memory 312 to the first slave processor 311 via the command line 302, cancels the low power consumption mode, and activates a desired image processing operation.

Step 3: First slave processor 311
Performs an image processing operation using the first memory 312.

Step 4: The master processor 301 transmits desired data from the memory 300 of the master processor 301 to the second memory 322 of the second slave processor 321.

Step 5: The master processor 301 passes the access right of the second memory 322 to the second slave processor 321 via the command line 302, and releases the low power consumption mode and starts a desired image processing operation.

Step 6: second slave processor 321
Performs an image processing operation using the second memory 322.

Step 7: The master processor 301 sends the first slave processor 3 via the command line 302
After detecting the completion of the calculation of No. 11, the access right of the first memory 312 is returned to the master processor 301, and the first slave processor 311 is controlled to the low power consumption mode. Thereby, the first slave processor 311 is in the low power consumption mode until the next start is commanded.

Step 8: The master processor 301 transmits desired data from the memory 300 of the master processor 301 to the third memory 332 of the third slave processor 331.

Step 9: The master processor 301 passes the access right of the third memory 331 to the third slave processor 331 via the command line 302, cancels the low power consumption mode, and activates a desired image processing operation.

Step 10: third slave processor 33
1 performs an image processing operation using the third memory 332.

Step 11: The master processor 301 detects the end of the operation of the second slave processor 321 via the command line 302, returns the access right of the second memory 322 to the master processor 301, and returns the access right to the second slave processor 321. To the low power consumption mode.
As a result, the second slave processor 321 is in the low power consumption mode until the next start is commanded.

Step 12: The master processor 301
From the memory 300 of the master processor 301 to the fourth
The desired data is transmitted to the fourth memory 342 of the slave processor 341.

Step 13: The master processor 301 passes the access right of the fourth memory 342 to the fourth slave processor 341 via the command line 302, and releases the low power consumption mode and starts a desired image processing operation.

Step 14: fourth slave processor 34
1 performs an image processing operation using the fourth memory 342.

Step 15: The master processor 302 detects the completion of the operation of the third slave processor 331 via the command line 302, returns the access right of the third memory 332 to the master processor 302, and returns the third slave processor 331 To the low power consumption mode.
As a result, the third slave processor 332 enters the low power consumption mode until the next start is commanded.

Step 16: The master processor 301
First memory 312 of first slave processor 311
From the memory 300 of the master processor 301 to the first
Received by the slave processor 311.

Step 17: The master processor 301 detects the end of the operation of the fourth slave processor 341 via the command line 302, returns the access right of the fourth memory 342 to the master processor 301, and returns the fourth slave processor 342 To the low power consumption mode.
As a result, the fourth slave processor 341 is in the low power consumption mode until the next start is commanded.

Step 18: The master processor 301 receives the operation result data from the second slave processor 321 from the second memory 322 of the second slave processor 321 to the memory 300 of the master processor 301.

Step 19: The master processor 301 receives the operation result data from the third slave processor 331 from the third memory 332 of the third slave processor 331 to the memory 300 of the master processor 301.

Step 20: The master processor 301 receives the operation result data by the fourth slave processor 341 from the fourth memory 342 of the fourth slave processor 341 to the memory 300 of the master processor 301.

Step 21: This is the starting point of repetition of steps 1 to 20 in the next frame. In addition, between the n-th frame and the (n + 1) -th frame, the slave processor 3
11, 321, 331, and 341 are in the low power consumption mode.

According to the control of the arithmetic operation as described above, when each of the slave processors 311, 321, 331, and 341 is not performing an arithmetic operation, the slave processors 311 and the like are separately controlled to the low power consumption mode as described above. However, if the time during which the slave processors perform arithmetic operations redundantly is reduced, the absolute heat generation can be reduced.

Next, referring to FIG.
Is a numerical value indicating the order of control, and the control procedure will be described in detail according to this numerical value. Although step 20 is omitted in the drawing due to space limitations, its contents are described in step 2 in FIG.
Equal to zero. Also, as in FIG. 3, the four slave processors 311, 321, and 33 in the (n-1) th frame.
1 and 341 are controlled to the low power consumption mode and only the master processor 301 is operating.

Procedure 1: The master processor 301 transmits desired data from the memory 300 of the master processor 301 to the first memory 312 of the first slave processor 311.

Procedure 2: The master processor 301 passes the access right of the first memory 312 to the first slave processor 311 via the command line 302 to release the low power consumption mode and start a desired image processing operation.

Step 3: First slave processor 311
Performs an image processing operation using the first memory 312.

Step 4: The master processor 301 transmits desired data from the memory 300 of the master processor 301 to the second memory 322 of the second slave processor 321.

Step 5: The master processor 301 passes the access right of the second memory 322 to the second slave processor 321 via the command line 302, and releases the low power consumption mode and starts a desired image processing operation.

Step 6: second slave processor 321
Performs an image processing operation using the second memory 322.

Step 7: The master processor 301 transmits desired data from the memory 300 of the master processor 301 to the third memory 332 of the third slave processor 331.

Step 8: The master processor 301 passes the access right of the third memory 332 to the third slave processor 332 via the command line 302, and releases the low power consumption mode and activates a desired image processing operation.

Step 9: Third slave processor 331
Performs an image processing operation using the third memory 332.

Step 10: The master processor 301
From the memory 300 of the master processor 301 to the fourth
The desired data is transmitted to the fourth memory 342 of the slave processor 341.

Step 11: The master processor 301 passes the access right of the fourth memory 342 to the fourth slave processor 341 via the command line 302, cancels the low power consumption mode, and activates a desired image processing operation.

Step 12: fourth slave processor 34
1 performs an image processing operation using the fourth memory 342.

Step 13: The master processor 301 detects the completion of the operation of the first slave processor 311 via the command line 302, returns the access right of the first memory 312 to the master processor 301, and returns the first slave processor 311 To the low power consumption mode.
Thus, the first slave processor 311 is in the low power consumption mode until the next start is commanded.

Step 14: The master processor 301 receives the operation result data by the first slave processor 311 from the first memory 312 of the first slave processor 311 to the memory 300 of the master processor 301.

Step 15: The master processor 301 detects the end of the operation of the second slave processor 321 via the command line 302, returns the access right of the second memory 322 to the master processor 301, and returns the access right to the second slave processor 321. To the low power consumption mode.
As a result, the second slave processor 321 enters the low power consumption mode until the next start is commanded.

Step 16: The master processor 301 receives the operation result data from the second slave processor 321 from the second memory 322 of the second slave processor 321 to the memory 300 of the master processor 301.

Step 17: The master processor 301 detects the end of the operation of the third slave processor 331 via the command line 302, returns the access right of the third memory 332 to the master processor 301, and returns the third slave processor 331 To the low power consumption mode.
As a result, the third slave processor 331 is in the low power consumption mode until the next start is commanded.

Step 18: The master processor 301 receives the operation result data by the third slave processor 331 from the third memory 332 of the third slave processor 331 to the memory 300 of the master processor 301.

Step 19: The master processor detects the completion of the operation of the slave processor 4 via the command line, returns the access right of the memory 4 to the master processor, and controls the slave processor 4 to the low power consumption mode. As a result, the slave processor 4 enters the low power consumption mode until the next activation.

Step 20: The master processor 301 receives the operation result data by the fourth slave processor 341 from the fourth memory 342 of the fourth slave processor 342 to the memory 300 of the master processor 301.

Step 21: This is the starting point of repetition of steps 1 to 20 in the next frame. Note that the slave processor is in the low power consumption mode between the nth frame and the (n + 1) th frame.

As shown in FIG. 4, the slave processor 31
1, 321, 331 and 341 perform relatively large calculations in real time, and the slave processor 31
When 1 or the like is not calculating, the absolute heat generation can be reduced by controlling to the low power consumption mode as described above.

As shown in FIG. 4, when a relatively large operation is performed in real time, when a plurality of slave processors, in this example, four simultaneously perform high-speed image processing operations, the ambient temperature rises. Time zone.

However, even in this case, since the master processor 301 manages the operation amount of the slave processor 311 and the like, even if the ambient temperature rises, at least the temperature fluctuation range from the rise value can be controlled. .

Next, the control of the temperature fluctuation range from the above-mentioned rise value will be described. FIG. 5 is an operation flowchart of the master processor 301 for the control operation of the temperature fluctuation width.

In step S1 of FIG. 5, the master processor 301 determines whether or not the electron microscope apparatus is operating, and if it is, proceeds to step S2. And
In step S2, the master processor 301
It is determined whether or not the operation of the electron microscope apparatus is performing a temperature-sensitive measurement. If the measurement is not sensitive to temperature, the process returns to step S1. If the measurement is sensitive to temperature, the process proceeds to step S3.

In step S3, it is determined whether or not the temperatures of the slave processors 311, 321, 331, and 341 are equal to or lower than an allowable temperature upper limit. In this step S3,
If the slave processor 311 or the like has exceeded the allowable temperature, the process proceeds to step S4, in which the operation of the slave processor 311 or the like is stopped, and the process returns to step S3.

If it is determined in step S3 that the slave processor 311 or the like is at or below the allowable temperature upper limit, the flow proceeds to step S3.
Go to 5. Then, in this step S5, it is determined whether or not the current temperature is lower than a temperature obtained by subtracting a predetermined temperature, for example, 1 ° C. from the initial temperature (the temperature of the slave processor 311 or the like initially determined or detected in step S3). I do.

If it is determined in step S5 that the current temperature is less than the initial temperature minus the predetermined temperature, the process proceeds to step S6.
Then, the amount of calculation of the plurality of slave processors 311 and the like is increased, or the overlap of the calculation time of the slave processors 311 and the like is increased, and the process returns to step S1.

If it is determined in step S5 that the current temperature is not less than the initial temperature minus a predetermined temperature, the process proceeds to step S7.
The current temperature is changed from the initial temperature to a predetermined temperature, for example, 1 ° C.
It is determined whether or not the temperature exceeds the plus temperature. If the current temperature does not exceed the temperature obtained by adding the initial temperature by a predetermined temperature, the process proceeds to step S8, and the current calculation state is maintained. Subsequently, the process returns to step S1.

If it is determined in step S7 that the current temperature exceeds the initial temperature plus a predetermined temperature, the process proceeds to step S9, in which the amount of calculation is reduced, or the calculation time of each of the slave processors 311 and the like is reduced. The duplication is reduced, and the process returns to step S1.

By operating as described above, it is possible to control the temperature fluctuation range from the rising value to a constant value.

The above-mentioned initial temperature and current temperature may be detected by providing a temperature detecting hardware such as a thermistor in a package such as the slave processor 311 or in a peripheral portion thereof, or may generate heat corresponding to the calculation amount. The amount may be detected in advance, and based on the data, the temperature for the operation amount at that time may be calculated.

If necessary, the temperature information is fed back via the control computer 110 to the precision machine section of industrial equipment requiring absolute temperature management or industrial equipment requiring temperature fluctuation range management. It is possible to control the temperature of the mechanical part.

As described above, the applications of these devices are called real-time properties such as inspection and diagnosis.
Since high-speed processing is required, a plurality of high-speed processors generating a large amount of heat are used in parallel.

On the other hand, as described above, these devices
For example, when data is transferred between the control computer and a peripheral device or when the control computer is interfaced with a user, there is a considerable amount of time during which image processing calculations and signal processing calculations are unnecessary.

As described above, by adopting the configuration of the present invention, a high-speed processor is operated only when necessary and a desired image processing operation is performed according to a command from the control computer. Can be controlled to the low power consumption mode, so that the total amount of heat generation can be greatly reduced, and furthermore, the fluctuation range in the temperature rise can be controlled.

Thus, the data processing apparatus according to the present invention can be used for a semiconductor inspection apparatus, a semiconductor manufacturing apparatus, an electron microscope, an electron beam drawing apparatus, etc. used in a clean room where temperature is strictly controlled. It can be applied to a medical examination device, a medical diagnostic device, and the like used in the above.

The architecture of the parallel processor is not particularly limited to the configuration of the present invention.
For example, literature (parallel computer, Shokodo, 1996)
Naturally, the present invention can be applied to the architectures described in many publications, and the bus right control, which is one of the hardest controls in the hardware configuration of the parallel processor, is described in, for example, the document (Transistor Technology, CQ
Publisher, March 1994),
Bus right release control, bus switch, multiple port memory, F
There is a method using an IFO (First In First Out) memory or the like, and the present invention is applicable to these methods.

Further, regarding the mounting, it is not necessary that the above-mentioned components are mounted on a single substrate, and a plurality of components may be used.

Further, in the above-described embodiment, the example in which the number of the high-speed processors is four has been described. However, the present invention is not limited to the number of the processors but may be applied to the case where the number is one.

The transition between the low power consumption mode and the normal operation mode of the slave processor is not limited to a command from the master processor, but may be a command of the slave processor itself, a command from a control computer, or It may be a command between slave processors.

Further, the master processor itself may be a processor capable of controlling the low power consumption mode. Further, although a processor capable of controlling the low power consumption mode is used, the effect of the present invention cannot be directly obtained even if the usage method does not employ the low power consumption mode, but the effect of the present invention will be obtained in the future. And the functions of the image processing apparatus can be sufficiently achieved.

Further, an application example of the data processing apparatus according to the present invention is applied to a room controlled by air conditioning such as a semiconductor inspection apparatus, a semiconductor manufacturing apparatus, an electron microscope, and an electron beam drawing apparatus used in a clean room where temperature is strictly controlled. The present invention is applicable to medical examination devices, medical diagnostic devices, and the like, which are not particularly limited thereto, and can be applied to devices expected to have the effects of the present invention. It is.

[0105]

Since the present invention is configured as described above, it has the following effects. A processor capable of controlling a low power consumption mode, generally called a sleep mode or a standby mode, is used to operate a high-speed processor only when necessary and to control the operation amount of the high-speed processor. It is possible to realize a data processing device capable of reducing the temperature drop and the temperature fluctuation width.

[Brief description of the drawings]

FIG. 1 is a schematic overall configuration diagram when a data processing device according to an embodiment of the present invention is applied to an electron microscope.

FIG. 2 is a block diagram of the image processing apparatus in the example of FIG.

FIG. 3 is a control sequence diagram when the amount of calculation of the image processing apparatus in the example of FIG. 1 is small.

FIG. 4 is a control sequence diagram when the amount of calculation of the image processing apparatus in the example of FIG. 1 is large.

FIG. 5 is an operation flowchart of a master processor regarding a control operation of a temperature fluctuation width in the example of FIG. 1;

FIG. 6 is a diagram illustrating a relationship between power consumption of a parallel processor and an increase in ambient temperature.

[Explanation of symbols]

Reference Signs List 101 mirror section of electron microscope 102 electron gun 103 electron beam 104 deflector 105 sample 106 electron detector 107 amplifier 108 control signal 109 image processing device 110 control computer 111 peripheral device such as display and storage 300 local memory of master processor 301 Master processor 302 command line 311 first low power consumption mode control slave processor 312 first memory 321 second low power consumption mode control slave processor 322 second memory 331 third low power consumption mode control slave processor 332 3rd memory 341 4th low power consumption mode control slave processor 342 4th memory

 ──────────────────────────────────────────────────続 き Continued on front page (72) Inventor Keisuke Morita 882 Ma, Hitachinaka-shi, Ibaraki Pref.Measurement Division, Hitachi, Ltd. Measuring Instruments Division

Claims (4)

[Claims] 1. A data processing apparatus having a parallel processor in which a plurality of processors generate heat by calculation and having an increased processing capacity is used, wherein at least one of the plurality of processors operates in a sleep mode or a standby mode. A data processing device comprising a processor capable of low power consumption mode control. 2. The data processing device according to claim 1, wherein
A data processing apparatus wherein a processor capable of controlling the low power consumption mode is controlled to a low power consumption mode during a period in which data processing operation is unnecessary. 3. The data processing apparatus according to claim 1, wherein only the processor that needs to operate among the plurality of processors is operated, and the other processor is set to a low power consumption mode, and the plurality of processors overlap. A data processing device for controlling the operation so as to reduce the time required to execute the calculation. 4. The data processing device according to claim 3, wherein
It is determined whether the temperature of the data processing device exceeds a temperature obtained by adding the predetermined temperature and whether the temperature of the data processing device exceeds a temperature obtained by adding the predetermined temperature. In this method, the time for a plurality of processors to execute an operation in an overlapping manner is suppressed, and when the temperature of the data processing device is lower than a temperature obtained by subtracting the predetermined temperature, the plurality of processors execute an operation in an overlapping manner. A data processing device characterized by increasing time.