JPH11266145A - Tuner circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tuner circuit which suppresses the differences in power gain by the frequency of a selected channel and is able to obtain optimal power gain for each band. SOLUTION: This tuner circuit includes variable capacity parts 20 and 21, which change in the capacity in response to a frequency of a selected channel. The variable capacity part 20 includes plural capacitors C4 and C13 and a switch D9. The variable capacity part 21 includes plural capacitors C5 and C15 and a switch D10. The switches 9 and 10 enter conductive state by receiving a bias voltage BH for a high band. Thus, when a channel of high frequency is selected, the condenser C13 is connected to the condenser C4 in parallel, and the condenser 15 is connected to the condenser C5 in parallel.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuner circuit for receiving a high-frequency signal, and more particularly to a tuner circuit capable of adjusting a power gain according to a frequency of a selected channel.

[0002]

2. Description of the Related Art A conventional tuner circuit 900.1 will be described with reference to FIG.

FIG. 6 is a diagram showing a configuration of a main part of a conventional tuner circuit 900.1. Referring to FIG. 6, a conventional tuner circuit 900.1 includes an input filter 2, an input tuning circuit 3, a high-frequency amplifier circuit 5, an interstage tuning circuit 6, and coupling sections 4 and 7. The tuner circuit 900.1 selects a signal of a desired channel from high-frequency signals (VHF) received by the antenna 1. The selected signal is converted to an intermediate frequency via a mixer (not shown).

[0004] The input filter 2 is composed of a high-pass filter. The input filter 2 removes interference waves and noise components of the signal received by the antenna 1.

[0005] The input tuning circuit 3 comprises a band-pass filter. The input tuning circuit 3 tunes the signal of the selected channel among the signals output from the input filter 2 to the frequency of the selected channel in response to the high-band bias voltage BH and the tuning voltage VT.

The high-frequency amplifier circuit 5 amplifies and outputs a signal output from the input tuning circuit 3 in response to an AGC voltage VAGC output from an AGC circuit (automatic gain control circuit) not shown.

[0007] The coupling section 4 includes a capacitor C4. The capacitor C4 couples the input tuning circuit 3 and the high frequency amplifier circuit 5.

The inter-stage tuning circuit 6 responds to the tuning voltage VT and the high-band bias voltage BH or the low-band bias voltage BL to further select the signal output from the high-frequency amplifier circuit 5 at the frequency of the selected channel. Synchronize with.

The signal output from the inter-stage tuning circuit 6 is converted to an intermediate frequency signal via a mixer (not shown).

The coupling section 7 includes a capacitor C5. Capacitor C5 couples interstage tuning circuit 6 and a mixer (not shown).

Another example of the configuration of a conventional tuner circuit (hereinafter referred to as a tuner circuit 900.2) will be described with reference to FIG. FIG. 7 is a diagram showing a configuration of a conventional tuner circuit 900.2.

The conventional tuner circuit 900.2 shown in FIG.
Is replaced with a capacitor C4 shown in FIG.
Includes diode D4, capacitor C10 and resistor R3. The coupling unit 7 of the conventional tuner circuit 900.2 shown in FIG. 7 includes a diode D5, a capacitor C11, and a resistor R9 instead of the capacitor C5 shown in FIG.

More specifically, in the coupling section 4 shown in FIG. 7, the diode D4 and the capacitor C10 are connected to the input tuning circuit 3
And the high-frequency amplifier circuit 5 are connected in series. In the coupling section 7 shown in FIG. 7, the diode D5 and the capacitor C
11 is connected in series between the interstage tuning circuit 6 and a mixer (not shown).

The diodes D4 and D5 are variable capacitance diodes and function as capacitive elements. Capacitors C10 and C11 are capacitors for cutting an AC component.

The coupling section 4 shown in FIG. 7 further includes a resistor R3. The coupling section 7 shown in FIG. 7 further includes a resistor R9.
The resistor R3 has one terminal connected to a connection node between the diode D4 and the capacitor C10, and the other terminal connected to a ground potential. The resistor R9 has one terminal connected to a connection node between the diode D5 and the capacitor C11, and the other terminal connected to a ground potential. Resistors R3 and R9
Are discharge resistances, respectively.

[0016]

Since the conventional tuner circuits 900.1 and 900.2 are constructed as described above, there are cases where a high band signal is selected and a case where a low band signal is selected. In this case, the power gain was greatly different due to the difference between the frequencies and the Q value (degree of resonance) of the internal circuit for each. Then, there is a problem that the difference in power gain greatly affects the evaluation on the mounting screen of the television set.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a power gain difference depending on the frequency of a selected channel without complicating the system. It is to provide a tuner circuit capable of suppressing the noise.

It is another object of the present invention to provide a tuner circuit capable of obtaining a maximum power gain for each selected frequency band.

[0019]

A tuner circuit according to a first aspect of the present invention is a tuner circuit for converting a signal of a selected channel among received high-frequency signals into an intermediate frequency, and wherein the tuner circuit selects the selected signal among received signals. Tuning means for tuning the signal of the selected channel to the frequency of the selected channel, amplifying means for amplifying the output of the tuning means, provided between the tuning means and the amplifying means, in response to the frequency of the selected channel. Variable capacity means for changing the capacity.

Therefore, the coupling capacitance between the tuning means and the amplifying means can be changed according to the frequency of the selected channel. This makes it possible to suppress the difference in power gain depending on the frequency of the selected channel.

A tuner circuit according to a second aspect is a tuner circuit according to the first aspect.
In the tuner circuit according to the variable variable capacitance means, a plurality of capacitive elements provided between the tuning means and the amplification means, in response to the frequency of the selected channel, each of the plurality of capacitive elements Control means for changing the connection relationship.

Therefore, the coupling relationship between the plurality of capacitive elements between the tuning means and the amplifying means can be changed according to the frequency of the selected channel. Thereby, the capacitance between the tuning means and the amplifying means can be effectively changed.

A tuner circuit according to a third aspect is a tuner circuit according to the second aspect.
Wherein the plurality of capacitive elements include a first capacitive element connected between a tuning unit and the amplifying unit, and a second capacitive element, and the control unit includes: In response to the frequency of the selected channel, a switch means for connecting / disconnecting the second capacitive element to / from the first capacitive element, wherein the switch means adjusts the frequency of the selected channel to the first capacitive element. If the frequency is higher than the level, the second capacitive element is connected in parallel with the first capacitive element. If the frequency of the selected channel is lower than the first level, the second capacitive element is connected to the second capacitive element. Disconnect with one capacitive element.

Therefore, when the frequency of the selected channel is high, a capacitive element can be connected in parallel between the tuning means and the amplifying means. Thereby, when the frequency of the selected channel is high, a high power gain can be obtained.

A tuner circuit according to a fourth aspect of the present invention is a tuner circuit for converting a signal of a selected channel among received high-frequency signals to an intermediate frequency, wherein the tuner circuit converts the signal of the selected channel among the received signals to Tuning means for tuning to the frequency of the selected channel; amplifying means for amplifying the output of the tuning means; converting means for converting the output of the amplifying means to an intermediate frequency; and selecting means provided between the amplifying means and the converting means. Variable capacitance means whose capacitance varies in response to the frequency of the selected channel.

Therefore, the coupling capacitance between the amplifying means and the converting means can be changed according to the frequency of the selected channel. This makes it possible to suppress a difference in power gain depending on the frequency of the selected channel.

The tuner circuit according to claim 5 is a tuner circuit according to claim 4.
In the tuner circuit according to the variable variable capacitance means, a plurality of capacitive elements provided between the amplification means and the conversion means, in response to the frequency of the selected channel, each of the plurality of capacitive elements Control means for changing the connection relationship.

Therefore, the coupling relationship of the plurality of capacitive elements between the amplifying means and the converting means can be changed according to the frequency of the selected channel. Thus, the capacitance between the amplifying unit and the converting unit can be effectively changed.

A tuner circuit according to claim 6 is a tuner circuit according to claim 5.
Wherein the plurality of capacitive elements include a first capacitive element connected between the amplifying means and the converting means, and a second capacitive element; Switch means for connecting / disconnecting the second capacitive element to / from the first capacitive element in response to the frequency of the selected channel, wherein the switch means adjusts the frequency of the selected channel to the first level. If higher, the second capacitive element is connected in parallel with the first capacitive element, and if the frequency of the selected channel is lower than the first level, the second capacitive element is connected to the first capacitive element. In a non-connected state with the capacitive element.

Therefore, when the frequency of the selected channel is high, a capacitive element can be connected in parallel between the amplifying means and the converting means. Thereby, when the frequency of the selected channel is high, a high power gain can be obtained.

A tuner circuit according to claim 7 is a tuner circuit for converting a signal of a selected channel among received high-frequency signals into an intermediate frequency, and selecting a signal of a selected channel among received signals. Tuning means for tuning to the frequency of the adjusted channel, amplification means for amplifying the output of the tuning means, provided between the tuning means and the amplification means,
A first variable capacitance means for varying the capacity in response to the frequency of the selected channel; a conversion means for converting the output of the amplification means to an intermediate frequency; and a switching means provided between the amplification means and the conversion means. And a second variable capacitance means whose capacitance varies in response to the frequency of

Therefore, the respective coupling capacitances between the tuning means and the amplifying means and between the amplifying means and the converting means can be changed according to the frequency of the selected channel. This makes it possible to suppress the difference in power gain depending on the frequency of the selected channel.

The tuner circuit according to claim 8 is the tuner circuit according to claim 7.
Wherein the first variable capacitance means comprises:
A first plurality of capacitive elements provided between the tuning unit and the amplifying unit, and a first plurality of capacitive elements that change a connection relationship of the first plurality of capacitive elements in response to a frequency of the selected channel. Control means, wherein the second variable capacitance means includes a second plurality of capacitive elements provided between the amplification means and the conversion means, and a second variable capacitance means responsive to a frequency of the selected channel.
And a second control means for changing a connection relation of each of the plurality of capacitive elements.

Therefore, the coupling relationship between a plurality of capacitive elements can be changed according to the frequency of the selected channel. Thereby, the respective capacitances between the tuning means and the amplification means and between the amplification means and the conversion means can be effectively changed.

The tuner circuit according to claim 9 is the tuner circuit according to claim 8
Wherein the first plurality of capacitive elements includes a first capacitive element connected between the tuning means and the amplifying means, and a second capacitive element; Control means includes first switch means for connecting / disconnecting the second capacitive element to / from the first capacitive element in response to the frequency of the selected channel, and comprising the second plurality of capacitors. The sex element is
A third capacitive element connected between the amplifying means and the converting means, and a fourth capacitive element, wherein the second control means
A second switch for connecting / disconnecting the fourth capacitive element to / from the third capacitive element in response to a frequency of the selected channel; If the frequency is higher than the first level, the second capacitive element is connected in parallel with the first capacitive element, and if the frequency of the selected channel is lower than the first level, the second capacitive element is connected. The second switch means disconnects the fourth capacitive element from the third capacitive element when the frequency of the selected channel is higher than the second level. When the frequency of the selected channel is lower than the second level, the fourth capacitive element is disconnected from the third capacitive element.

Therefore, when the frequency of the selected channel is high, capacitive elements can be connected in parallel between the tuning means and the amplifying means and between the amplifying means and the converting means. Thereby, when the frequency of the selected channel is high, a high power gain can be obtained.

[0037]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] A tuner circuit according to a first embodiment of the present invention suppresses a power gain difference between bands irrespective of a frequency of a channel to be selected, and furthermore, has a maximum gain in each band. It is possible to obtain a power gain.

The overall configuration of the tuner circuit according to the first embodiment of the present invention will be briefly described with reference to FIG.

FIG. 1 is a schematic block diagram showing an example of the configuration of tuner circuit 100 according to the first embodiment of the present invention. The tuner circuit 100 shown in FIG. 1 includes an input filter 12, an input tuning circuit 13, a high-frequency amplifier circuit 15, an inter-stage tuning circuit 16, and variable capacitance units 20 and 21.

The variable capacitors 20 and 21 according to the first embodiment of the present invention change the size of the capacitors according to the desired channel frequency. Thereby, the power gain of tuner circuit 100 is adjusted according to each of the high band and the low band.

A specific configuration of a main part of the tuner circuit 100 shown in FIG. 1 will be described with reference to FIG. FIG. 2 is a circuit diagram showing an example of a specific configuration of a main part of the tuner circuit 100 shown in FIG.

The input filter 12 is composed of a high-pass filter. The input filter 12 removes an interference wave and a noise component of the signal received by the antenna 1.

The configuration of the input tuning circuit 13 will be described. The input tuning circuit 13 includes resistors R1 and R2, coils L1 and L6, capacitors C1, C16, and C1.
7 and diodes D1 and D6. The input tuning circuit 13 is connected to the input filter 12 at a node N0 and to a variable capacitance unit 20 described later at a node N1.

One terminal of the capacitor C1 is connected to the node N
Connected to 0. Coil L1, coil L6 and capacitor C17 are connected in series between node N0 and the ground potential. Connection node N4 between coil L1 and coil L6
And a ground potential, a diode D6 and a capacitor C16 are connected in series. A connection node between the diode D6 and the capacitor C16 receives the high-band bias voltage BH. A resistor R is connected between the node N4 and the ground potential.
2 are connected.

The other terminal of the capacitor C1 is connected to the node N
1 is connected. Diode D1 is connected between node N1 and the ground potential. Node N1 receives tuning voltage VT via resistor R1.

The coil L1, the capacitor C1, and the diode D1 constitute a high-band input tuning circuit.
The coils L1 and L6, the capacitor C1, and the diode D1 form a low-band input tuning circuit.

The diode D1 is a variable capacitance diode, and changes the capacitance according to the tuning voltage VT. Resistance R
1 is a bias resistor for the tuning voltage VT. Resistance R2
Is a high-band switching bias resistor.
The capacitors C16 and C17 are ground capacitors.

The operation of the input tuning circuit 13 will be described. The diode D6 is a switch for switching between the high band channel and the low band channel (changing the resonance frequency).

The high-band bias voltage BH and the low-band bias voltage BL are complementary to each other. Specifically, when a high-band signal is selected, the high-band bias voltage BH goes high and the low-band bias voltage BL goes low. When a low-band signal is selected, the high-band bias voltage BH goes low and the low-band bias voltage BL goes high.

When the high-band bias voltage BH is applied (high-band selection), the diode D6 is turned on. Therefore, the signal passing through the input filter 12 resonates in the coil L1, the capacitor C1, and the diode D1.

On the other hand, when the low-band bias voltage BL is applied (low-band selection), the diode D6
Is in a non-conductive state. Therefore, the signal that has passed through the input filter 12 includes the coils L1 and L6 and the capacitor C
Resonate at 1 and D1.

The configuration of the high-frequency amplifier circuit 15 will be described. The high frequency amplifier circuit 15 includes a field effect transistor Q
1, including resistors R4 and R5 and a capacitor C9. Transistor Q1 is a dual gate MOSFET
It is. The resistor R4 is a bias resistor for AGC,
The resistor R5 is a resistor for preventing parasitic oscillation of the FET. The capacitor C9 is a ground capacitor.

The first gate electrode of the transistor Q1 is
It is connected to an output node of the variable capacitance unit 20 described later. The second gate electrode receives an AGC voltage VAGC from an AGC circuit (not shown) via a resistor R4. A capacitor C9 is connected between the second gate electrode and the ground potential. The source of transistor Q1 is connected to the ground potential, and the drain is connected to one terminal of resistor R5.

The high-frequency amplifier circuit 15 includes the input tuning circuit 13
Is amplified and output in response to the AGC voltage VAGC.

The configuration of the interstage tuning circuit 16 will be described. The interstage tuning circuit 16 includes coils L2, L3, L7, L
8 and L9, capacitors C2, C3, C7, C8 and C19, and diodes D2, D3, D7 and D8. The interstage tuning circuit 16 is connected at a node N2 to the high-frequency amplifier circuit 15 (the other terminal of the resistor R5), and is connected at a node N3 to a variable capacitance section 21 described later.

A capacitor C2 and a diode D2 are connected in series between the node N2 and the ground potential. The connection node between the capacitor C2 and the diode D2 is a resistor R
6 receives the tuning voltage VT. Furthermore, coils L2 and L7 are connected in series to node N2. A diode D7 and a capacitor C7 are connected in series to a connection node between the coils L2 and L7. A connection node between the diode D7 and the capacitor C7 receives a high-band bias voltage BH. The other terminal of the capacitor C7 is
Connected to ground potential.

A diode D3 is connected between the node N3 and the ground potential. Node N3 receives tuning voltage VT via resistor R7. Further, a coil L3, a capacitor C3, and a coil L8 are connected in series to the node N3. At the connection node between the capacitor C3 and the coil L8,
Diode D8 and capacitor C8 are connected in series. A connection node between the diode D8 and the capacitor C8 receives the high-band bias voltage BH. The other terminal of capacitor C8 is connected to the ground potential.

A coil L9 and a capacitor C18 are connected in series between one terminal of each of the coils L7 and L8 and the ground potential. Coil L9 and capacitor C
18 is connected to a low-band bias voltage B
Receive L.

The coil L2, the capacitor C2 and the diode D2 constitute a high-band primary interstage tuning circuit. The coils L2 and L7, the capacitor C2, and the diode D2 form a low-band interstage primary tuning circuit.

Further, the coil L3, the capacitor C3, and the diode D3 form a high-band interstage secondary tuning circuit. The coils L3 and L8, the capacitor C3, and the diode D3 form a low-band interstage secondary tuning circuit.

Capacitor C19 is a coupling capacitor for coupling the interstage primary tuning circuit and the interstage secondary tuning circuit. One terminal is connected to node N2, and the other terminal is connected to node N3. Is done.

The diodes D2 and D3 are variable capacitance diodes, and change the capacitance according to the tuning voltage VT. The resistors R6 and R7 are bias resistors for the tuning voltage VT. The capacitors C7, C8 and C18 are ground capacitors.

The operation of the inter-stage tuning circuit 16 will be described. Diodes D7 and D8 are switches for switching between a high-band channel and a low-band channel (changing the resonance frequency). The diodes D7 and D8 are turned on when the high-band bias voltage BH is applied.

When the high-band bias voltage BH is applied (high-band selection), the diodes D7 and D8 are turned on. Therefore, transistor Q
1 passes through a high-band interstage primary tuning circuit (coil L2, capacitor C2 and diode D2)
, And furthermore, a secondary tuning circuit (coil L
3. Resonate at the capacitor C3 and the diode D3).

When low-band bias voltage BL is applied (low-band selection), diodes D7 and D8 are off. Therefore, the signal passing through the transistor Q1 resonates in the low-band interstage primary tuning circuit (coils L2, L7 and L9, capacitor C2 and diode D2), and further interstage secondary tuning circuits (coils L3 and L8). And L9, capacitor C
3 and the diode D3).

Next, an example of a specific configuration of the variable capacitance units 20 and 21 according to the first embodiment of the present invention shown in FIGS. 1 and 2 will be described with reference to FIG.

FIG. 3 shows the variable capacitance section 20 shown in FIGS.
And FIG. 21 is a circuit diagram showing an example of a specific configuration of FIG.

The variable capacitance section 20 shown in FIG. 3 will be described. The variable capacitance section 20 includes capacitors C4, C12 and C13, resistors R10 and R11, and a diode D9.

One terminal of the capacitor C4 is connected to the node N
1 and the other terminal is connected to the first terminal of the transistor Q1.
Is connected to the gate electrode. A capacitor C12 and a resistor R10 are connected in series between the node N1 and the ground potential. One terminal of diode D9 is connected to a connection node between capacitor C12 and resistor R10, and the other terminal is connected to one terminal of capacitor C13.
The other terminal of capacitor C13 is connected to the first gate electrode of transistor Q1. A connection node between the diode D9 and the capacitor C13 receives the high-band bias voltage BH via the resistor R11.

The diode D9 functions as a switch. The capacitor C12 is a capacitor for cutting an AC component, and the resistors R10 and R11 are switching bias resistors for a high band.

The variable capacitance section 21 shown in FIG. 3 will be described. Variable capacitance section 21 includes capacitors C5, C14 and C15, resistors R12 and R13, and diode D10.

One terminal of the capacitor C5 is connected to the node N
3 and the other terminal is connected to a mixer (not shown). A capacitor C14 and a resistor R12 are connected in series between the node N3 and the ground potential. One terminal of the diode D10 is connected to the capacitor C14 and the resistor R1.
2 and the other terminal is connected to one terminal of the capacitor C15. Capacitor C15
Is connected to a mixer (not shown). The connection node between the diode D10 and the capacitor C15 receives the high-band bias voltage BH via the resistor R13.

The diode D10 functions as a switch. The capacitor C14 is a capacitor for cutting an AC component, and the resistors R12 and R13 are switching bias resistors for a high band.

The operation of the variable capacitance units 20 and 21 shown in FIG. 3 will be described. Bias voltage BL for low band
Is applied (low band is selected), the diode D
9 and D10 are both non-conductive. Therefore, similarly to the conventional tuner circuit 900.1, the capacitors C4 and C5 function as coupling capacitors.

On the other hand, when the high-band bias voltage BH is applied (high-band is selected), the diode D9
Becomes conductive. Therefore, the capacitors C4 and C13 are connected in parallel between the input tuning circuit 13 and the high-frequency tuning circuit 15, and the capacitance therebetween is larger than when the low band is selected. Also, the diode D1
0 becomes conductive. Therefore, the capacitors C5 and C15 are connected in parallel between the inter-stage tuning circuit 16 and the mixer (not shown), and the capacitance therebetween becomes larger than when the low band is selected. For this reason, the Q value increases, and the power gain increases compared to when the high band is selected in the conventional tuner circuit 900.1.

Another specific configuration example of variable capacitance sections 20 and 21 in the first embodiment of the present invention shown in FIGS. 1 and 2 will be described with reference to FIG. FIG. 4 shows FIGS.
21 is a circuit diagram showing another example of a specific configuration of the variable capacitance units 20 and 21 shown in FIG.

The variable capacitance section 20 shown in FIG. 4 will be described. The variable capacitance section 20 includes a capacitor C10,
C12 and C13, resistors R3, R10 and R11,
And diodes D4 and D9.

A diode D4 and a capacitor C are connected between the node N1 and the first gate electrode of the transistor Q1.
10 are connected in series. A capacitor C12 and a resistor R10 are connected in series between the node N1 and the ground potential. One terminal of the diode D9 is a capacitor C
12 is connected to a connection node between the resistor R10 and the other terminal, and the other terminal is connected to one terminal of the capacitor C13. The other terminal of capacitor C13 is connected to a connection node between diode D4 and capacitor C10. A connection node between the diode D9 and the capacitor C13 is connected to a resistor R11.
Receives the high-band bias voltage BH via the. The resistor R3 has one terminal connected to the diode D4 and the capacitor C.
10, and the other terminal is connected to the ground potential.

As described above, the diode D4 is a variable capacitance diode and functions as a capacitive element. The diode D9 functions as a switch.

The variable capacitance section 21 shown in FIG. 4 will be described. Variable capacitance section 21 includes capacitors C11, C14 and C15, resistors R9, R12 and R13, and diodes D5 and D10.

Between the node N3 and a mixer (not shown)
Diode D5 and capacitor C11 are connected in series. A capacitor C is connected between the node N3 and the ground potential.
14 and the resistor R12 are connected in series. One terminal of the diode D10 is connected to a capacitor C14 and a resistor R12.
And the other terminal is connected to one terminal of the capacitor C15. The other terminal of the capacitor C15 is connected to a connection node between the diode D5 and the capacitor C11. The connection node between the diode D10 and the capacitor C15 receives the high-band bias voltage BH via the resistor R13. The resistor R9 has one terminal connected to a connection node between the diode D5 and the capacitor C11, and the other terminal connected to a ground potential.

As described above, the diode D5 is a variable capacitance diode and functions as a capacitive element. The diode D10 functions as a switch.

The operation of variable capacitance units 20 and 21 shown in FIG. 4 will be described. Bias voltage BL for low band
Is applied (low band is selected), the diode D
9 and D10 are both non-conductive. Therefore, similarly to the conventional tuner circuit 900.2, the diodes D4 and D5 function as a coupling capacitor.

On the other hand, when the high-band bias voltage BH is applied (high-band is selected), the diode D9
Becomes conductive. Therefore, the diode D4 and the capacitor C13 are connected in parallel between the input tuning circuit 13 and the high-frequency tuning circuit 15, and the capacitance therebetween becomes larger than when the low band is selected. Further, the diode D10 becomes conductive. Therefore, the diode D5 is connected between the inter-stage tuning circuit 16 and a mixer (not shown).
And the capacitor C15 are connected in parallel,
The capacity during this time is larger than when the low band is selected.
For this reason, the Q value increases, and the conventional tuner circuit 90
The power gain is higher than when the high band is selected in 0.2.

The inter-stage tuning circuit 16 shown in FIG. 5 may be used instead of the inter-stage tuning circuit 16 shown in FIG. FIG. 5 is a diagram showing another example of a specific configuration of the interstage tuning circuit 16 shown in FIG.

The inter-stage tuning circuit 16 shown in FIG.
4 and R15. The resistor R14 is a coil L
7 and L9. The resistor R15 is a coil L
8 and L9. Resistors R14 and R1
Is a damping resistor, which plays a role in lowering the power gain when the low band is selected. By using this together with the variable capacitance units 20 and 21 shown in FIG. 2 or FIG. 3, it is possible to suppress the difference in power gain.

As described above, tuner circuit 100 according to Embodiment 1 of the present invention can suppress the difference in power gain regardless of the frequency of the selected channel. Furthermore, by making the coupling capacitance between the circuits variable, it is possible to obtain the maximum power gain for each band.

[Brief description of the drawings]

FIG. 1 is a tuner circuit 1 according to a first embodiment of the present invention.
It is a schematic block diagram which shows an example of a structure of 00.

FIG. 2 is a circuit diagram showing an example of a specific configuration of a main part of the tuner circuit 100 shown in FIG.

FIG. 3 is a circuit diagram showing an example of a specific configuration of variable capacitance units 20 and 21 shown in FIGS.

FIG. 4 is a circuit diagram showing another example of a specific configuration of the variable capacitance units 20 and 21 shown in FIGS. 1 and 2;

FIG. 5 is a diagram showing another example of a specific configuration of the interstage tuning circuit 16 shown in FIG. 1;

FIG. 6 is a diagram showing a configuration of a main part of a conventional tuner circuit 900.1.

FIG. 7 is a diagram showing a configuration of a main part of a conventional tuner circuit 900.2.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Antenna 12 Input filter 13 Input tuning circuit 15 High frequency amplifier 16 Interstage tuning circuit 20, 21 Variable capacitance part L1 to L9 Coil C1 to C18 Capacitor D1 to D10 Diode R1 to R15 Resistance Q1 Field effect transistor 100 Tuner circuit

Claims (9)

[Claims] 1. A tuner circuit for converting a signal of a selected channel among received high-frequency signals to an intermediate frequency, wherein the tuner circuit converts the signal of the selected channel among the received signals to a frequency of the selected channel. A tuning means for tuning the output of the tuning means; a variable capacitance means provided between the tuning means and the amplification means, wherein a capacity varies in response to a frequency of the selected channel. A tuner circuit comprising: 2. The variable capacitance means includes: a plurality of capacitive elements provided between the tuning means and the amplifying means; and each of the plurality of capacitive elements in response to a frequency of the selected channel. 2. The tuner circuit according to claim 1, further comprising control means for changing a connection relationship of the tuner. 3. The plurality of capacitive elements include: a first capacitive element connected between the tuning means and the amplifying means; and a second capacitive element, wherein the control means comprises: Switching means for connecting / disconnecting the second capacitive element to / from the first capacitive element in response to a frequency of the selected channel, wherein the switching means comprises: Is higher than the first level, the second capacitive element is connected in parallel with the first capacitive element, and when the frequency of the selected channel is lower than the first level, 3. The tuner circuit according to claim 2, wherein the second capacitive element is disconnected from the first capacitive element. 4. A tuner circuit for converting a signal of a selected channel among received high-frequency signals to an intermediate frequency, wherein the tuner circuit converts the signal of the selected channel among the received signals to a frequency of the selected channel. Tuning means for tuning to; amplifying means for amplifying an output of the tuning means; a converting means for converting an output of the amplifying means to the intermediate frequency; provided between the amplifying means and the converting means, A variable capacitance means for varying a capacitance in response to a frequency of a selected channel. 5. The variable capacitance means includes: a plurality of capacitive elements provided between the amplifying means and the conversion means; and a plurality of capacitive elements in response to a frequency of the selected channel. 5. The tuner circuit according to claim 4, further comprising control means for changing a connection relationship of the tuner. 6. The plurality of capacitive elements include a first capacitive element connected between the amplifying unit and the converting unit, and a second capacitive element, and the control unit includes: Switching means for connecting / disconnecting the second capacitive element to / from the first capacitive element in response to a frequency of the selected channel, wherein the switching means comprises: Is higher than the first level, the second capacitive element is connected in parallel with the first capacitive element, and when the frequency of the selected channel is lower than the first level, The tuner circuit according to claim 5, wherein said second capacitive element is disconnected from said first capacitive element. 7. A tuner circuit for converting a signal of a selected channel among received high-frequency signals into an intermediate frequency, wherein the tuner circuit converts the signal of the selected channel among the received signals to a frequency of the selected channel. Tuning means for tuning the output of the tuning means; amplifying means for amplifying the output of the tuning means; a first means provided between the tuning means and the amplifying means, and having a variable capacity in response to the frequency of the selected channel.
A variable capacity means, a conversion means for converting an output of the amplification means to the intermediate frequency, and a variable capacity means provided between the amplification means and the conversion means, wherein a capacity is changed in response to a frequency of the selected channel. Second
And a variable capacitance means. 8. The first variable capacitance means comprises: a first plurality of capacitive elements provided between the tuning means and the amplification means; and the first variable capacitance means, in response to a frequency of the selected channel. A first control unit for changing a connection relationship of each of the plurality of capacitive elements, wherein the second variable capacitance unit includes a second plurality provided between the amplification unit and the conversion unit. 9. The tuner circuit according to claim 7, further comprising: a capacitive element, and a second control unit configured to change a connection relation of each of the second plurality of capacitive elements in response to a frequency of the selected channel. . 9. The first plurality of capacitive elements includes: a first capacitive element connected between the tuning means and the amplifying means; and a second capacitive element, The first control means includes first switch means for connecting / disconnecting the second capacitive element to / from the first capacitive element in response to a frequency of the selected channel, The second plurality of capacitive elements includes a third capacitive element connected between the amplifying unit and the converting unit, and a fourth capacitive element, and the second control unit includes: A second switch for connecting / disconnecting the fourth capacitive element to / from the third capacitive element in response to a frequency of the selected channel, wherein the first switch comprises: If the frequency of the selected channel is higher than the first level, the second content A capacitive element connected in parallel with the first capacitive element, and when the frequency of the selected channel is lower than the first level, the second capacitive element is connected to the first capacitive element. When the frequency of the selected channel is higher than a second level, the second switch means connects the fourth capacitive element in parallel with the third capacitive element when the frequency of the selected channel is higher than a second level. 9. The tuner circuit according to claim 8, wherein when the frequency of the selected channel is lower than the second level, the fourth capacitive element is disconnected from the third capacitive element.