JP2000209067A - Tuner circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a tuner circuit capable of reducing interference frequencies by changing a trap frequency in response to the frequency of a selected channel. SOLUTION: This tuner circuit is provided with variable trap parts 20 and 21. The variable trap part 20 is provided with a variable capacitance diode D4, a diode D9 functioning as a switch, a capacitor and a coil L10. The variable trap part 21 is provided with the variable capacitance diode D5, the diode D10 functioning as the switch, the plural capacitors and the coil L11. The diodes D9 and D10 are turned to a conducting state corresponding to a bias voltage BH for a high band. As a result, the diode D4 and the coil L10 are parallelly connected and a trap circuit functions. The diode D5 and the coil L11 are parallelly connected and the trap circuit functions.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tuner circuit for receiving a high-frequency signal, and more particularly to a tuner circuit capable of adjusting a trap frequency according to a frequency of a selected channel.

[0002]

2. Description of the Related Art A conventional tuner circuit 900.1 will be described with reference to FIG. FIG. 5 shows a conventional tuner circuit 9.
It is a figure which shows the structure of the principal part of 00.1. Referring to FIG. 5, a conventional tuner circuit 900.1 includes an input filter 2, an input tuning circuit 3, a high-frequency amplifier circuit 5, an inter-stage tuning circuit 6, coupling sections 4 # 1 and 7 # 1, and a mixer 8. Prepare.

A tuner circuit 900.1 selects a signal of a desired channel from high frequency signals (VHF) received by the antenna 1. The selected signal is converted to an intermediate frequency via the mixer 8.

[0004] The input filter 2 is composed of a high-pass filter. The input filter 2 removes interference waves and noise components of the signal received by the antenna 1. The input tuning circuit 3
It consists of a band pass filter. The input tuning circuit 3 tunes the signal of the selected channel among the signals output from the input filter 2 to the frequency of the selected channel in response to the high-band bias voltage BH and the tuning voltage VT.

The high-frequency amplifier circuit 5 has an AGC voltage VA output from an AGC circuit (automatic gain control circuit) not shown.
In response to the GC, the signal output from the input tuning circuit 3 is amplified and output.

[0006] Coupling portion 4 # 1 includes a capacitor C4.
The capacitor C4 is connected between the input tuning circuit 3 and the high-frequency amplifier circuit 5.
And The inter-stage tuning circuit 6 further tunes the signal output from the high-frequency amplifier circuit 5 to the frequency of the selected channel in response to the tuning voltage VT and the high-band bias voltage BH or the low-band bias voltage BL. .

[0007] Coupling section 7 # 1 includes a capacitor C5.
Capacitor C5 couples interstage tuning circuit 6 and mixer 8. The signal output from the inter-stage tuning circuit 6 is
Is converted to an intermediate frequency signal.

Further, another example of the configuration of the conventional tuner circuit will be described with reference to FIG. FIG. 6 is a diagram showing a configuration of a main part of a conventional tuner circuit 900.2. Referring to FIG. 6, tuner circuit 900.2 includes coupling section 4 #
1 and a coupling portion 7 # 2 instead of the coupling portion 7 # 1.

[0009] Coupling portion 4 # 2 includes a diode D4, a capacitor C10 and a resistor R3. The diode D4 and the capacitor C10 are connected in series between the input tuning circuit 3 and the high frequency amplifier circuit 5. The resistor R3 has one terminal connected between the connection node between the diode D4 and the capacitor C10, and the other terminal connected to the ground potential.

[0010] Coupling section 7 # 2 includes a diode D5, a capacitor C11 and a resistor R9. Diode D5 and capacitor C11 are connected in series between interstage tuning circuit 6 and mixer 8. The resistor R9 has one terminal connected to a connection node between the diode D5 and the capacitor C11, and the other terminal connected to a ground potential.

The diodes D4 and D5 are variable capacitance diodes and function as capacitive elements. Capacitors C10 and C11 are capacitors for cutting an AC component. The resistors R3 and R9 each function as a discharge resistor.

[0012]

Generally, various interference frequencies are generated in a tuner circuit. For example, one of them is an image disturbance that always occurs when the tuner is operated.

However, the conventional tuner circuit 90
Since 0.1 and 900.2 are configured as described above, there is a problem that various interference frequencies cannot be reduced.

SUMMARY OF THE INVENTION Therefore, the present invention has been made to solve the above-described problem, and an object of the present invention is to provide a tuner circuit capable of efficiently reducing an interference frequency according to a frequency of a selected channel. It is to be.

[0015]

According to a first aspect of the present invention, there is provided a tuner circuit for converting a signal of a selected channel into an intermediate frequency among received high-frequency signals. Tuning means for tuning the channel signal to the frequency of the selected channel; amplifying means for amplifying the output of the tuning means; and a capacitance value provided between the tuning means and the amplifying means in response to the frequency of the selected channel. And a frequency varying means for varying the frequency characteristic by changing the inductance and the inductance.

Therefore, the frequency characteristic between the tuning circuit and the amplifier circuit can be changed according to the selected channel. This makes it possible to delete various interference frequencies according to the selected channel.

A tuner circuit according to a second aspect is a tuner circuit according to the first aspect.
In the tuner circuit according to the above, the frequency variable means, the capacitance means including a plurality of capacitive elements, by changing the connection relationship between the plurality of capacitive elements in response to the frequency of the selected channel, the tuning means and Control means for changing a capacitance value between the control means and the amplifying means.

Therefore, the coupling relationship between the plurality of capacitive elements between the tuning circuit and the amplifier circuit can be changed according to the frequency of the selected channel. Thereby, the trap frequency can be changed.

According to a third aspect of the present invention, there is provided a tuner circuit.
Wherein the frequency varying means further includes a coil, and the control means switches or disconnects the coil in parallel with the capacitance means in response to the frequency of the selected channel. Wherein the switch means connects the coil in parallel with the capacitance means when the frequency of the selected channel is higher than a predetermined level,
When the frequency of the selected channel is lower than a predetermined level, the coil is disconnected from the capacitance means.

Therefore, when the selected channel is higher than a predetermined level (high band), the capacitive element and the coil are connected in parallel between the tuning circuit and the amplifier circuit. Thus, when the high band is selected, a trap circuit is formed between the tuning circuit and the amplifier circuit, so that the interference frequency can be reduced.

According to a fourth aspect of the present invention, there is provided a tuner circuit.
Wherein the frequency varying means further includes a coil, and the control means switches or disconnects the coil in parallel with the capacitance means in response to the frequency of the selected channel. Wherein the switch means connects the coil to the capacitance means in parallel when the frequency of the selected channel is lower than a predetermined level,
If the frequency of the selected channel is higher than a predetermined level, the coil is disconnected from the capacitance means.

Therefore, when the selected channel is lower than the predetermined level (low band), the capacitive element and the coil are connected in parallel between the tuning circuit and the amplifier circuit. Thereby, when the low band is selected, a trap circuit is formed between the tuning circuit and the amplifier circuit, and it is possible to reduce the interference frequency.

A tuner circuit according to a fifth aspect of the present invention is a tuner circuit for converting a signal of a selected channel among received high-frequency signals into an intermediate frequency, and selects a signal of the selected channel among received signals. Tuning means for tuning to the frequency of the selected channel, amplifying means for amplifying the output of the tuning means, converting means for converting the output of the amplifying means to an intermediate frequency, provided between the amplifying means and the converting means, and selected. Frequency varying means for varying a frequency characteristic by changing a capacitance value and an inductance in response to a channel frequency.

Therefore, the frequency characteristic between the amplifier circuit and the conversion circuit can be changed according to the selected channel. This makes it possible to delete various interference frequencies according to the selected channel.

A tuner circuit according to claim 6 is a tuner circuit according to claim 5.
In the tuner circuit according to the above, the frequency variable means, the capacitance means including a plurality of capacitive elements, by changing the connection relationship of the plurality of capacitive elements in response to the frequency of the selected channel, amplifying means and Control means for changing a capacitance value between the conversion means and the conversion means.

Therefore, the coupling relationship between a plurality of capacitive elements between the tuning circuit and the amplifier circuit can be changed according to the frequency of the selected channel. Thereby, the trap frequency can be changed.

The tuner circuit according to claim 7 is the tuner circuit according to claim 6
Wherein the frequency varying means further includes a coil, and the control means switches or disconnects the coil in parallel with the capacitance means in response to the frequency of the selected channel. Wherein the switch means connects the coil in parallel with the capacitance means when the frequency of the selected channel is higher than a predetermined level,
When the frequency of the selected channel is lower than a predetermined level, the coil is disconnected from the capacitance means.

Therefore, when the selected channel is higher than a predetermined level (high band), the capacitive element and the coil are connected in parallel between the tuning circuit and the amplifier circuit. Thus, when the high band is selected, a trap circuit is formed between the tuning circuit and the amplifier circuit, so that the interference frequency can be reduced.

The tuner circuit according to claim 8 is the tuner circuit according to claim 6.
Wherein the frequency varying means further includes a coil, and the control means switches or disconnects the coil in parallel with the capacitance means in response to the frequency of the selected channel. Wherein the switch means connects the coil to the capacitance means in parallel when the frequency of the selected channel is lower than a predetermined level,
If the frequency of the selected channel is higher than a predetermined level, the coil is disconnected from the capacitance means.

Therefore, when the selected channel is lower than the predetermined level (low band), the capacitive element and the coil are connected in parallel between the amplifier circuit and the conversion circuit. Thus, when the low band is selected, a trap circuit is formed between the amplifier circuit and the conversion circuit, and it is possible to reduce the interference frequency.

A tuner circuit according to a ninth aspect is a tuner circuit for converting a signal of a selected channel among received high-frequency signals into an intermediate frequency, and selecting a signal of the selected channel among received signals. Tuning means for tuning to the frequency of the tuned channel, amplifying means for amplifying the output of the tuning means, conversion means for converting the output of the tuning means to an intermediate frequency, and a selected means provided between the tuning means and the amplifying means. A first frequency variable means for changing a frequency characteristic by changing a capacitance value and an inductance in response to a frequency of a channel; and a first frequency variable means provided between an amplifying means and a converting means. A second frequency varying means for varying the frequency characteristic by changing the capacitance value and the inductance.

Therefore, the frequency characteristics between the tuning circuit and the amplifier circuit and between the amplifier circuit and the conversion circuit can be respectively changed according to the selected channel. This makes it possible to delete various interference frequencies according to the selected channel.

A tuner circuit according to a tenth aspect is the tuner circuit according to the ninth aspect, wherein the first frequency variable means includes a first capacitance means including a plurality of first capacitive elements;
First control means for changing a connection value of the plurality of first capacitive elements in response to a frequency of the selected channel to thereby change a capacitance value between the tuning means and the amplifying means; The second frequency variable means includes a plurality of second
A capacitance value between the amplifying means and the converting means by changing a connection relationship between the second capacitive means including the first capacitive element and the plurality of second capacitive elements in response to the frequency of the selected channel. And second control means for changing

Therefore, according to the frequency of the selected channel, the coupling relationship between the plurality of capacitive elements between the tuning circuit and the amplifier circuit and the coupling relationship between the plurality of capacitive elements between the amplifier circuit and the conversion circuit. Can be changed respectively. Thereby, the trap frequency can be changed.

The tuner circuit according to claim 11 is the tuner circuit according to claim 10, wherein the first frequency variable means further includes a first coil, and the first control means comprises:
A first switching means for connecting or disconnecting the first coil in parallel with the first capacitance means in response to a frequency of the selected channel; Second control means for connecting or disconnecting the second coil in parallel with the second capacitance means in response to the frequency of the selected channel. including.

Therefore, when the selected channel is lower than the predetermined level (or higher than the predetermined level), the capacitive element and the coil are connected in parallel between the tuning circuit and the amplifier circuit, and the selected channel is selected. When the channel is higher than the predetermined level (or lower than the predetermined level), the capacitive element and the coil are connected in parallel between the amplifier circuit and the conversion circuit. Thus, a trap circuit is formed between the tuning circuit and the amplifier circuit, and a trap circuit is formed between the amplifier circuit and the conversion circuit, depending on the selected channel. As a result, various interference frequencies can be reduced.

[0037]

[First Embodiment] A tuner circuit 100 according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a schematic block diagram showing an example of a configuration of a main part of tuner circuit 100 according to Embodiment 1 of the present invention. FIG. 2 is an example of a specific configuration of a main part of tuner circuit 100 shown in FIG. FIG.

Referring to FIG. 1, tuner circuit 100 includes:
It includes an input filter 12, an input tuning circuit 13, a high-frequency amplifier circuit 15, an interstage tuning circuit 16, a mixer 18, and variable trap units 20 and 21.

The variable trap units 20 and 21 according to the first embodiment of the present invention function as a trap circuit according to the selected channel, and change the desired trap frequency by changing the size of the capacitance. Thereby, the image frequency and the like in the tuner circuit 100 are adjusted according to each of the high band and the low band.

The input filter 12 is composed of a high-pass filter. The input filter 12 removes an interference wave and a noise component of the signal received by the antenna 1. The mixer 18
The signal output from the variable trap unit 21 is converted into an intermediate frequency signal.

An example of a specific configuration of the input tuning circuit 13 will be described. Referring to FIG. 2, the input tuning circuit 13 includes:
Resistors R1 and R2, coils L1 and L6, capacitors C1, C16 and C17, and diode D1
And D6. The input tuning circuit 13 is connected to the input filter 12 at a node N0 and to a variable trap unit 20 described later at a node N1.

One terminal of the capacitor C1 is connected to the node N
Connected to 0. Coil L1, coil L6 and capacitor C17 are connected in series between node N0 and the ground potential. Connection node N4 between coil L1 and coil L6
And a ground potential, a diode D6 and a capacitor C16 are connected in series. A connection node between the diode D6 and the capacitor C16 receives the high-band bias voltage BH. A resistor R is connected between node N4 and the ground potential.
2 are connected.

The other terminal of the capacitor C1 is connected to the node N
1 is connected. Diode D1 is connected between node N1 and the ground potential. Node N1 receives tuning voltage VT via resistor R1.

The coil L1, the capacitor C1, and the diode D1 constitute a high-band input tuning circuit.
The coils L1 and L6, the capacitor C1, and the diode D1 form a low-band input tuning circuit.

The diode D1 is a variable capacitance diode, and changes the capacitance according to the tuning voltage VT. Resistance R
1 is a bias resistor for the tuning voltage VT. Resistance R2
Is a high-band switching bias resistor.
Capacitors C16 and C17 are ground capacitors.

The operation of the input tuning circuit 13 will be described. The diode D6 functions as a switch for switching (changing the resonance frequency) between the high band channel and the low band channel.

The high-band bias voltage BH and the low-band bias voltage BL are complementary to each other. Specifically, when a high-band signal is selected, the high-band bias voltage BH goes high and the low-band bias voltage BL goes low. On the other hand, when the low-band signal is selected, the high-band bias voltage BH goes low and the low-band bias voltage BL goes high.

When the high-band bias voltage BH is selected (high-band selection), the diode D6 is turned on. As a result, the signal that has passed through the input filter 12 resonates in the coil L1, the capacitor C1, and the diode D1.

On the other hand, when the low-band bias voltage BL is applied (low-band selection), the diode D6
Becomes non-conductive. As a result, the signal that has passed through the input filter 12 is output to the coils L1 and L6 and the capacitor C
1 and the diode D1.

Next, an example of a specific configuration of the high-frequency amplifier circuit 15 will be described. The high-frequency amplifier 15 includes a field-effect transistor Q1, resistors R4 and R5, and a capacitor C9. The transistor Q1 is a dual gate MOSFET. The resistor R4 is a bias resistor for AGC, and the resistor R5 is a resistor for preventing parasitic oscillation of the FET. The capacitor C9 is a ground capacitor.

The first gate electrode of the transistor Q1 is
It is connected to an output node of the variable trap section 20 described later. A second gate electrode of the transistor Q1 is connected to an AGC voltage V from an AGC circuit (not shown) via a resistor R4.
Receive AGC. A capacitor C9 is connected between the second gate electrode and the ground potential. The source of transistor Q1 is connected to the ground potential, and the drain is connected to one terminal of resistor R5.

The high-frequency amplifier circuit 15 includes an AGC (not shown).
In response to the AGC voltage VAGC outputted from the circuit, the signal outputted from the input tuning circuit 13 is amplified and outputted.

Next, an example of a specific configuration of the interstage tuning circuit 16 will be described. Referring to FIG. 2, the interstage tuning circuit (symbol 16 # 1 in the figure) includes coils L2, L3, L7, L
8 and L9, capacitors C2, C3, C7, C8, C
18 and C19, and diodes D2, D3, D
7 and D8. The inter-stage tuning circuit 16 # 1 is connected at a node N2 to the high-frequency amplifier circuit 15 (the other terminal of the resistor R5), and is connected at a node N3 to a variable trap unit 21 described later.

A capacitor C2 and a diode D2 are connected in series between the node N2 and the ground potential. The connection node between the capacitor C2 and the diode D2 is a resistor R
6 receives the tuning voltage VT. Furthermore, coils L2 and L7 are connected in series to node N2. A diode D7 and a capacitor C7 are connected in series to a connection node between the coils L2 and L7. A connection node between the diode D7 and the capacitor C7 receives a high-band bias voltage BH. The other terminal of the capacitor C7 is
Connected to ground potential.

A diode D3 is connected between the node N3 and the ground potential. Node N3 receives tuning voltage VT via resistor R7. Further, a coil L3, a capacitor C3, and a coil L8 are connected in series to the node N3. At the connection node between the capacitor C3 and the coil L8,
Diode D8 and capacitor C8 are connected in series. A connection node between the diode D8 and the capacitor C8 receives the high-band bias voltage BH. The other terminal of capacitor C8 is connected to the ground potential.

A coil L9 and a capacitor C18 are connected in series between one terminal of each of the coils L7 and L8 and the ground potential. Coil L9 and capacitor C
18 is connected to a low-band bias voltage B
Receive L.

The coil L2, the capacitor C2 and the diode D2 constitute a high-band interstage primary tuning circuit. The coils L2 and L7, the capacitor C2 and the diode D2 constitute a low-band interstage primary tuning circuit. Coil L3, capacitor C3 and diode D
Reference numeral 3 denotes a high-band interstage secondary tuning circuit. The coils L3 and L8, the capacitor C3, and the diode D3 form a low-band interstage secondary tuning circuit.
Capacitor C19 is a capacitor for coupling the interstage primary tuning circuit and the interstage secondary tuning circuit. One terminal is connected to node N2, and the other terminal is connected to node N3.

The diodes D2 and D3 are variable capacitance diodes, and change the capacitance according to the tuning voltage VT. The resistors R6 and R7 are bias resistors for the tuning voltage VT. Capacitors C7, C8 and C18
Is a ground capacitor.

The operation of interstage tuning circuit 16 # 1 will be described. The diodes D7 and D8 function as switches for switching between a high-band channel and a low-band channel (changing the resonance frequency). The diodes D7 and D8 are turned on when the high-band bias voltage BH is applied.

When high-band bias voltage BH is applied (high-band selection), diodes D7 and D8 are turned on. Thereby, the transistor Q
1 passes through a high-band interstage primary tuning circuit (coil L2, capacitor C2 and diode D2)
, And furthermore, the interstage secondary tuning circuit (coil L
3. Resonate at the capacitor C3 and the diode D3).

When the low-band bias voltage BL is applied (low-band selection), the diodes D7 and D8 are off. Thus, the signal passing through the transistor Q1 resonates in the low-band interstage primary tuning circuit (coils L2, L7 and L9, the capacitor C2 and the diode D2), and further interstage secondary tuning circuits (coils L3 and L8). And L9, capacitor C
3 and the diode D3).

Next, a specific configuration of the variable trap units 20 and 21 according to the first embodiment of the present invention shown in FIGS. 1 and 2 will be described with reference to FIG. FIG.
FIG. 3 is a circuit diagram showing an example of a specific configuration of variable trap units 20 and 21 shown in FIGS.

Referring to FIG. 3, variable trap unit 20 includes:
Capacitors C10, C12 and C13, resistors R3, R
10, and R11, diodes D4 and D9, and coil L10.

A diode D4 and a capacitor C are connected between the node N1 and the first gate electrode of the transistor Q1.
10 are connected in series. A capacitor C12 and a resistor R10 are connected in series between the node N1 and the ground potential. One terminal of the diode D9 is a capacitor C
12 is connected to a connection node between the resistor R10 and the other terminal, and the other terminal is connected to one terminal of the capacitor C13. The other terminal of the capacitor C13 is connected to one terminal of the coil L10. A connection node between the diode D9 and the capacitor C13 receives the high-band bias voltage BH via the resistor R11. The other terminal of the coil L10 is
It is connected to the connection node between diode D4 and capacitor C10. One terminal of resistor R3 is connected to a connection node between coil L10 and capacitor 13, and the other terminal is connected to ground potential.

The diode D4 is a variable capacitance diode and functions as a capacitive element. The diode D9 is
Functions as a switch. The capacitor C12 is a capacitor for cutting an AC component, and the resistors R10 and R11 are switching bias resistors for a high band.

The variable trap section 21 includes a capacitor C1
1, C14 and C15, resistors R9, R12 and R1
3, diodes D5 and D10, and coil L1
Including 1.

A diode D5 and a capacitor C11 are connected in series between the node N3 and the input node of the mixer 18. A capacitor C14 and a resistor R12 are connected in series between the node N3 and the ground potential. One terminal of the diode D10 is connected to the capacitor C14 and the resistor R
12, and the other terminal is connected to one terminal of the capacitor C15. Capacitor C15
Is connected to one terminal of the coil L11. The connection node between the diode D10 and the capacitor C15 is connected to a high-band bias voltage B via a resistor R13.
Receive H. The resistor R9 has one terminal connected to a connection node between the coil L11 and the capacitor C15, and the other terminal connected to a ground potential. The other terminal of coil L11 is connected to a connection node between diode D5 and capacitor C11.

The diode D5 is a variable capacitance diode and functions as a capacitive element. Diode D10
Functions as a switch. The capacitor C14 is a capacitor for cutting an AC component, and includes a resistor R1
2 and R13 are high-band switching bias resistors.

Next, the operation of the variable trap units 20 and 21 will be described. Bias voltage BL for low band
Is applied, diodes D9 and D10 are both turned off. Therefore, like the conventional tuner circuit, the diodes D4 and D5 function only as coupling capacitors.

On the other hand, when the high-band bias voltage BH is applied, the diode D9 is turned on. Therefore, the diode D4 and the coil L10 are connected in parallel between the input tuning circuit 13 and the high-frequency tuning circuit 15. Thereby, the diode D4 and the coil L10 function as a trap circuit. Further, the diode D10 becomes conductive. Therefore, the diode D5 and the coil L11 are connected in parallel between the inter-stage tuning circuit 16 and the mixer 18. Thereby, the diode D5 and the coil L1 function as a trap circuit.

As described above, in the tuner circuit 100 according to the first embodiment of the present invention, the trap circuit can be selectively operated according to the band to be applied, and the maximum capacity can be obtained by making the coupling capacitance variable. It is possible to realize a trap function.

The voltage applied to the diodes D9 and D10 may be not only the bias voltage BH for the high band but also the bias voltage BL for the low band. Further, switching may be performed in one of the variable trap units 20 and 21 in the high band, and switching may be performed in the other in the low band. Switching can be switched according to the attenuation frequency.

It should be noted that interstage tuning circuit 16 # 2 shown in FIG. 4 may be used instead of interstage tuning circuit 16 # 1 shown in FIG. FIG. 4 is a circuit diagram showing another example of a specific configuration of the interstage tuning circuit 16 shown in FIG. Interstage tuning circuit 16 # 2 shown in FIG. 4 further includes resistors R14 and R15 in addition to the configuration of interstage tuning circuit 16 # 1 shown in FIG. The resistor R14 is connected between the coils L7 and L9. The resistor R15 is connected between the coils L8 and L9. The resistors R14 and R15 are damping resistors and play a role in lowering the power gain when the low band is selected. By using the inter-stage tuning circuit 16 # 2 shown in FIG. 4 together with the variable trap units 20 and 21, the interference frequency can be effectively reduced.

It should be understood that the embodiments disclosed herein are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[Brief description of the drawings]

FIG. 1 is a tuner circuit 1 according to a first embodiment of the present invention.
It is a schematic block diagram which shows an example of a structure of the principal part of 00.

FIG. 2 is a diagram showing an example of a specific configuration of a main part of the tuner circuit 100 shown in FIG.

FIG. 3 shows the variable trap units 20 and 2 shown in FIGS.
1 is a circuit diagram showing an example of a specific configuration of FIG.

FIG. 4 is a circuit diagram showing another example of a specific configuration of the interstage tuning circuit 16 shown in FIG. 1;

FIG. 5 is a diagram showing a configuration of a main part of a conventional tuner circuit 900.1.

FIG. 6 is a diagram showing a configuration of a main part of a conventional tuner circuit 900.2.

[Explanation of symbols]

 Reference Signs List 1 antenna 12 input filter 13 input tuning circuit 15 high-frequency amplifier 16, 16 増 幅 器 1, 16、2 interstage tuning circuit 18 mixer 20, 21 variable trap unit L1 to L11 coil C1 to C19 capacitor D1 to D10 diode R1 to R15 resistor Q1 Field effect transistor 100 Tuner circuit

Claims (11)

[Claims] 1. A tuner circuit for converting a signal of a selected channel among received high-frequency signals to an intermediate frequency, wherein the signal of the selected channel is converted to a frequency of the selected channel among the received signals. Tuning means for tuning; amplifying means for amplifying an output of the tuning means; provided between the tuning means and the amplifying means, for changing a capacitance value and an inductance in response to a frequency of the selected channel. A tuner circuit comprising frequency variable means for varying a frequency characteristic. 2. The tuning means according to claim 2, wherein said frequency varying means comprises: a capacitance means including a plurality of capacitive elements; and said tuning means by changing a connection relationship between said plurality of capacitive elements in response to a frequency of said selected channel. 2. The tuner circuit according to claim 1, further comprising control means for changing a capacitance value between the tuner circuit and the amplifying means. 3. The frequency changing means further includes a coil, and the control means connects or disconnects the coil in parallel with the capacitance means in response to a frequency of the selected channel. When the frequency of the selected channel is higher than a predetermined level, the switch connects the coil in parallel with the capacitance means, and the frequency of the selected channel is higher than the predetermined level. 3. The tuner circuit according to claim 2, wherein when the voltage is low, the coil is disconnected from the capacitance means. 4. The frequency changing means further includes a coil, and the control means connects or disconnects the coil in parallel with the capacitance means in response to a frequency of the selected channel. When the frequency of the selected channel is lower than a predetermined level, the switch connects the coil in parallel with the capacitance unit, and the frequency of the selected channel is higher than the predetermined level. The tuner circuit according to claim 2, wherein when higher, the coil is disconnected from the capacitance means. 5. A tuner circuit for converting a signal of a selected channel among received high-frequency signals to an intermediate frequency, wherein the signal of the selected channel among the received signals is converted to a frequency of the selected channel. Tuning means for tuning; amplifying means for amplifying the output of the tuning means; converting means for converting the output of the amplifying means to the intermediate frequency; and the selecting means provided between the amplifying means and the converting means; A frequency varying means for varying a frequency characteristic by changing a capacitance value and an inductance in response to a frequency of the selected channel. 6. The amplifying unit according to claim 6, wherein the frequency varying unit includes a capacitance unit including a plurality of capacitive elements, and a connection relationship between the plurality of capacitive elements in response to a frequency of the selected channel. 6. The tuner circuit according to claim 5, further comprising control means for changing a capacitance value between the control means and the conversion means. 7. The frequency varying means further includes a coil, and the control means connects or disconnects the coil in parallel with the capacitance means in response to a frequency of the selected channel. When the frequency of the selected channel is higher than a predetermined level, the switch connects the coil in parallel with the capacitance means, and the frequency of the selected channel is higher than the predetermined level. 7. The tuner circuit according to claim 6, wherein when low, said coil is disconnected from said capacitance means. 8. The frequency varying unit further includes a coil having the inductance, and the control unit connects the coil to the capacitance unit in parallel in response to a frequency of the selected channel, or When the frequency of the selected channel is lower than a predetermined level, the switch connects the coil in parallel with the capacitance unit, and the frequency of the selected channel is 7. The tuner circuit according to claim 6, wherein said coil is disconnected from said capacitance means when said level is higher than a predetermined level. 9. A tuner circuit for converting a signal of a selected channel among received high-frequency signals to an intermediate frequency, wherein the tuner circuit converts the signal of the selected channel among the received signals to a frequency of the selected channel. Tuning means for tuning; amplifying means for amplifying an output of the tuning means; converting means for converting an output of the amplifying means to the intermediate frequency; and a selecting means provided between the tuning means and the amplifying means; A first frequency variable means for changing a frequency characteristic by changing a capacitance value and an inductance in response to the frequency of the selected channel, and provided between the amplifying means and the converting means, A second frequency varying unit that varies a frequency characteristic by changing a capacitance value and an inductance in response to a frequency. , A tuner circuit. 10. The first frequency variable means includes: first capacitance means including a plurality of first capacitive elements; and the plurality of first capacitive elements in response to a frequency of the selected channel. By changing the connection relationship of
A first control means for changing a capacitance value between the tuning means and the amplifying means, wherein the second frequency variable means includes a second capacitance means including a plurality of second capacitive elements; Changing the connection relationship of the plurality of second capacitive elements in response to the frequency of the selected channel,
10. The tuner circuit according to claim 9, further comprising: a second control unit that changes a capacitance value between the amplification unit and the conversion unit. 11. The first frequency varying means further includes a first coil, and the first control means responds to a frequency of the selected channel with respect to the first capacitance means. The first frequency control means includes first switch means for connecting or disconnecting the first coil in parallel, the second frequency variable means further includes a second coil, and the second control means includes: And a second switch means for connecting or disconnecting the second coil in parallel with the second capacitance means in response to a frequency of the selected channel.
0. The tuner circuit according to 0.