JPH1126391A - Local annealing method, manufacture of semiconductor element, and semiconductor element - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable easy local annealing of a semiconductor element, by generating electric conduction and heating a wiring which is made of a heat-resistant material and locally formed directly on or through an insulating film on the semiconductor element during a manufacturing process. SOLUTION: In manufacturing a field-effect transistor, a gate electrode 35 having, at its both ends, terminals for electric conduction made of a heat-resistant material is formed in a predetermined part on a first impurity introducing region 33 formed on a GaAs substrate 31, by using a lithography technique or a film forming technique. In the manufacturing process after that, impurity is introduced to form source/drain regions and a channel region. In addition, first layer wirings 51a to 51c, a second interlayer insulating film 53, and a second layer wiring 55 are formed, and a passivation film 57 is formed, thereby providing a semiconductor element. In the case where local annealing is carried out, a current is caused to flow via the terminals of the gate electrode 35. Thus, power is consumed at the portion between the terminals and heat is generated. The temperature of the impurity introducing region 33 under the gate electrode 35 and in the vicinity thereof is raised to such a degree as to generate an annealing effect.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for selectively annealing one or a plurality of localities in a semiconductor device, a method for manufacturing a semiconductor device using the method, and a structure suitable for implementing these methods. And a semiconductor device having the same.

[0002]

2. Description of the Related Art When manufacturing a semiconductor device, impurities are selectively introduced into a semiconductor substrate by an impurity diffusion method, an ion implantation method, or the like. In addition, the semiconductor substrate is annealed to recover crystal damage caused in the semiconductor substrate due to the introduced impurities and to put the impurities into a correct lattice position and activate the impurities as donors or acceptors. (For example, Reference I: Baifukan “Ultra High-Speed Compound Semiconductor Device”, Masamichi Omori, First Edition in 1986, pp. 190-195).

This annealing is generally performed on a semiconductor substrate (semiconductor wafer) on which a large number of semiconductor elements are formed. Specifically, this is performed by placing the semiconductor wafer in an atmosphere at a temperature of several hundred degrees to several hundreds degrees for several minutes to several hours.

[0004]

By the way, a semiconductor element is required to have electrical characteristics as designed. However, since a large number of semiconductor elements are manufactured on a semiconductor substrate having a size of several inches, the electrical characteristics vary from one semiconductor element to another obtained from one semiconductor substrate. The main reason is that
This is because it is difficult to uniformly perform various processes (for example, impurity ion implantation, annealing, and the like) performed in a semiconductor device manufacturing stage at various locations in a semiconductor substrate.

[0005] If the electrical characteristics of the semiconductor element are not as designed, for example, the following problems occur.

Here, as a semiconductor element, reference II (Technical Research Report of IEICE, E93-155, pp.
53 to 58) are considered. FIG. 11 is an explanatory diagram of the bias circuit 10 included in the multiplexer and the demultiplexer.

The bias circuit 10 is provided at an input stage of a clock input circuit provided in the above-described multiplexer or demultiplexer or an input stage of a data input circuit provided in the above-described demultiplexer. However, in FIG.
Details of the internal circuits of the clock input circuit and the data input circuit are omitted, and the internal circuits are simply shown as a broken-line frame 20.

The bias circuit 10 includes a depletion-type FET 11 as a first field-effect transistor,
It comprises an enhancement type FET 13 as a second field effect transistor and a capacitor 15. The first and second field effect transistors 11, 13 are connected in series. That is, DCFL (Direct Coupled FET)
Logic). In addition, both transistors 11, 1
The connection points of the three transistors and the gate electrodes of the transistors 11 and 13 are connected. Therefore, both transistors 1
Reference numerals 1 and 13 are equivalent to resistance elements. A capacitor 15 is connected between the connection point between the transistors 11 and 13 and the ground.
Is connected. The terminal of the capacitor 15 opposite to the ground side is connected via a terminating resistor 21 to a signal input terminal 23 of a clock input circuit or a data input circuit.

In the case of the bias circuit 10, the voltage at the connection point between the first and second transistors 11, 13 is used as the bias voltage for the clock signal and the data signal. In order to normally operate the above-described multiplexer and demultiplexer, it is necessary to set the bias voltage supplied from the bias circuit 10 to a design value. However, there is a case where the bias voltage deviates from the design value due to the variation in the processing conditions in the above-described manufacturing process.

In the bias circuit 10, a semiconductor device (ie, the above-described multiplexer or demultiplexer)
If the bias voltage deviates from the design value after manufacturing, it is necessary to change the power supply voltage supplied to the power supply input terminal 10a of the bias circuit 10 to adjust the bias voltage to the design value. Specifically, an external power supply (not shown) is connected to the power supply input terminal 10a via a variable resistor (not shown), and the power supply input terminal 1a is connected by a voltage drop of the variable resistor.
The power supply voltage supplied to Oa is changed. However, in this case, it is necessary to provide the variable resistor on a motherboard or the like, and accordingly, there is a problem that the device is increased in size. In addition, since noise outside the semiconductor element may flow into the semiconductor element via the variable resistor, there is a problem that bias adjustment cannot be stably performed.

Here, as one of the adjusting methods when the electric characteristics of the semiconductor device deviate from the design values, the local characteristics of the semiconductor device are selectively annealed to change the electric characteristics of the semiconductor device. A method is conceivable. In the example of the bias circuit 10 described above, by selectively annealing one of the channel regions of the first and second field-effect transistors 11 and 13, the electrical characteristics of the field-effect transistor, specifically, A method of changing a threshold value, a mutual conductance, and the like can be considered. However, annealing the semiconductor element itself (the semiconductor substrate itself on which a large number of semiconductor elements have been fabricated) causes problems such as melting of the aluminum wiring in the semiconductor element and further widening the variation in the characteristics of the semiconductor element. Likely to occur. On the other hand, such a phenomenon does not occur if the local annealing is performed. For example, in document 193
It is considered that laser annealing and electron beam annealing described on the page can be used as a technique for annealing local portions of a semiconductor element. However, laser annealing or the like is not preferable because the apparatus is expensive. Furthermore, in this case, it is necessary to measure the electrical characteristics of the individual devices and anneal according to the characteristics to change the device characteristics.
The process becomes complicated.

Therefore, a new method for annealing local portions of a semiconductor device is desired. In addition, a new method for manufacturing a semiconductor device using the new local annealing method is desired. Further, a semiconductor device having a structure suitable for implementing this novel manufacturing method is desired.

[0013]

Therefore, in the local annealing method of this application, a local portion of a semiconductor element manufactured by a manufacturing method including an impurity introducing step and a first annealing step for activating the impurity is removed. In order to make it possible to perform annealing separately after the first annealing step, a wiring made of a heat-resistant material (hereinafter, referred to as a wire) on the local part directly or through an insulating film during the manufacturing step of the semiconductor element. A local annealing wire is also formed. And
The local annealing is performed by causing the wiring to generate heat to such an extent that the wiring is energized to give an annealing effect locally.

According to this local annealing method, after performing the first annealing step performed in the manufacturing process of the semiconductor device, it is possible to selectively perform annealing locally on the semiconductor device. Needless to say, local annealing can be selectively performed only by energizing the local annealing wiring under predetermined conditions. Needless to say, the location where the local annealing wiring is provided can be one or a plurality of locations where local annealing will be required later. Needless to say, since the local annealing wiring can be formed simultaneously with the original wiring of the semiconductor element during the manufacturing process of the semiconductor element, the preparation of the local annealing wiring can be easily performed.

In carrying out this local annealing method, the local region is typically a p-type or n-type impurity introduction region in a semiconductor device. Specifically, the resistive layer is a channel region of an arbitrary field-effect transistor in a semiconductor device or a resistive layer including an impurity-doped region in the semiconductor device.

When the local annealing method is performed, the impurity-introduced region itself that has been subjected to the first annealing step (that is, the annealing step generally performed in a semiconductor device manufacturing step) is annealed by the local annealing method of the present invention. Is also good. Alternatively, an impurity may be further introduced into the impurity introduction region after the first annealing step, and this layer may be annealed by the local annealing method of the present invention. It is considered that the latter can increase the adjustment range of the electrical characteristics. In addition,
When the impurity is further introduced as described above, it is preferable to carry out the impurity in advance during the manufacturing process of the semiconductor element.

In the invention of the method of manufacturing a semiconductor device of the present application, the case of manufacturing a semiconductor device including a field effect transistor and the case where the semiconductor device includes first and second field effect transistors, for example, are described with reference to FIG. When a semiconductor element including a bias circuit is manufactured, a gate electrode made of a heat-resistant material and having first and second terminals for conduction is formed as a gate electrode of a field-effect transistor. After the original annealing step performed in the manufacturing process of the semiconductor element, the first and second gate electrodes are applied to the gate electrode.
To generate heat so that an annealing effect is exerted on the channel region of the field effect transistor. The heat anneals the channel region to adjust the electrical characteristics of the semiconductor device. Therefore, the electric characteristics of the field effect transistor and the bias voltage of the above-described bias circuit can be easily adjusted.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device including a resistor including an impurity-doped region, or a method of forming a voltage divider including two or more resistors. When manufacturing a semiconductor device including two or more impurity-introduced regions, a first current-carrying material made of a heat-resistant material directly or via an insulating film on the impurity-introduced regions
A wiring including the terminal and the second terminal is formed. Then, after the original annealing step performed in the manufacturing process of the semiconductor element, the wiring is energized through the first and second terminals to generate heat so that the wiring has an annealing effect on the impurity introduction region. Let it. With this heat, the impurity introduction region is annealed to adjust the resistance value of this layer. Therefore, the resistance value of the resistor and the voltage division ratio of the voltage divider can be easily adjusted.

According to a first aspect of the present invention, in a semiconductor device having a field effect transistor, the first and second current-carrying materials are formed of a heat-resistant material as a gate electrode of the field-effect transistor. A gate electrode having two terminals is provided.

According to a second aspect of the present invention, the first and second field-effect transistors are connected in series, and the connection point is connected to each gate electrode. In a semiconductor device including first and second field-effect transistors in which a voltage from this connection point is used as a bias voltage, a gate electrode of each of the first and second field-effect transistors is made of a heat-resistant material. A gate electrode having a first terminal and a second terminal for conducting electricity is provided.

According to a third aspect of the present invention, in a semiconductor device having a semiconductor substrate provided with a resistor comprising an impurity-doped region, the semiconductor device has a resistor directly or via an insulating film on the impurity-doped region. It is characterized by comprising a wiring made of a heat-resistant material and having a first terminal and a second terminal for conducting electricity.

According to a fourth aspect of the present invention, in a semiconductor device having two or more impurity introduction regions for forming a voltage divider comprising two or more resistors in a semiconductor substrate, On two or more impurity-introduced regions, a wiring made of a heat-resistant material and having a first terminal and a second terminal for electric conduction is provided directly or through an insulating film.

According to the first and second aspects of the present invention, a current is caused to flow through the gate electrode using the first and second terminals, thereby selectively selecting a channel region of the field effect transistor. Can be annealed. According to the third and fourth aspects of the semiconductor device, respectively, selectively annealing the impurity-introduced region as a resistor by passing a current through the wiring using the first and second terminals. Can be.

[0024]

Embodiments of the present invention will be described below with reference to the drawings. However,
The drawings used in the description merely schematically show the dimensions, shapes, and arrangements of the components so that the present invention can be understood. In each of the drawings, the same components are denoted by the same reference numerals, and duplicate description thereof may be omitted.

1. First Embodiment First, a case where a field effect transistor (MESFET) is manufactured on a GaAs substrate as a semiconductor substrate, and an example in which the local annealing method of the present invention is applied to the field effect transistor will be described. This explanation is shown in FIG. 1 and FIG.
This will be described with reference to FIG. Here, FIG. 1 and FIG. 2 are manufacturing process diagrams of this field-effect transistor. In particular, FIG.
2 is a process diagram showing a sample in a manufacturing process as a cross-sectional view taken along a direction corresponding to the gate length direction of the field-effect transistor. FIG. 2 is a plan view of the sample of FIG. It is.

First, as shown in FIG.
An impurity for forming a channel region of a field effect transistor is introduced into a predetermined portion of the s substrate 31 by, for example, an ion implantation method. Thereby, the first impurity introduction region 33 is formed in the GaAs substrate 31. Next, a gate electrode 35 is formed in a predetermined portion on the first impurity introduction region 33 by using, for example, a known lithography technique and a film formation technique. However, the gate electrode 35 is made of a heat-resistant material and has first and second terminals 35a, 35 for conducting electricity.
b (see FIG. 2). Further, as the heat resistant material, for example, a high melting point metal such as tungsten can be used.

In the case where local annealing is performed after the completion of the semiconductor device, the terminals 35a and 35b are provided on the surface of the semiconductor device. Otherwise, a current for performing local annealing cannot be supplied. In such a case, the terminals 35a and 35b mentioned here are connected to the gate electrode 35 via a multilayer wiring. However, if local annealing is performed at an appropriate time during the semiconductor device manufacturing process after the original annealing, these terminals 3
5a and 35b can be formed integrally with the gate electrode 35.

Next, a side wall (not shown) is formed on the side wall of the gate electrode 35. This sidewall is
The source / drain region formed later is the gate electrode 35
Provided to prevent contact with Next, as shown in FIG. 1B, a resist pattern, for example, is formed on the sample as a mask 39 covering portions other than the impurity introduction region 33. Next, impurities for forming source / drain regions are introduced into the sample. This is performed by, for example, an ion implantation method. Thus, an impurity introduction region 41 (second impurity region 41) for forming a source / drain region is formed in the impurity introduction region 33 and in a region not covered by the gate electrode 35 and the sidewall. You.

Next, the entire sample is annealed at a temperature of several hundred degrees to several hundreds degrees for a predetermined time (several seconds to several hours) by a known method.

Next, in this embodiment, the gate electrode 3
Impurities are introduced into the semiconductor substrate near 5. This is because the electrical characteristics of the channel region can be easily changed by local annealing performed later. The nearby semiconductor substrate portion is determined according to the design, but may be, for example, a semiconductor substrate portion exposed by removing the sidewall.

This impurity introduction is performed, for example, as follows. First, the sidewalls are removed, and then, for example, a resist pattern (not shown) as a mask covering the portion other than the substrate portion on which the sidewalls are formed, on the sample.
Form. Then, for this sample, the same impurities as those used when introducing the impurities for forming the channel region are used.
For example, it is introduced by an ion implantation method. Or Figure 1
As shown in (C), first, the ohmic electrode 4 is formed on the second impurity introduction region 41 as a source / drain region.
Form 3 Further, on the sample, a first interlayer insulating film 45 having a contact hole 45a exposing the ohmic electrode 43 and a window 45b exposing a semiconductor substrate portion near the gate electrode is provided. A film 45 is formed. Then, for this sample, the same impurities as those used when introducing the impurities for forming the channel region are used.
For example, it is introduced by an ion implantation method. FIG. 1 (C)
In the figure, reference numeral 47 denotes a mask (for example, a resist pattern) used for forming the contact hole 45a and the window 45b of the first interlayer insulating film 45.

In each of the above two methods, the third impurity introduction region 49 is formed in the portion of the semiconductor substrate near the gate electrode 35 by performing the method.
(C)).

Next, the first layer wiring 51 is formed by a known method.
a to 51c are formed, a second interlayer insulating film 53 is further formed, a second layer wiring 55 is further formed, and a passivation film 57 is further formed to obtain a semiconductor element.

In the case of this semiconductor device, local annealing can be performed as described below.

Normally, a predetermined gate voltage is applied to the gate electrode 35 described above. However, when performing local annealing, a current flows through the gate electrode 35 via the first and second terminals 35a and 35b of the gate electrode 35. The flow current and I _AN, the first and second terminals 35a of the gate electrode 35, the resistance of the portion between 35b R
_G , the first and second terminals 3 of the gate electrode 35
In the portion between 5a and 35b, electric power represented by P _W = I _AN × _RG ² (W) is consumed, and heat is generated. In fact, the inventor of the present application has confirmed that the gold connected to the gate electrode 35 generates heat to such an extent that the gold is melted. Due to this heat, the temperature of the first impurity introduction region (channel region) 33 existing under the gate electrode 35 and in the vicinity thereof rises to the extent that an annealing effect is generated. Then, in particular, the impurities in third impurity introduction region 49 are activated because they are annealed. The rate of this activation is
It is mainly determined by the temperature of the gate electrode 35 and the time during which the gate electrode 35 is heated.

On the other hand, in the field effect transistor subjected to the local annealing as described above, the threshold voltage and the transconductance change from the values before the local annealing. That is, when the activation ratio increases, the threshold value shifts to the minus side when the field effect transistor is an n-channel transistor, and shifts to the plus side when the field-effect transistor is a p-channel transistor. Also, the transconductance increases. Therefore, it is understood that the electric characteristics of the field-effect transistor can be adjusted by the method of the present invention in which the gate electrode 35 is energized to perform local annealing.

The limitation of the heat generation temperature when performing local annealing as described above is mainly due to the ohmic electrode 4.
3. When the maximum temperature that does not damage the ohmic electrode 43 is T _OMAX , measures are taken so that the target annealing is performed even if the gate electrode 35 is heated so as not to exceed this temperature. For example, even when the temperature of the gate electrode 35 is increased to a temperature at which the annealing effect can be given to the first impurity region 33 as the channel region, the temperature of the ohmic electrode 43 does not exceed the above T _OMAX . Gate electrode 35 and ohmic electrode 43
Take precautionary measures such as separating from.

Next, a more specific method for adjusting the electric characteristics of the field effect transistor by local annealing and the effect of local annealing will be described.

FIG. 3 is a diagram for explaining this specific method, and FIG. 4 is a diagram for explaining the experimental results. In FIG. 3, I indicates a semiconductor element, and II indicates a system having an external power supply for annealing. Further, 61 is a terminal for electrically connecting an external power supply and the semiconductor element. Here,
An example in which local annealing is performed on a depletion-type field-effect transistor having a gate length of 0.5 μm and a gate width of 10 μm will be described.

The current source 63 is connected to the gate electrode 35 via the first switch SW1. Of course, a voltage source may be used instead of a current source. Further, the voltage source 65 is connected to the drain electrode D via the second switch SW2.

The relationship between the drain-source voltage V _ds and the drain current I _d of the field-effect transistor before the local annealing was performed was as shown by the characteristic I in FIG. However, when measuring the relationship between the drain-source voltage V _ds and the drain current I _d , the voltage between the gate electrode and the source electrode was 0 V, that is, the two electrodes were short-circuited. The same in.).

Next, SW2 is opened, SW1 is closed, and a current _IAN is applied to the gate electrode 35 for 5 minutes to perform local annealing. Next, SW1 is opened and the semiconductor element waits for cooling. Then, the relationship between the drain-source voltage V _ds and the drain current I _d is measured. The relationship was as shown by the characteristic II in FIG.

Next, SW2 is opened, SW1 is closed, and a current _IAN is applied to the gate electrode 35 for another 5 minutes, that is, local annealing is performed for 10 minutes in combination with the above-described local annealing. Next, SW1 is opened and the semiconductor element waits for cooling. Then, the relationship between the drain-source voltage V _ds and the drain current I _d is measured. The relationship was as shown by the characteristic III in FIG.

As can be seen from the results shown in FIG.
It can be seen that the saturation current of the depression type transistor increases as the local annealing time increases.

From the above, according to the local annealing method of the present invention, the electric characteristics of the semiconductor element can be irreversibly changed even after the manufacturing process of the semiconductor element is completed.

2. Second Embodiment Next, a second embodiment will be described with reference to FIG. FIG. 5 is a cross-sectional view of a semiconductor device for explaining a main part of the second embodiment. However, hatching indicating a cross section is omitted. FIG. 5 corresponds to a diagram in which the features of the second embodiment are illustrated in the structure of FIG. 1C and the illustration of the first interlayer insulating film 45 and the like is omitted.

In the second embodiment, the gate electrode 3
5 are formed on both sides along the gate length direction.
(The first impurity-introduced region 33 is annealed). The formation of the concave portion 71 is performed by, for example, using the sample after forming the first interlayer insulating film 45 described with reference to FIG.
This can be achieved by performing etching using 5 as an etching mask. Note that this etching is performed in the third region under the concave portion.
In order to efficiently introduce impurities into the impurity introduction region of
This step is preferably performed before the ion implantation step for forming the third impurity introduction region 49 (see FIG. 1C).

A semiconductor element is manufactured and local annealing is performed in the same manner as in the first embodiment except that the recess 71 is formed.

In the second embodiment, the following new effects can be expected in addition to the same effects as in the first embodiment.

First, when a current is applied to the gate electrode 35 to heat the channel region, it is considered that this heat is not easily transmitted to the ohmic electrode 43 due to the concave portion 71. Therefore, it is considered that the temperature rise of the ohmic electrode 43 can be suppressed as compared with the first embodiment. On the other hand, it is considered that the above-mentioned heat is likely to be trapped in the channel region by the provision of the concave portion 71, and thus it is considered that the efficiency of local annealing is improved.

When the field-effect transistor according to the second embodiment is operated, the distance that electrons travel in the channel region becomes longer due to the provision of the concave portion 71. That is, since the electrons travel on the side wall (indicated by P in FIG. 5) of the concave portion 71, the distance that the electrons travel in the channel region is:
become longer. Therefore, it is considered that electrons are more affected by the electrical characteristics of the channel region than in the case where the concave portion 71 is not provided. Therefore, it is considered that the degree of change in the electrical characteristics due to the local annealing increases.

3. Third Embodiment Next, an example in which the local annealing method of the present invention is applied to the bias circuit described with reference to FIG. 11 will be described. This will be described with reference to FIG. However, in FIG. 6, the same components as those described with reference to FIG.
The same reference numerals are given and their description is omitted.

In the third embodiment, as the gate electrode of the first field-effect transistor 11 in the bias circuit 10x, the first and second current-carrying materials are made of a heat-resistant material.
The gate electrode 11g having the terminals 11a and 11b is formed. In addition, as the gate electrode of the second field-effect transistor 13, a gate electrode 13g made of a heat-resistant material and provided with first and second terminals 13a and 13b for conducting electricity is formed. These gate electrodes 11g and 13g can be formed based on the same idea as the gate electrode 35 described in the first embodiment. In FIG. 6, the second terminal 11 for energization is used.
Although b and 13b are shown separately, they may be common terminals.

Next, after the above-described first annealing step in the process of manufacturing the first and second field-effect transistors 11 and 13 is completed, the vicinity of the gate electrodes 11g and 13g of each of these transistors is determined. As described in the first embodiment, impurities are separately introduced into the semiconductor substrate portion.

In the bias circuit 10x, the first field-effect transistor 11 has first and second terminals 11a,
11b, the channel region of the transistor is locally annealed.
1 changes its electrical characteristics. Specifically, the first field-effect transistor 11 changes to a state where current can easily flow. Then, the voltage output from the connection point of the two transistors 11 and 13, that is, the voltage obtained by dividing the voltage input from the power input terminal 10 a by the two transistors 11 and 13 is increased. Therefore, the bias voltage output from the bias circuit 10x can be increased. on the other hand,
When current is supplied to the second field effect transistor 13 via the first and second terminals 13a and 13b to locally anneal the channel region of the transistor, the electrical characteristics of the second field effect transistor 13 change. Specifically, the second field-effect transistor 13 changes to a state where current can easily flow. Then, the voltage output from the connection point of both transistors 11 and 13, that is, the voltage obtained by dividing the voltage input from power supply input terminal 10 a by both transistors 11 and 13 becomes low. Therefore, this bias circuit 10x
Can be adjusted to a lower side.

Therefore, according to the method of manufacturing a semiconductor device, it is understood that the bias voltage can be adjusted even after the semiconductor device is manufactured.

4. Fourth Embodiment Next, an embodiment will be described in which the semiconductor element is a semiconductor element including a resistor formed of an impurity-doped region. This will be described with reference to FIG. FIG. 7 is a cross-sectional view focusing on a resistor portion formed of an impurity introduction region. However, hatching indicating a cross section is omitted.

An impurity is introduced into a predetermined portion of, for example, a GaAs substrate as the semiconductor substrate 81 by, for example, an ion implantation method. Thus, an impurity introduction region 83 for forming a resistor is formed in the semiconductor substrate 81. Next, by a known method, annealing is performed at a temperature of several hundred degrees to several hundred degrees for a predetermined time (several seconds to several hours) to activate the impurity introduction region 83.

Next, the activated impurity introduction region 8
Ohmic electrodes 85 are formed on both ends of the third electrode 3 respectively.

Next, the activated impurity introduction region 8
Further, impurities are further introduced into at least a part of 3. As a result, the second impurity introduction region 87 is
3 are formed. The reason for forming the second impurity-introduced region 87 is that such a method can increase the resistance value fluctuation of the resistor in the subsequent local annealing.

Next, the activated impurity introduction region 8
A wiring 91 made of a heat-resistant material and provided with first and second terminals for energization is formed on the insulating film 89 via an insulating film 89. Note that, in the case of FIG. 7, the wiring 91 is formed along a direction perpendicular to the paper surface. Therefore, the first and second terminals for energization are not shown in FIG. 7 because they are located in a direction perpendicular to the plane of the paper.

The wiring 91 can be formed with the same idea as the gate electrode 35 described in the first embodiment.
Of course, this wiring 91 is formed in a state of being electrically insulated from the ohmic electrode 85. If the width of the wiring 91 is too wide, it is difficult for the wiring 91 to generate heat even when it is energized. To avoid this, a plurality of narrow wirings may be provided as the wiring 91 in some cases.

Here, the wiring 91 is formed on the impurity introduction region 83 via the insulating film 89, but a Schottky junction can be formed between the semiconductor substrate 81 and the wiring 91, and
If local annealing is not performed or a state where the Schottky barrier voltage is exceeded does not occur when the semiconductor element is operated, the wiring 91 may be formed directly on the impurity introduction region 83.

In the case of the semiconductor device of the fourth embodiment, when the wiring 91 is energized to generate heat, the heat reaches the impurity introduction regions 83 and 87. Therefore, local annealing can be performed on impurity introduction regions 83 and 87. In particular, local annealing can be performed on the second impurity introduction region 87. When the local annealing is performed in this manner, the resistance values of the impurity introduction regions 83 and 87 for forming the resistors are lower than before the local annealing. Therefore, according to the method of the present invention, the resistance value of the resistor can be irreversibly adjusted.

5. Fifth Embodiment Next, an example in which the present invention is applied to a semiconductor device including two or more impurity-introduced regions for forming a voltage divider including two or more resistors will be described.

In this case, the impurity introduction regions 83 and 87, the ohmic electrode 85 and the wiring 9 described with reference to FIG.
Two or more resistors having 1 are formed on the semiconductor substrate 81 such that they are in series. FIG. 8 shows this as an equivalent circuit. However, FIG. 8 illustrates an example of a voltage divider composed of the first and second two resistors R1 and R2. Needless to say, this embodiment is simplified so that it can be understood. In addition, the first voltage between the power supply V and the ground
It is a diagram provided with a resistor R1 and a second resistor R2. In FIG. 8, reference numerals 91a and 91b denote first and second terminals for supplying current to the wiring 91.

In the case of the semiconductor device according to the fifth embodiment, when a current is applied to the wiring 91 on the first resistor R1 side to perform local annealing, the resistance value of the first resistor R1 decreases.
On the other hand, when current is supplied to the wiring 91 on the second resistor R2 side and local annealing is performed, the resistance value of the second resistor R2 decreases. Therefore, the voltage division ratio of the voltage divider composed of the first and second resistors R1 and R2 can be adjusted even after the semiconductor device is manufactured.

6. Sixth Embodiment In the above-described first to fifth embodiments, an example has been described in which a direct current is used as a current when a current is applied to the gate electrode 35 or the wiring 91 for local annealing. However, high-frequency power may be applied to the gate electrode 35 and the wiring 91. The sixth embodiment is an example. This will be described with reference to FIG. FIG. 9 is a diagram illustrating an example in which the channel region 33 of the field-effect transistor is locally annealed using high-frequency power. FIG. 9 is a plan view corresponding to FIG.

In the sixth embodiment, the gate electrode 1
01 is used as an input terminal for a gate voltage during normal operation, and as a high-frequency input terminal during local annealing. Further, the gate electrode 101
Is connected to the ground through a capacitor 103.

Note that the sheet resistance of the gate electrode 101 is ρ
(Ρ / □), when the dimension in the direction perpendicular to the direction in which the current flows through the gate electrode 101 is W, and the length in the direction in which the current flows through the gate electrode 101 is L, then ρ × L / W is It is preferable that the impedance is equal to the characteristic impedance of a line for transmitting high frequency to the terminal 101a.

In the semiconductor device according to the sixth embodiment,
When a DC voltage is applied to the gate electrode 101 to perform a normal operation, a desired voltage can be applied to the gate electrode 101 because the capacitor 103 is provided. On the other hand, when a high frequency is applied to the gate electrode 101 when performing local annealing, the high frequency flows to the ground through the capacitor 103. Accordingly, a current flows through the gate electrode 101, so that the gate electrode 101 can generate heat. Therefore, local annealing can be performed as in the case of the first embodiment.

In the case of the sixth embodiment, there is an advantage that one of the terminals for current supply can be grounded. Therefore, the number of terminals can be reduced as compared with the first embodiment.

Each invention of this application is not limited to the above-described embodiments, and many modifications and changes can be made.

For example, the present invention may be used as follows. As shown in FIG. 10, a voltage controlled oscillator (VCO) formed in a semiconductor integrated circuit is provided with a center frequency adjustment terminal 111 for adjusting a center frequency of an oscillation frequency range output from the VCO. Then, the bias voltage of the above-described bias circuit 10x is input to the center frequency adjustment terminal 111.

As is well known, the VCO is a device that outputs a signal having a frequency corresponding to the voltage input to the input terminal 113 from the output terminal 115. Then, in this VCO, in order to output a signal of a certain frequency F ₀ with respect to the center voltage in the variable range of the voltage input from the input terminal 113, the input voltage input to the VCO must be biased. Good. The bias circuit 10x connected to the VCO
Can be biased, thereby enabling the center frequency adjustment described above.

However, in order to enable the center frequency adjustment, the value of the bias voltage output from the bias circuit 10x must be a designed value. Even if the bias voltage deviates from the design value after manufacturing the bias circuit 10x, the bias circuit 10x can adjust the bias voltage by local annealing, which is convenient.

In each of the above embodiments, GaAs
Although the description has been mainly given of the case of the semiconductor element manufactured using the substrate, the inventions of this application can of course be applied to the semiconductor element manufactured using the silicon substrate, for example, a semiconductor element including a MOSFET and / or a diffusion resistor. .

Further, in each of the above embodiments, an example in which the impurity introduction region is irreversibly changed has been described, but the present invention is not limited to this. Annealing may be performed by rapidly raising and lowering the temperature of the gate electrode and the wiring to change the stress between the insulating film around the gate electrode and the wiring and the semiconductor substrate. In such a case, the threshold voltage and transconductance of the field effect transistor can be changed by the stress, and the resistance value of the resistor can be changed by the resistor. Even if the electrical characteristics of the semiconductor element are changed by the stress as described above, there is no practical problem as long as the relaxation time of the stress (therefore, the stabilized time of the changed electrical characteristic) is equal to or longer than the service life of the semiconductor element.

Further, in each of the embodiments described above, an example has been described in which a semiconductor element is formed on the semiconductor substrate itself. However, the semiconductor substrate according to the present invention comprises a semiconductor substrate and an epitaxial layer formed thereon. Of course, a substrate may be used.

[0080]

As is apparent from the above description, according to the invention of the local annealing method of this application, the local annealing method is manufactured by a manufacturing method including an impurity introducing step and a first annealing step for activating the impurity. Of the semiconductor element to be
In annealing separately after the first annealing step, it is preferable that:
A wiring made of a heat-resistant material is formed directly or through an insulating film: and the local annealing is performed by heating the wiring to such an extent that the wiring is energized to give an annealing effect locally. For this reason, a new method that can easily anneal the local portion of the semiconductor element is realized.

[Brief description of the drawings]

FIG. 1 is an explanatory diagram (part 1) of a first embodiment;
FIG. 4 is a manufacturing process diagram of a semiconductor element particularly when the local annealing method of the present invention is applied.

FIG. 2 is an explanatory diagram (part 2) of the first embodiment;
In particular, it is an explanatory diagram of a gate electrode.

FIG. 3 is a specific explanatory diagram of local annealing.

FIG. 4 is an explanatory diagram of an effect of local annealing.

FIG. 5 is an explanatory diagram of a second embodiment.

FIG. 6 is an explanatory diagram of the third embodiment, illustrating an example in which the present invention is applied to a bias circuit.

FIG. 7 is an explanatory diagram of the fourth embodiment, illustrating an example in which the invention is applied to a resistor.

FIG. 8 is an explanatory diagram of the fifth embodiment, illustrating an example in which the present invention is applied to a voltage divider.

FIG. 9 is an explanatory diagram of the sixth embodiment, illustrating an example in which local annealing is performed at a high frequency.

FIG. 10 is an explanatory diagram of another application example of the present invention;
It is explanatory drawing of the example applied to the center frequency adjustment of O.

FIG. 11 is a diagram specifically explaining a problem.

[Explanation of symbols]

31: semiconductor substrate 33: first impurity introduction region (for forming a channel region) 35: gate electrode 35a: first terminal for conduction 35b: second terminal for conduction 41: second impurity introduction region (source) Drain region formation) 49: Third impurity introduction region 81: Semiconductor substrate 83: Impurity introduction region (for resistor formation) 85: Ohmic electrode 87: Second impurity introduction region 89: Insulating film 91: Wiring 91a: 1st terminal for conduction 91b: 2nd terminal for conduction

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/812

Claims (17)

[Claims] A step of separately annealing a local portion of a semiconductor element manufactured by a manufacturing method including an impurity introducing step and a first annealing step for activating the impurity, after the first annealing step; In the local annealing method, a wiring made of a heat-resistant material is formed directly or via an insulating film on the local during the manufacturing process of the semiconductor element. A local annealing method wherein the wiring is heated to such an extent as to provide a desired annealing effect. 2. The local annealing method according to claim 1, wherein the local is an arbitrary p-type or n-type impurity introduction region in the semiconductor element. 3. The local annealing method according to claim 2, wherein after the first annealing step, an impurity is further introduced into at least a part of the impurity introduction region, and thereafter, the local annealing is performed. Characterized local annealing method. 4. A first impurity introducing step for introducing an impurity for forming a channel region of a field effect transistor into a semiconductor substrate; a step of forming a gate electrode of the field effect transistor on the semiconductor substrate; Manufacturing of a semiconductor device including a second impurity introducing step of introducing impurities for forming source / drain regions of the field effect transistor into a substrate, and a first annealing step of activating the introduced impurities. In the method, as the gate electrode, a gate electrode made of a heat-resistant material and provided with a first terminal and a second terminal for energization is formed, and after the first annealing step, the first electrode is formed on the gate electrode. And a current is applied through the second terminal to cause the gate electrode to generate heat so as to give a desired annealing effect to the channel region, thereby causing the channel region to be exposed. And Lumpur, a method of manufacturing a semiconductor device characterized by adjusting the electrical characteristics of the field effect transistor. 5. The method for manufacturing a semiconductor device according to claim 4, wherein after the first annealing step, an impurity is introduced into a portion of the semiconductor substrate near the gate electrode, and thereafter, the gate electrode is heated. A method for manufacturing a semiconductor device, wherein annealing is performed. 6. The method of manufacturing a semiconductor device according to claim 4, wherein a portion of the semiconductor substrate near the gate electrode is removed from a surface thereof to a depth smaller than a depth of the channel region, and thereafter, the gate electrode is heated. A method for manufacturing a semiconductor device, comprising performing all kinds of annealing. 7. A first impurity introducing step of introducing an impurity for forming a channel region of a field effect transistor into a semiconductor substrate; a step of forming a gate electrode of the field effect transistor on the semiconductor substrate; Manufacturing of a semiconductor device including a second impurity introducing step of introducing impurities for forming source / drain regions of the field effect transistor into a substrate, and a first annealing step of activating the introduced impurities. The method wherein the semiconductor element to be manufactured is a first and a second field effect transistor connected in series, wherein a connection point of these transistors is connected to a gate electrode of these transistors, and the connection point is Including a first and a second field-effect transistor in which a voltage from is used as a bias voltage for another circuit in the semiconductor device. In the method for manufacturing a semiconductor element, which is a body element, a gate electrode made of a heat-resistant material and provided with a first terminal and a second terminal for conduction is formed as a gate electrode of the first and second field-effect transistors. After the first annealing step, at least one of the gate electrodes of the first and second field-effect transistors is energized through the first and second terminals to connect the gate electrode to the channel. A method for manufacturing a semiconductor device, comprising: generating heat to such an extent that an annealing effect is given to a region, annealing the channel region, and adjusting the bias voltage. 8. The method for manufacturing a semiconductor device according to claim 7, wherein after the first annealing step, an impurity is added to a semiconductor substrate portion near a gate electrode of each of the first and second field-effect transistors. A method of manufacturing a semiconductor device, wherein the annealing is performed by causing the gate electrode to generate heat. 9. The method of manufacturing a semiconductor device according to claim 7, wherein a portion of the semiconductor substrate near a gate electrode of each of the first and second field-effect transistors is removed from a surface thereof to a depth smaller than a depth of the channel region. And thereafter performing annealing by causing the gate electrode to generate heat. 10. A method for manufacturing a semiconductor device, comprising: a step of introducing an impurity to form a resistor comprising an impurity introduction region in a semiconductor substrate; and a first annealing step of activating the introduced impurity. In the method, a wiring made of a heat-resistant material and provided with a first terminal and a second terminal for conducting electricity is formed directly or via an insulating film on the impurity introduction region, and after the first annealing step, Energizing the wiring through the first and second terminals to cause the wiring to generate heat so as to give an annealing effect to the impurity introduction region, to anneal the impurity introduction region, and to reduce the resistance of the resistor. A method of manufacturing a semiconductor device, comprising adjusting a value. 11. The method for manufacturing a semiconductor device according to claim 10, wherein an impurity is further introduced into the impurity introduction region after the first annealing step, and thereafter, the annealing is performed by causing the wiring to generate heat. A method of manufacturing a semiconductor device. 12. A method of manufacturing a semiconductor device, comprising: a step of introducing an impurity to form a resistor comprising an impurity introduction region in a semiconductor substrate; and a first annealing step of activating the introduced impurity. A method of manufacturing a semiconductor device, wherein the semiconductor device to be manufactured is a semiconductor device including two or more impurity introduction regions for forming a voltage divider including two or more resistors. Wirings made of a heat-resistant material and having a first terminal and a second terminal for conduction are formed on the impurity introduction region directly or via an insulating film, and after the first annealing step, these wirings are formed. Is supplied with electricity through the first and second terminals to generate heat to the extent that an annealing effect is exerted on the impurity introduction region, thereby annealing the impurity introduction region. A method of manufacturing a semiconductor device characterized by adjusting the division ratio of the divider. 13. The method of manufacturing a semiconductor device according to claim 12, wherein after the first annealing step, an impurity is further introduced into each of the two or more impurity regions, and thereafter, the wiring is heated. A method for manufacturing a semiconductor device, comprising performing all kinds of annealing. 14. A semiconductor device having a field-effect transistor, characterized in that the field-effect transistor has a gate electrode made of a heat-resistant material and having first and second terminals for conducting electricity as a gate electrode. Semiconductor element. 15. A first and a second field effect transistor connected in series, wherein said connection point is connected to each gate electrode, and a voltage from this connection point is used as a bias voltage. In a semiconductor device including first and second field-effect transistors, a gate terminal of each of the first and second field-effect transistors includes a first terminal and a second terminal made of a heat-resistant material for conducting electricity. A semiconductor device comprising: a gate electrode; 16. A semiconductor device provided with a resistor comprising an impurity introduction region on a semiconductor substrate, wherein a first terminal for conduction and a first terminal made of a heat-resistant material are provided directly or via an insulating film on the impurity introduction region. A semiconductor device comprising a wiring having two terminals. 17. A semiconductor device having two or more impurity introduction regions for forming a voltage divider composed of two or more resistors in a semiconductor substrate, wherein a direct or insulating film is formed on the two or more impurity introduction regions. A semiconductor device comprising a wiring made of a heat-resistant material and having a first terminal and a second terminal for conducting electricity.