JPH11261373A - Phase shifter, voltage control-type oscillation circuit, demodulation circuit and signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase shifter, a voltage control-type oscillation circuit and a demodulation circuit, which are suitable for making an integrated circuit, and to provide a signal processor using them by holding an input terminal with high impedance and making driving current corresponding to a phase signal whose phase differs from an input signal by 90 degrees flow from the input signal. SOLUTION: Two pairs of differential transistors Q1-Q2 and Q5-Q6 hold both ends of capacitors C14 and C15 to be high impedance and input signals Vin and -Vin are inputted to the differential pairs of transistors Q1 and Q2. Phase signals whose phases differ from the input signals Vin and -Vin by 90 degrees are generated. Current is made to flow out from an input/output terminal in accordance with the phase signal. Thus, a four terminal circuit network formed by connecting non-contact-type active inductance is connected to the capacitors C14 and C15 in parallel can be formed. Thus, resistances Re are connected like a way that sleeves are rolled up and a phase shifter can be constituted.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase shifter, a voltage control type oscillation circuit, a demodulation circuit and a signal processing device, for example, a radio receiver, a television receiver, a satellite broadcast receiver, and the like.
The present invention can be applied to a video tape recorder, a mobile communication device, and the like. According to the present invention, the input terminal and the like are held at high impedance, a phase signal having a phase different from that of the input signal by 90 degrees is generated, and a drive current corresponding to the phase signal is caused to flow out of the input signal, thereby achieving integration. We propose a phase shifter, a voltage controlled oscillator, and a demodulator suitable for circuitization, and a signal processing device using them.

[0002]

2. Description of the Related Art Conventionally, in a signal processing device such as a television receiver, a detection circuit and a demodulation circuit are constituted by using various phase shifters.

That is, FIG. 12 shows a television receiver,
AM (Amplitude Modulati) applied to radio receivers, etc.
FIG. 3 is a block diagram illustrating a synchronous detection circuit. This AM synchronous detection circuit 1 outputs, for example, A
The M-modulated signal S1 is supplied to the multiplier 2, where the output signal S2 of the voltage-controlled oscillator (VCO) 3 is multiplied. The low-pass filter (LPF) 4 outputs the output signal of the multiplier 2 with its band limited, and the voltage-controlled oscillation circuit 3 outputs the output signal S2 so that the output signal of the low-pass filter 4 becomes 0 level. Change the frequency. Thereby, the multiplier 2, the voltage control type oscillation circuit 3, the low-pass filter 4
Constitutes a PLL (Phase Locked Loop) circuit, and 90
An output signal S2 which is phase-synchronized with the AM modulation signal S1 is generated based on the phase difference.

The phase shifter 5 sets the phase of the output signal S2 to 9
0 degree, thereby changing the AM modulation signal S1 to 0 degree.
A reference signal S3 which is phase-synchronized by the phase difference and has a constant amplitude is generated. The multiplier 6 outputs the reference signal S3
And the AM modulation signal S1 to output a low-frequency component, thereby outputting an AM detection signal S4 obtained by envelope-detecting the AM modulation signal S1.

On the other hand, FIG. 13 shows a QPSK (Quadrature Pha) applied to a mobile communication device such as a mobile phone.
FIG. 4 is a block diagram illustrating a demodulation circuit.
The QPSK demodulation circuit 11 supplies a multiplier 12 with a QPSK modulated signal S11 output from, for example, an intermediate frequency circuit, where the signal is multiplied by an output signal S12 of a voltage controlled oscillator (VCO) 13. Low-pass filter (LPF) 14
Outputs the output signal of the multiplier 12 with its band limited, and the voltage-controlled oscillation circuit 13 varies the frequency of the output signal S12 according to the output signal of the low-pass filter 14. As a result, the multiplier 12, the voltage-controlled oscillation circuit 1
3. The low-pass filter 14 constitutes a PLL circuit, and 9
An output signal S12 that is phase-synchronized with the carrier of the QPSK modulated signal S11 is generated by the phase difference of 0 degrees.

[0006] The phase shifter 15 changes the phase of the output signal S12 by 45 degrees, whereby the QPSK modulated signal S11 is changed.
, And generates a reference signal S13 having a fixed amplitude with a phase difference of 45 degrees. The multiplier 16 has the reference signal S13 and the QPSK modulated signal S11.
To output a low-frequency component, thereby outputting a Q signal SQ obtained by demodulating the QPSK modulated signal S11 with reference to the Q axis.

The phase shifter 17 changes the phase of the output signal S12 by -45 degrees, thereby synchronizing the phase of the carrier of the QPSK modulated signal S11 with a phase difference of -45 degrees and having a constant amplitude. A reference signal S14 is generated.
The multiplier 18 multiplies the reference signal S14 by the QPSK modulation signal S11 and outputs a low-frequency component,
An I signal SI obtained by demodulating the QPSK modulated signal S11 with reference to the I axis is output.

On the other hand, FIG. 14 shows an FM (Frequency Modu) applied to, for example, sound detection of a television receiver.
FIG. 3 is a block diagram illustrating a detection circuit. The FM detection circuit 21 is a quadrature detection circuit, for example, an FM modulation signal S output from an intermediate frequency circuit.
21 is given to a band pass filter (BPF) 22.

Here, the band-pass filter 22 limits the band of the FM modulation signal S21 with respect to the carrier frequency f0 and outputs the resulting signal, so that the phase of the FM modulation signal S21 varies with the frequency of the FM modulation signal S21 with respect to the carrier frequency f0. A changed band limiting signal S22 is output. Phase shifter 23
Changes the phase of the FM modulation signal S21 by 90 degrees and outputs the same. The phase discrimination circuit 24 outputs the output signal S of the phase shifter 23.
23 and the band-limited signal S22,
An FM detection signal S24 whose signal level changes according to the frequency of the FM modulation signal S21 is output.

A phase shifter applied to various demodulation circuits in this manner is configured by an equalizer circuit configuration using a capacitor, a resistor, or the like, or by a biquad filter.

FIG. 15 is a block diagram showing a phase shifter using this biquad filter. The phase shifter 30 includes a first operational amplifier circuit 32 having a non-inverting input terminal connected to a positive signal source 31, and a second operational amplifier circuit 33 having an output of the operational amplifier circuit 32 input to an inverting input terminal. It is composed of The phase shifter 30 feeds back the output of the second operational amplifier circuit 33 to the inverting input terminals of the first and second operational amplifier circuits 32 and 33, and supplies a predetermined capacity capacitor to each of the operational amplifier circuits 32 and 33. Connect C1 and C2. Further, the phase shifter 30 connects the negative signal source 34 and the positive signal source 35 to the capacitors C1 and C2 of the first and second operational amplifier circuits 32 and 33, respectively. Thus, in the phase shifter 30, the transfer function is represented by the following equation. Here, gm1 and gm2 are the operational amplifier circuits 32
And 33 are transconductances, and S is a Laplace operator.

[0012]

(Equation 1)

[0013]

However, capacitors,
If a phase shifter having an equalizer circuit configuration such as a resistor is used, there is a problem that it is difficult to integrate such a demodulation circuit and a detection circuit into an integrated circuit and easily secure desired characteristics.

That is, the phase shifter having the equalizer circuit configuration
When integrated circuits are used, variations in characteristics cannot be avoided due to variations in resistance values and the like, and various adjustments are required to secure desired characteristics. Further, in the case where the amount of phase shift is adjusted by adjusting the inductance value, a change in Q cannot be avoided along with this, and deterioration of characteristics cannot be avoided due to a change in output level.

One way to solve this problem is to use a phase shifter using a biquad filter. However, a phase shifter using a biquad filter has a limited upper limit of the usable frequency due to two operational amplifier circuits. Therefore, when the frequency of the signal to be processed is high, there is a problem that it is difficult to apply.

Incidentally, a phase shifter using a biquad filter is limited in the operating frequency range by the GB product of the operational amplifier circuit. Offsets occur in phase and gain between outputs. Further, when the antenna is used near the upper limit of the operating frequency band, the output impedance cannot be ignored, and the Q also decreases.

Further, even when the operating frequency is low, by operating the two operational amplifier circuits 32 and 33 as integrators, it is inevitable to generate an offset voltage at the output Vout. There is a risk that security cannot be guaranteed. Further, in the case where signals are input and output by a differential input and a differential output with the circuits at the preceding and succeeding stages by forming an integrated circuit, two more operational amplifier circuits are added to form a circuit similar to that described in FIG. Therefore, there is a problem that the entire configuration is complicated.

The present invention has been made in view of the above points, and solves these problems at once to use a phase shifter and a demodulation circuit suitable for integration into a circuit, and use these phase shifters and demodulation circuits. The proposed signal processing device is proposed.

[0019]

According to the present invention, there is provided a phase shifter, a demodulation circuit using the phase shifter, and a signal processing apparatus using the phase shifter. Device, a pair of input / output terminals are provided with a first
And the second capacitor and the first and second resistors are connected, and the phase signal generating circuit holds the terminals of the first and second capacitors at high impedance and the first and second input terminals. 90 for the input signal of
First and second phase signals having different degrees of phase are generated, and a current source supplies driving currents corresponding to the first and second phase signals to a second and first input terminals, a second and a first, respectively. From the output end of

The present invention is applied to a voltage-controlled oscillation circuit, a demodulation circuit using the voltage-controlled oscillation circuit, and a signal processing device using the voltage-controlled oscillation circuit. And a feedback circuit for positively feeding back the output signal of the band-pass filter to the band-pass filter. Furthermore, in this bandpass filter,
The first and second input signals by the differential input from the feedback circuit are received by high impedance, and the first and second phase signals having phases different from each other by 90 degrees are respectively generated, and the first and second phase signals are added to the first and second phase signals. The driving current is controlled to flow out from the second and first input terminals, respectively, and the driving current is controlled.

Further, the present invention is applied to a demodulation circuit, a signal processing device using the demodulation circuit, the demodulation circuit is used as a band-pass filter for band-limiting and outputting a frequency-modulated signal, and a reference is made to an output signal of the band-pass filter. And a phase discrimination circuit for processing the frequency modulation signal. At this time, the band pass filter receives the frequency modulation signal by the differential input at high impedance, generates the phase signals of the differential output having a phase difference of 90 degrees with respect to the frequency modulation signal, Are caused to flow out of the modulation signal input terminals.

Holding by high impedance, the first
And a first phase signal having a phase difference of 90 degrees with respect to the input signal of the second input terminal, and a driving source corresponding to the first and second phase signals is generated by the current source. 2 and the first input terminal and the second and the first output terminals, when viewed from the first and the second input terminals and the first and the second output terminals, 90 As a result, currents having different phases flow, thereby forming a configuration in which an inductance is equally arranged between the input and output terminals.

The present invention is applied to a phase shifter, a demodulation circuit using the phase shifter, and a signal processing device using the phase shifter. In these phase shifters, a predetermined form is provided between a pair of input / output terminals. A ladder-type four-terminal network can be formed by connecting the first and second capacitors and the first and second resistors, and output an output signal having a phase difference of 90 degrees with respect to an input signal. Can be.

Further, the present invention is applied to a voltage-controlled oscillation circuit, a demodulation circuit using the voltage-controlled oscillation circuit, and a signal processing device using the voltage-controlled oscillation circuit. If the band-pass filter is formed by using a feedback circuit and the inductance is similar to the above-described configuration, and the first and second input signals by the differential input are received from the feedback circuit, An oscillation circuit using positive feedback can be configured. Further, at this time, by controlling the drive current flowing out from the second and first input terminals, the oscillation frequency can be varied by controlling the drive current. As a result, various modulation signals can be processed by selectively using the input signal and the phase signal as needed.

Further, the present invention is applied to a demodulation circuit, a signal processing apparatus using the demodulation circuit, and a demodulation circuit which limits a frequency-modulated signal in a band and outputs the signal. And a phase discriminating circuit for processing the frequency modulation signal.
If this bandpass filter is configured using the above-described inductance, the frequency modulation signal can be processed without using a phase shifter having a conventional configuration.

[0026]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(1) First Embodiment FIG. 1 is a connection diagram showing a phase shifter according to a first embodiment of the present invention. In this embodiment, the phase shifter 4
0 is applied in place of the phase shifter described above with reference to FIGS. 12 and 14, and is integrated with various signal processing circuits.

That is, the phase shifter 40 receives the differential inputs Vin and -Vin from the preceding signal processing circuit at the bases of the transistors Q1 and Q2, respectively. In this input circuit, the description of the DC bias is omitted. The transistors Q1 and Q2 are a differential pair of a high impedance input with an emitter follower circuit configuration, each having a collector connected to the power supply VCC, and having the emitter connected to the resistors R13 and R14.

Further, the other ends of the resistors R13 and R14 of the transistors Q1 and Q2 are connected by a capacitor C13, and both ends of the capacitor C13 are connected to the collectors of the transistors Q3 and Q4, respectively. These transistors Q3 and Q4 have current sources 41 and 4 as emitters.
2 are connected, and the emitters of these transistors Q3 and Q4 are connected by a resistor R15. As a result, the transistors Q1 and Q2 maintain their input terminals at high impedance and input signals Vin and -V at both ends of the capacitor C13.
A phase signal having a phase change of 90 degrees with respect to in is generated. Here, the capacity of the capacitor C13 is C1 / 2
It is. The resistances R13 and R14 and the resistance R15 are set to the resistance value R1.

The transistors Q1 and Q2 are connected to the transistor Q1 via capacitors C14 and C15, respectively.
5 and Q6 are commonly connected to the base, the collectors of these transistors Q5 and Q6 are connected to the power supply VCC, and the emitters of these transistors Q5 and Q6 are connected to the collectors of transistors Q3 and Q4 via emitter resistors R16 and R17, respectively. It is made to be connected.

As a result, the transistors Q5 and Q6 are
Together with the transistors Q1 and Q2, a high impedance input differential pair is formed. In the phase shifter 40, both ends of the capacitors C14 and C15 are held at high impedance by the differential pair of the transistors Q1, Q2, Q5 and Q6. These capacitors C14
, And both ends of C15 are assigned to input / output terminals of two terminals, respectively. The capacitance of the capacitors C14 and C15 is C2, and the resistances of the resistors R16 and R17
Is R1 which is equal to the resistances of the resistors R13 and R14.

In the transistors Q1 and Q2, both ends of the capacitor C13 are connected to the bases of the transistors Q7 and Q8 having the emitters connected to the current sources 43 and 44, respectively. The emitters of the transistors Q7 and Q8 are connected by the resistor R19. Connected to the output terminals of the transistors Q5 and Q6. This allows the phase shifter 40 to current-drive one ends of the capacitors C14 and C15, which are output ends, in accordance with the phase signal appearing at both ends of the capacitor C13.

Similarly, transistors Q1 and Q2
Has both ends of a capacitor C13 connected to the bases of transistors Q9 and Q10 having emitters connected to current sources 45 and 46, respectively. These transistors Q9
And Q10, the emitters are connected by a resistor R20, and the collectors are connected to the input terminals of the transistors Q1 and Q2, respectively. Thus, the phase shifter 40 drives the other ends of the capacitors C14 and C15, which are input ends, in accordance with the phase signal appearing at both ends of the capacitor C13. Note that these resistors R19 and R19
The resistance value of 20 is 2R2.

Further, in the phase shifter 40, the input terminal and the output terminal are connected in a crossing manner by a resistor Re.

In the above configuration, the differential inputs Vin and -Vin input from the preceding signal processing circuit are high-impedance input transistors Q1 and Q2, respectively.
And output to the output terminal via the capacitors C14 and C15, the other ends of which are also held at high impedance.

If the voltages across the capacitor C13 are set to VL and -VL, respectively, and Kirchhoff's theorem is applied to the transistor Q1 of the capacitor C13, the following equation can be obtained in the phase shifter 40. it can. Here, i1 is the current of the resistor R13, i2 is the current of the capacitor C13, and i3 is
This is the collector current of the transistor Q3, and i4 is the current of the resistor R17. Vout and -Vout are voltages at the output terminal.

[0037]

(Equation 2)

[0038]

(Equation 3)

[0039]

(Equation 4)

[0040]

(Equation 5)

Here, both ends of the capacitor C13 are connected to the bases of the transistors Q3 and Q4, and the emitters of the transistors Q3 and Q4 are connected by the resistor R15. expressed.

[0042]

(Equation 6)

By substituting the expressions (3) to (6) into the expression (2), the following relational expression can be obtained.

[0044]

(Equation 7)

By further rearranging the equation (7), the following relational equation can be obtained.

[0046]

(Equation 8)

Here, the bases of the transistors Q9 and Q10 are respectively connected to both ends of the capacitor C13, and a current iL1 represented by the following equation is caused to flow from the bases of the transistors Q2 and Q1 in accordance with the base voltage. Become.

[0048]

(Equation 9)

Here, by substituting equation (8) into equation (9),
The following relational expression can be obtained.

[0050]

(Equation 10)

Thus, the resistance Re and the capacitor C1
4. If it is assumed that C15 is not connected, the signal source V
transistors Q1 and Q1 from in and -Vin, respectively.
The impedance Z as viewed from the second side is expressed by the following equation, and the non-grounded active inductance Z (= C
1 * R1 * R2) are formed.

[0052]

[Equation 11]

Similarly, transistors Q7 and Q8 are
A base is connected to both ends of the capacitor C13, and output voltages −Vout and Vout are output in accordance with the base voltage.
A current iL2 represented by the following equation flows out of the output terminal t.

[0054]

(Equation 12)

By substituting equation (8) into equation (12), the following relational expression can be obtained.

[0056]

(Equation 13)

Thus, the resistance Re and the capacitor C1
4, C15 is not connected, the impedance Z when the transistor Q5 and the transistor Q6 are viewed from the output terminal is expressed by the following equation, and the non-grounded active inductance Z ( = C1 ・
R1 and R2) are formed.

[0058]

[Equation 14]

At the input / output terminals, which are the connection terminals of the non-grounded active inductance Z (= C1, R1, R2) thus formed, the transistors Q1, Q
2, Q5 and Q6, which are kept at high impedance and biased at a predetermined DC level,
4, C15 and the resistor Re are connected, so that the phase shifter 40 can be represented by the equalizer circuit shown in FIG.

Thus, the transfer function T between input and output is
(S) is represented by the following equation, whereby a secondary phase shifter that changes the phase of the output signal by 90 degrees with respect to the input signal can be configured. Here, L1 is SC1 · R
1 · R2.

[0061]

(Equation 15)

According to the above configuration, both ends of the capacitors C14 and C15 are held at high impedance by the two pairs of differential pair transistors Q1 and Q2, Q5 and Q6, respectively, and the differential pair transistors Q1 and Q2 are maintained.
Input signals Vin and -Vin to the input signal Vi.
A phase signal having a phase difference of 90 degrees with respect to n and -Vin is generated, and a current is caused to flow out of the input / output terminal in accordance with the phase signal, whereby a non-grounded active inductance is connected in parallel to the capacitors C14 and C15, respectively. A connected four-terminal network can be formed. Thereby, the phase shifter can be configured by connecting the resistor Re in a cross. At this time, it is possible to configure a phase shifter having desired characteristics without using an integrating circuit like a biquad filter, thereby preventing generation of an offset voltage. Therefore, the input signal can be processed with a high SN ratio by effectively avoiding the loss of the dynamic range as a whole.

Further, since there is no need to use an integrating circuit, the device can be operated at a low voltage, and the entire power consumption can be reduced accordingly.

Further, since it can be constituted only by the NPN type transistors, it is possible to prevent the deterioration of the frequency characteristic due to the use of the PNP type transistors as in the case of the biquad filter, and to apply the present invention to a demodulation circuit having a high frequency. Can be.

Further, the phase shifter can be constituted by the differential input and the differential output as a whole, so that the input and output to and from the signal processing circuit before and after the phase shifter can be simplified.
The ratio and stability can be improved.

Thus, an integrated circuit can be formed, a chip area can be reduced, and an integrated circuit can be formed by a simple configuration.

(2) Second Embodiment FIG. 3 is a connection diagram showing a phase shifter according to a second embodiment. In this phase shifter 49, a resistor Ri is connected to each input terminal.
n, and a resistor Ro at the output terminal.
ut is connected.

In this case, the equalizing circuit can be represented as shown in FIG. 4, and the transfer function F (S) is represented by the following equation.

[0069]

(Equation 16)

The transfer function F (S) in the equation (16) indicates a phase shifter when Rin = Rout = R and C2 / R
Since e = C2 / 2R, the phase shifter can be configured by Re = 2Rin.

The same effect as in the first embodiment can be obtained by the structure shown in FIG. Further, since the phase shifter can be inserted into the ladder type transmission network without a DC offset, the group delay characteristic (Group-Delay) can be corrected.

(3) Third Embodiment FIG. 5 shows a quadrature detection circuit according to a third embodiment of the present invention. For example, an FM modulation signal S51 output from an intermediate frequency circuit is output from the quadrature detection circuit. It is given to a band pass filter (BPF) 52.

Here, the band-pass filter 52 has a phase difference of 90 degrees with respect to the carrier signal of the FM modulation signal S51 by outputting the FM modulation signal S51 in a band-limited manner around the carrier frequency f0. For the signal, a band-limited signal S52 whose phase changes according to the frequency of the FM modulation signal S51 is output. Phase discrimination circuit 5
4 multiplies the FM modulation signal S51 by the band-limited signal S52 and outputs a low-frequency component, thereby obtaining a conventional configuration (FIG. 1).
The phase shifter in 4) is omitted, and an FM detection signal S53 whose signal level changes according to the frequency of the FM modulation signal S51 is output.

FIG. 6 is a connection diagram showing the band-pass filter 52. The band-pass filter 52 inputs the FM modulation signal S51 by differential input from the signal processing circuit of the preceding stage via the drive resistors R21 and R22, respectively.
Here, the FM modulation signal S51 is indicated by the differential input Vin and -Vin. The bandpass filter 52 receives the differential inputs Vin and −Vin at both ends of the capacitor C21. The capacitor C21 forms a parallel resonance capacitance,
The capacitance is set to the value Cd / 2 and the resistors R21 and R22
Is set to the resistance value Rd.

The transistors Q11 and Q12 are a high impedance input differential pair having an emitter follower circuit configuration, and include transistors Q13 to Q16 and a resistor R23.
R25, the capacitor C23, and the current sources 61 and 62 constitute a 90-degree phase shifter.

That is, the transistors Q11 and Q12
Has a collector connected to the power supply VCC and resistors R23 and R24 connected to the emitter. The other ends of the resistors R23 and R24 of the transistors Q11 and Q12 are connected by a capacitor C23. Further, the transistors Q11 and Q12 have both ends of the capacitor C23 connected to the collectors of the transistors Q13 and Q14, respectively, the current sources 61 and 62 connected to the emitters of the transistors Q13 and Q14, and the emitters of the transistors Q13 and Q14 connected to the resistors. The connection is made by R25. As a result, the transistors Q11 and Q12 hold the input terminals at high impedance, and generate phase signals having a phase change of 90 degrees with respect to the input signals Vin and -Vin at both ends of the capacitor C23. Here, the capacitor C23
Is C0 / 2. Also, resistors R23 and R24
Is set to the resistance value R0.

The transistors Q11 and Q12 have a capacitor C15 connected to the bases of transistors Q15 and Q16 having current emitters 63 and 64 connected to their emitters, respectively.
23 are connected at both ends, and the emitters of these transistors Q15 and Q16 are connected to the other transistors Q12 and Q12.
11 is connected to the bases of the transistors Q13 and Q14.

The resistor R25 connecting the emitters of the transistors Q13 and Q14 is connected to the resistors R23 and R2.
4 is set to a resistance value 2R0 which is twice the resistance value.

The transistors Q17 and Q18 have their emitters grounded by current sources 65 and 66, respectively,
26 connects the emitter. Further, the transistors Q17 and Q18 connect the emitters of the transistors Q15 and Q16 to the base, respectively.
Are connected to the bases of the transistors Q11 and Q12 through the collectors. Here, the resistance R26 is set to the resistance value 2R2.

The current variable circuit 68 includes a transistor Q17
, And the collector current of Q18 is each multiplied by K to flow out from the input terminal. Thereby, the transistors Q17 and Q1
8 is a capacitor C2 controlled by the current variable circuit 68.
The input terminal is current-driven according to the phase signal composed of the terminal voltage of No. 3.

In the configuration of FIG. 6, the FM modulated signal S51
Are input as differential inputs Vin and −Vin to the high impedance input transistors Q11 and Q12 via the resistors R21 and R22.

Here, the base voltages of the transistors Q11 and Q12 are VB and -VB, respectively, and the capacitor C23
Are set to VL and −VL, respectively, and Kirchhoff's theorem is applied to the transistor Q11 side of the capacitor C23, the bandpass filter 52 can obtain the following relational expression. Here, i5 is the current of the resistor R23, i6 is the current of the capacitor C23, and i7 is the collector current of the transistor Q14.

[0083]

[Equation 17]

[0084]

(Equation 18)

[0085]

[Equation 19]

Here, both ends of the capacitor C23 are connected to the bases of the transistors Q15 and Q16, and the emitters of the transistors Q15 and Q16 are connected to the transistors Q1 and Q11 connected to the other transistors Q12 and Q11.
The current i7 in the equation (17) is represented by the following equation by being connected to the bases of the Q4 and Q13.

[0087]

(Equation 20)

From these, the following relational expression can be obtained.

[0089]

(Equation 21)

By further rearranging the equation (21), the following relational equation can be obtained.
It can be seen that a 90-degree phase component obtained by integrating the base inputs of the transistors Q11 and Q12 appears at the voltages VL and -VL between the terminals 3. That is, the capacitor C2
A phase signal having a phase change of 90 degrees with respect to the input signals Vin and -Vin appears at both ends of the signal No. 3.

[0091]

(Equation 22)

Here, the transistors Q17 and Q18 are
The emitters of the transistors Q15 and Q16 are respectively connected to the base, and a K-fold value of the current iL expressed by the following equation flows out from both ends of the resistors R21 and R22 according to the base voltage.

[0093]

(Equation 23)

Here, by substituting equation (22) into equation (23), the following equation can be obtained.

[0095]

(Equation 24)

As a result, as shown in FIG.
It can be seen that a non-grounded active inductance Z (= K · C0 · R0 · R2) is connected to both ends of R1 and R12. Thus, the following relational expression can be obtained using the resistance value Rd of the resistors R21 and R22 and the capacitance Cd / 2 of the capacitor C21.

[0097]

(Equation 25)

As a result, the transistors Q11 and Q12
Terminal voltage VB at the output terminal connected to the base of
It can be seen that VB has bandpass outputs of the signal sources Vin and -Vin. Further, the signal sources Vin and -V
The impedance Z1 (FIG. 7) viewed from “in” is represented by the following equation.

[0099]

(Equation 26)

When these are arranged, it can be understood that the following relational expression can be obtained, whereby a low-pass output can be obtained by the output from both ends of the capacitor C23.

[0101]

[Equation 27]

Also, 1 of the denominator of the equations (25) and (27)
From the following terms, f0 and Q of this bandpass filter 52
Can be expressed by the following equation.

[0103]

[Equation 28]

[0104]

(Equation 29)

Thus, the current amplification factor K in the current variable circuit 68 can be varied to adjust the center frequencies f0 and Q. The current amplification factor K can be adjusted to change the center frequency f0 of the band-pass filter 52 to the frequency of the FM modulation signal S51. The carrier frequency is set, and the band-pass filter 52 changes the phase of the reference signal synchronized with the carrier signal by a phase difference of 90 degrees according to the frequency displacement of the FM modulation signal S51. Can be obtained.

Therefore, the FM signal S51 can be obtained by multiplying the output signal S52 by the FM modulation signal S51 in the phase discrimination circuit 54.

According to the configuration shown in FIG. 5, transistors Q11 and Q12 of a differential pair with a high impedance input
The FM modulation signal S51 (input signals Vin, -Vin) is input to the phase shifter to generate a phase signal obtained by changing the phase by 90 degrees with respect to the FM modulation signal S51, and the input signals Vin, -Vin according to the phase signal. By allowing the current iL to flow more, a non-grounded active inductance can be formed.

As a result, the FM modulation signal S51 is generated by the band pass filter using the active inductance.
Is supplied to the phase discrimination circuit 54 after band-limiting, the FM modulation signal S51 can be processed without using a phase shifter, and an FM detection circuit suitable for integration into an integrated circuit can be obtained.

That is, since the inductance can be taken into the IC circuit, elements that require adjustment of the inductance and the like are not required, so that an integrated circuit can be formed by a simple configuration and the time required for the adjustment can be shortened. Can be.

In particular, by using the present invention for an audio detection circuit and an AFC detection circuit of a television receiver, a radio receiver, and the like, it is possible to improve the performance by improving the deterioration of characteristics due to variations, and to simplify the overall configuration. And the substrate area can be further reduced.

Further, generation of an offset voltage can be prevented, and loss of a dynamic range can be effectively avoided as a whole, and an input signal can be processed with a high SN ratio. Further, since there is no need to use an integrating circuit, the operation can be performed at a low voltage, and the entire power consumption can be reduced accordingly.

Further, since it can be constituted only by the NPN type transistors, it is possible to prevent the deterioration of the frequency characteristic due to the use of the PNP type transistors as in the case of the biquad filter. A high Q can be easily obtained, and a filter can be constituted by differential input and differential output as a whole, so that input and output to and from a signal processing circuit before and after the filter can be simplified.

(4) Fourth Embodiment FIG. 8 is a block diagram showing an AM synchronous detection circuit according to a fourth embodiment of the present invention. This AM synchronous detection circuit 7
0 is applied to a television receiver, a radio receiver and the like. The AM synchronous detection circuit 70 supplies an AM modulation signal S71 output from, for example, an intermediate frequency circuit to a multiplier 72, where the AM signal S71 is multiplied by an output signal S72 of a voltage controlled oscillator (VCO) 73. The low-pass filter 74 outputs the output signal of the multiplier 72 in a band-limited manner, and the voltage-controlled oscillation circuit 73 receives the output signal of the low-pass filter 74 as the control signal VC, and outputs the output signals S72 and S7.
3 is varied. Thus, the voltage-controlled oscillation circuit 73, together with the multiplier 72 and the low-pass filter 74,
A PLL circuit is configured to generate output signals S72 and S73 that are phase-synchronized with the AM modulation signal S71 with phase differences of 90 degrees and 0 degrees, respectively.

The multiplier 76 outputs the output signal S73 and A
By multiplying the M-modulated signal S71 with the M-modulated signal S71, an AM detection signal S7 obtained by envelope detection of the AM modulation signal S71 is obtained.
4 is output.

FIG. 9 is a connection diagram showing the voltage control type oscillation circuit 73. In this voltage-controlled oscillation circuit 73, the same components as those of the band-pass filter 52 described above with reference to FIG. 6 are denoted by the corresponding reference numerals, and redundant description will be omitted.

That is, the voltage-controlled oscillation circuit 73
As shown in FIG. 10, a bandpass filter 80 using active inductance and a bandpass filter 8
And a feedback circuit 81 that feeds back an output signal of 0.

Here, in the band-pass filter 80, both ends of the capacitor C21 are set to the first oscillation output terminal by the differential output, and both ends of the capacitor C23 have a phase of 90 degrees with respect to the first oscillation output terminal. A different second oscillation output terminal is set. The band-pass filter 80 is configured the same as the band-pass filter 52 described above with reference to FIG. 6, except that the setting of the output terminal and the current variable circuit 82 are different. The current variable circuit 82 varies the current amplification factor K according to the control signal VC, and thereby varies the resonance frequency f0 of the bandpass filter 80.

The feedback circuit 81 connects the input terminal of the band-pass filter 80, which is also the first oscillation output terminal, to the power supply line VCC via drive resistors R21 and R22, thereby connecting this input terminal to the drive resistor R21. , R2
Terminate with a resistance value of 2. Further, the feedback circuit 81 drives the other output terminal by the oscillation output output from one of the first oscillation output terminals, and thereby outputs the output signal of the band-pass filter 80 to the band-pass filter. Positive feedback to 80.

That is, in the feedback circuit 81, the transistors Q31 and Q32 are connected to the current sources 83 and 84, respectively.
, An emitter follower circuit having an emitter as an emitter, receives an output signal of the band-pass filter 80 from a first oscillation output terminal as a base, and outputs an emitter output to transistors Q33 and Q34. These transistors Q3
3 and Q34 form a differential pair, each having a current source 85
And 86 in the emitter, and the emitter is connected by a resistor R31. Further, transistors Q33 and Q34
Returns the collector output to the input terminal opposite to the input terminal corresponding to the base input.

Here, the feedback amount in the feedback circuit 81 is set to a feedback amount sufficient to continuously output the oscillation output from the bandpass filter 80 stably.

Thus, the AM synchronous detection circuit 70 outputs the second oscillation output (VL) of the band-pass filter 80 to the multiplier 72 and the first oscillation output (V
By outputting B) to the multiplier 76, the AM modulation signal S71 is demodulated. At this time, the first and second oscillation outputs are input to a multiplier by a differential output, so that an integrated circuit is formed by a differential pair as a whole.

According to the configuration shown in FIG. 8, a band-pass filter using active inductance and a feedback circuit for positively feeding back the output signal of the band-pass filter constitute a voltage-controlled oscillation circuit. Receives a signal input by a differential input of a high impedance, generates a phase signal having a phase difference of 90 degrees, varies a current amplification factor, and allows a driving current corresponding to the phase signal to flow out from an input terminal. By configuring a filter, a voltage-controlled oscillation circuit suitable for integration into a circuit, A
An M detection circuit can be obtained.

That is, the AM modulation signal can be processed without using a phase shifter, so that an integrated circuit can be formed by a simple configuration and the time required for adjustment can be shortened. In addition, by using it for an audio detection circuit and an AFC detection circuit of a television receiver and a radio receiver, etc., it is possible to improve the performance by improving the deterioration of characteristics due to variations, and to simplify the entire configuration,
Further, the substrate area can be reduced.

Further, generation of an offset voltage can be prevented, loss of a dynamic range can be effectively avoided as a whole, and a video signal or the like can be processed with a high SN ratio. Also, since there is no need to use an integrating circuit,
The operation can be performed at a low voltage, and the entire power consumption can be reduced accordingly.

Further, since it can be constituted only by the NPN type transistors, it is possible to prevent the deterioration of the frequency characteristic due to the use of the PNP type transistors as in the case of using the phase shifter using the biquad filter. A higher Q can be easily obtained, and a filter can be constituted by differential input and differential output as a whole, so that input and output to and from a signal processing circuit before and after the filter can be simplified.

(5) Fifth Embodiment FIG. 11 shows a QP applied to a mobile communication device such as a mobile phone.
FIG. 3 is a block diagram illustrating an SK demodulation circuit. The QPSK demodulation circuit 90 supplies a QPSK modulation signal S91 output from the intermediate frequency circuit to a multiplier 92, where the QPSK modulation signal S91 is multiplied by a second oscillation output VL of the voltage controlled oscillation circuit 73. The low-pass filter 94 outputs the output signal of the multiplier 92 with its band limited, and the voltage-controlled oscillation circuit 73 inputs the output signal of the low-pass filter 94 as a control signal VC. Thereby, the multiplier 92, the voltage control type oscillation circuit 7
3. The low-pass filter 94 constitutes a PLL circuit, and outputs signals VB and VB which are phase-synchronized with the carrier S91 of the QPSK modulation signal by a phase difference of 0 degree and 90 degrees, respectively.
Generate L.

The adders 96 and 97 calculate the two output signals VB and VL to calculate an output signal φ45 which is phase-synchronized with the carrier S91 of the QPSK modulated signal by a phase difference of 45 degrees and 135 degrees, respectively. And φ
135 is generated.

The multiplier 98 outputs the output signal φ45 and Q
By multiplying by the PSK modulation signal S91 and outputting a low frequency component, the QPSK modulation signal S91 is referenced with respect to the Q axis.
Is output as a Q signal SQ. Multiplier 9
9 is an I signal SI obtained by multiplying the output signal φ135 by the QPSK modulation signal S91 and outputting a low-frequency component, thereby demodulating the QPSK modulation signal S91 with reference to the I axis.
Is output.

According to the configuration shown in FIG. 11, the voltage-controlled oscillation circuit described above with reference to FIG. By generating the output signals φ45 and φ135 with a phase difference of 135 degrees, a QPSK modulation signal can be demodulated without using a phase shifter, whereby a voltage-controlled oscillation circuit suitable for integration into an integrated circuit. A demodulation circuit using a voltage-controlled oscillation circuit can be obtained.

(6) Other Embodiments In the above-described fifth embodiment, the case where the QPSK modulated signal is demodulated has been described. However, the present invention is not limited to this, and the multi-level PSK modulated signal may be demodulated. The present invention can be widely applied to demodulation and also to demodulation of a phase modulation signal.

In the above-described embodiment, the case where the amplitude modulation signal, the frequency modulation signal, and the phase modulation signal are demodulated has been described. However, the present invention is not limited to this. Can be widely applied.

In the above-described embodiment, the case where the demodulation circuit is constituted by the voltage-controlled oscillation circuit has been described. However, the present invention is not limited to this, and is widely applied to various oscillation circuits such as FM sound sources. can do.

[0133]

As described above, according to the present invention, the input terminal and the like are held at a high impedance to generate a phase signal having a phase different from the input signal by 90 degrees, and the driving current corresponding to the phase signal is generated. Are output from the input signals, thereby obtaining a phase shifter, a voltage-controlled oscillation circuit, a demodulation circuit, and a signal processing device using these, which are suitable for integration into an integrated circuit.

[Brief description of the drawings]

FIG. 1 is a connection diagram showing a phase shifter according to a first embodiment of the present invention.

FIG. 2 is a connection diagram showing an equalization circuit of the phase shifter of FIG.

FIG. 3 is a connection diagram illustrating a phase shifter according to a second embodiment of the present invention.

FIG. 4 is a connection diagram illustrating an equalization circuit of the phase shifter of FIG. 3;

FIG. 5 is a block diagram illustrating an FM detection circuit according to a third embodiment of the present invention.

FIG. 6 is a connection diagram illustrating a bandpass filter applied to the FM detection circuit in FIG. 5;

FIG. 7 is a connection diagram showing an equalization circuit of the bandpass filter of FIG. 6;

FIG. 8 is a block diagram illustrating an AM detection circuit according to a fourth embodiment of the present invention.

FIG. 9 is a connection diagram illustrating a voltage-controlled oscillation circuit applied to the AM detection circuit of FIG. 8;

FIG. 10 is a block diagram of the voltage-controlled oscillation circuit of FIG. 9;

FIG. 11 is a block diagram illustrating a QPSK demodulation circuit according to a fifth embodiment of the present invention.

FIG. 12 is a block diagram showing a conventional AM synchronous detection circuit.

FIG. 13 is a block diagram showing a conventional QPSK demodulation circuit.

FIG. 14 is a block diagram showing a conventional FM detection circuit.

FIG. 15 is a block diagram showing a phase shifter using a biquad filter.

[Explanation of symbols]

1, 70... AM synchronous detection circuit, 2, 6, 12, 16,
18 Multiplier, 3, 73 Voltage-controlled oscillation circuit,
4, 14, 74, 94 ... low-pass filter, 5, 1
5, 17, 23, 30, 40, 49 ... phase shifter 11,
90... QPSK demodulation circuit, 21, 50... FM detection circuit, 22, 52, 80... Band-pass filter, 24.
... Phase discrimination circuit, L, L1 ... Inductance, Q1
Q34: Transistor, R13 to R31, Re, Ri
n, Rout: resistor, C1 to C23: capacitor
68, 82: current variable circuit, 81: feedback circuit

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Yoshihiro Murayama 6-35 Kita Shinagawa, Shinagawa-ku, Tokyo Inside Sony Corporation

Claims (12)

[Claims] A first capacitor connected to a first input terminal and a first output terminal; a second capacitor connected to a second input terminal and a second output terminal; A first resistor connected to an input terminal and a second output terminal of the first and second resistors; a second resistor connected to the second input terminal and a first output terminal; and a first resistor connected to the first and second capacitors. A phase signal generation circuit that holds each terminal at high impedance to generate first and second phase signals having a phase difference of 90 degrees with respect to the input signals at the first and second input terminals; And a drive current corresponding to the second phase signal flows out of the second and first input terminals, respectively.
A current source flowing out of the second and first output terminals. 2. The phase shifter according to claim 1, wherein the first and second input terminals have a drive resistance, and the first and second output terminals have a termination resistance. 3. A demodulation circuit for processing an input signal by a phase shifter and demodulating the input signal, wherein the phase shifter is a first capacitor connected to a first input terminal and a first output terminal. A second capacitor connected to a second input terminal and a second output terminal; a first resistor connected to the first input terminal and a second output terminal; and the second input. And a second resistor connected to the first and second output terminals, and each terminal of the first and second capacitors is held at a high impedance so that the input signal of the first and second input terminals Signal generating circuit for generating first and second phase signals having phases different from each other by 90 degrees, and driving currents corresponding to the first and second phase signals from the second and first input terminals, respectively. Along with the outflow,
A current source flowing out of the second and first output terminals. 4. A signal processing device for processing a desired signal by a phase shifter, wherein the phase shifter comprises: a first capacitor connected to a first input terminal and a first output terminal; A second capacitor connected to the input terminal and the second output terminal; a first resistor connected to the first input terminal and the second output terminal; a second capacitor connected to the second input terminal and the first output terminal; A second resistor connected to the output terminal, and holding each terminal of the first and second capacitors with high impedance, and having a phase of 90 degrees with respect to the input signal of the first and second input terminals. A phase signal generation circuit that generates different first and second phase signals, and a drive current corresponding to the first and second phase signals is caused to flow out of the second and first input terminals, respectively.
A current source flowing out of the second and first output terminals. 5. A voltage-controlled oscillation circuit comprising: a band-pass filter using an active inductance; and a feedback circuit that positively feeds back an output signal of the band-pass filter to the band-pass filter. Receiving first and second input signals by a differential input from a feedback circuit with high impedance;
A phase signal generation circuit that generates first and second phase signals having phases different from each other by 90 degrees with respect to the input signal, and driving currents corresponding to the first and second phase signals to the second and second phase signals, respectively. A voltage controlled oscillation circuit comprising: a current source flowing out from a first input terminal; and control means for controlling the drive current. 6. A demodulation circuit having a voltage-controlled oscillation circuit, wherein the voltage-controlled oscillation circuit includes a band-pass filter using an active inductance, and a feedback circuit that positively feeds back an output signal of the band-pass filter to the band-pass filter. The band-pass filter receives first and second input signals by differential input from the feedback circuit with high impedance, and the first and second
A phase signal generation circuit that generates first and second phase signals having phases different from each other by 90 degrees with respect to the input signal, and driving currents corresponding to the first and second phase signals to the second and second phase signals, respectively. A demodulation circuit comprising: a current source flowing out from a first input terminal; and control means for controlling the drive current. 7. A demodulation device for demodulating a desired modulation signal with reference to said first and / or second input signal and / or with reference to said first and / or second phase signal. Item 7. A demodulation circuit according to item 6. 8. The demodulation circuit according to claim 7, wherein said modulation signal is an amplitude modulation signal. 9. An arithmetic processing on the input signal and the phase signal to generate a reference signal having a desired phase difference with respect to the input signal, and demodulating a phase modulation signal based on the reference signal. The demodulation circuit according to claim 6, wherein 10. A signal processing device having a voltage-controlled oscillation circuit, wherein the voltage-controlled oscillation circuit includes a band-pass filter using active inductance, and a feedback that positively feeds an output signal of the band-pass filter to the band-pass filter. A first circuit and a second circuit, wherein the band-pass filter receives first and second input signals by a differential input from the feedback circuit with high impedance, and the first and second
A phase signal generation circuit that generates first and second phase signals having phases different from each other by 90 degrees with respect to the input signal, and driving currents corresponding to the first and second phase signals to the second and second phase signals, respectively. A signal processing device comprising: a current source flowing out from a first input terminal; and control means for controlling the driving current. 11. A demodulation circuit for demodulating a frequency-modulated signal, a band-pass filter for band-limiting and outputting the frequency-modulated signal, and a phase discrimination for processing the frequency-modulated signal based on an output signal of the band-pass filter. And a circuit for receiving the frequency-modulated signal by a differential input at high impedance, and for each of the frequency-modulated signals,
A phase signal generation circuit that generates a phase signal of a differential output having a phase difference of 0 degrees; and a current source that causes a drive current corresponding to the phase signal of the differential output to flow out from an input terminal of the frequency modulation signal. A demodulation circuit characterized by the above-mentioned. 12. A signal processing device for demodulating a frequency-modulated signal by a demodulation circuit, wherein the demodulation circuit performs band-limiting on the frequency-modulated signal and outputs the signal, and a signal output from the band-pass filter as a reference. A phase discrimination circuit for processing the frequency modulation signal, wherein the band-pass filter receives the frequency modulation signal by a differential input with high impedance, and receives 9
A phase signal generation circuit that generates a phase signal of a differential output having a phase difference of 0 degrees; and a current source that causes a drive current corresponding to the phase signal of the differential output to flow out from an input terminal of the frequency modulation signal. A demodulation circuit characterized by the above-mentioned.