JPH11260939A - Non-volatile semiconductor memory device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the data writing speed. SOLUTION: This is a non-volatile semiconductor memory device, using a mis-orientated substrate 10 which has a plurality of terraces 12 having crystallographocally smooth surfaces and having at least one step 11 located at the boundary part of the plurality of the terraces 12. In this case, the step 11 is formed substantially vertically with respect to the channel direction in the vicinity of a drain region 22. Hot electrons, which are injected into a floating gate 15 from the channel region through the step 11, are increased, and the data writing speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a nonvolatile semiconductor memory device and a method for manufacturing the same.

[0002]

2. Description of the Related Art A flash EEP is used as a nonvolatile semiconductor memory device capable of electrically writing and erasing information.
ROMs are well known. Hereinafter, a conventional flash type EEPROM will be described with reference to FIGS. 1 (a) and 1 (b).
M will be described. FIG. 1A is an enlarged cross-sectional view illustrating a local region near the drain region of the EEPROM.
FIG. 1B is a plan layout diagram showing the overall arrangement of the source / drain region and the channel region.

This EEPROM has a tunnel insulating film 54 and a floating gate 5 formed on a single crystal silicon substrate 51.
5, a gate insulating film 56 and a control gate 57, a source region 58 and a drain region 59 formed of an n ⁺ -type impurity diffusion layer formed on the silicon substrate 51, and a channel region located therebetween. Control gate 57
By applying a predetermined voltage to the silicon substrate 51
A channel 60 is formed in the vicinity of the interface between the semiconductor device and tunnel insulating film 54. When a potential higher than the potential of the source region 58 is applied to the drain region 59, carriers (electrons) in the channel 60 are accelerated along the direction 53 due to a horizontal and horizontal potential gradient formed near the substrate surface. A part thereof becomes hot electrons 52 and is injected into the floating gate 55. According to such a flash EEPROM,
Data writing is realized by injecting hot electrons 52 in the channel 60 into the floating gate 55. Further, data erasing is realized by applying electrons to the source region 58 or the drain region 59 by applying a high voltage to the source region 58 or the drain region 59.

Since the threshold voltage of the transistor operation changes depending on whether or not electrons are accumulated in the floating gate 55, the data reading detects the magnitude of the current flowing between the source region 58 and the drain region 59. This is made possible by:

[0005]

SUMMARY OF THE INVENTION The above-mentioned flash type EE
The data writing speed of the PROM is at least two orders of magnitude lower than the data writing speed of the DRAM. Comparing the characteristics of a typical flash memory and a DRAM, in the case of a flash EEPROM, "writing time: 10 μs,
In the case of a DRAM, there is a difference between "read time: 100 ns, no holding power required" and "write time: 70 ns, read time: 70 ns, holding power required". According to the conventional flash EEPROM, the gate voltage is 9 V and the drain voltage is 4.
When the voltage is set to 5 V, it takes a long write time as long as 10 μs to obtain the difference (8 V) between the threshold voltages of the transistors required for data reading. For the purpose of improving such a slow writing speed to some extent, a gate voltage at the time of writing is currently set high. For these reasons, there is a problem that low-voltage operation / high-speed writing cannot be expected in the conventional nonvolatile semiconductor memory device.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to make it possible to efficiently apply hot electrons to a floating gate by utilizing irregularities intentionally formed at an interface between a semiconductor and a tunnel insulating film. It is intended to provide an implantable nonvolatile semiconductor memory device and a method of manufacturing the same.

[0007]

A nonvolatile semiconductor memory device according to the present invention comprises a semiconductor substrate, a channel region formed on the surface of the semiconductor substrate, and the semiconductor substrate having the channel region interposed therebetween. A source region and a drain region formed on the surface, a first insulating film formed on the surface of the semiconductor substrate, a floating gate formed on the first insulating film, and a floating gate formed on the floating gate. A non-volatile semiconductor memory device, comprising: a second insulating film, and a control gate capacitively coupled to the floating gate via the second insulating film, wherein the semiconductor substrate is a mis-orientation substrate; The surface of the semiconductor substrate includes a plurality of terraces having a crystallographically smooth surface, and at least one step located at a boundary between the plurality of terraces. Is substantially perpendicular to the channel length direction.

Preferably, the step is formed on the surface of the semiconductor substrate at a position closer to the drain region than to the source region.

Another non-volatile semiconductor memory device according to the present invention comprises a semiconductor substrate, a channel region formed on the surface of the semiconductor substrate, and a channel region formed on the surface of the semiconductor substrate with the channel region interposed therebetween. Source and drain regions, a first insulating film formed on the surface of the semiconductor substrate, a floating gate formed on the first insulating film, and a second insulating film formed on the floating gate. Membrane and
A control gate capacitively coupled to the floating gate via the second insulating film, wherein the surface of the semiconductor substrate is substantially perpendicular to a channel length direction. And the surface of the semiconductor substrate has a crystallographically smooth surface.

[0010] The surface of the semiconductor substrate may include a plurality of terraces having a crystallographically smooth surface, and at least one step located at a boundary between the plurality of terraces.

In one embodiment, at least a part of the groove is covered by the floating gate.

According to a method of manufacturing a nonvolatile semiconductor memory device of the present invention, a semiconductor substrate, a channel region formed on a surface of the semiconductor substrate, and a channel region formed on the surface of the semiconductor substrate with the channel region interposed therebetween. Source and drain regions, a first insulating film formed on the surface of the semiconductor substrate, a floating gate formed on the first insulating film, and a second gate formed on the floating gate. What is claimed is: 1. A method for manufacturing a nonvolatile semiconductor memory device comprising: an insulating film; and a control gate capacitively coupled to said floating gate via said second insulating film, wherein a mis-orientation substrate is provided as said semiconductor substrate. A plurality of terraces having a crystallographically smooth surface on the surface of the semiconductor substrate; and at least one terrace located at a boundary between the plurality of terraces.
And forming the source region and the drain region such that the step is substantially perpendicular to the channel length direction.

In one embodiment, the method includes forming the floating gate such that the floating gate covers at least a portion of the step.

Preferably, the step includes a step of forming the source region and the drain region so as to be closer to the drain region than the source region on the surface of the semiconductor substrate.

In a method of manufacturing a nonvolatile semiconductor memory device according to the present invention, a semiconductor substrate, a channel region formed on a surface of the semiconductor substrate, and a channel region formed on the surface of the semiconductor substrate with the channel region interposed therebetween. Source and drain regions, a first insulating film formed on the surface of the semiconductor substrate, a floating gate formed on the first insulating film, and a second gate formed on the floating gate. A method for manufacturing a nonvolatile semiconductor memory device, comprising: an insulating film; and a control gate capacitively coupled to the floating gate via the second insulating film, wherein a groove is formed on a surface as the semiconductor substrate. Providing a substrate; a plurality of terraces having a crystallographically smooth surface on the surface of the semiconductor substrate; and at least one terrace located at a boundary between the plurality of terraces.
And forming the source region and the drain region such that the trench is substantially perpendicular to the channel length direction.

In one embodiment, the method includes forming the floating gate so that the floating gate covers at least a part of the trench.

In one embodiment, the step of forming the step includes a step of rearranging surface atoms of the semiconductor substrate.

Preferably, the rearrangement of the surface atoms of the semiconductor substrate is performed by heating the semiconductor substrate in a vacuum.

In addition to the source region and the drain region, the semiconductor device may further include another source region and a drain region forming a channel along a direction perpendicular to the channel length direction.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a nonvolatile semiconductor memory device according to the present invention will be described with reference to the drawings. First Embodiment FIG. 2 shows a cross section of a main part of a nonvolatile semiconductor memory device according to the present embodiment. As shown in FIG. 2, the semiconductor memory device includes a p-type single crystal silicon substrate 10, a tunnel insulating film (first insulating film) 14 formed on the surface of the silicon substrate 10, and a tunnel insulating film 14 A floating gate 15 formed thereon, a capacitive insulating film (second insulating film) 16 formed on the floating gate 15,
A control gate 17 that is capacitively coupled to the floating gate 15 via the capacitive insulating film 16.

The silicon substrate 10 is a mis-orientation substrate. The surface of the silicon substrate 10 has a plurality of terraces 12 having crystallographically smooth surfaces and a plurality of terraces 12.
And the step (atomic step) 11 located at the boundary of. In the present embodiment, a silicon substrate whose surface is misoriented in the [110] direction by an angle θ from the (001) plane is used.

On the surface of the silicon substrate 10, a source region 21 and a drain region 22 made of an n ⁺ type diffusion layer are formed, and a region between them functions as a channel region. At least one step 1 in the channel region
1 is formed, the floating gate 15 completely covers the channel region, and the step 1 in the channel region is formed.
1 is formed.

The silicon substrate 10 having such a surface
Can be obtained by heating the mis-orientation substrate in a vacuum or by homoepitaxial growth of silicon. The density (the number per unit area) of the step 11 and the terrace 12 is defined by the misorientation angle θ of the silicon substrate 10 (the angle between the direction perpendicular to the substrate and the normal line of the terrace 12). In this embodiment, the step 11 is located closer to the drain region 22 than the source region 21 on the surface of the silicon substrate 10.

To obtain such a silicon substrate 10,
You can do as follows. First, RCA cleaning is performed on a silicon substrate to remove organic substances and the like from the surface of the silicon substrate. Next, after forming a thermal oxide film on the surface of the silicon substrate by wet oxidation, the thermal oxide film is removed with hydrofluoric acid or the like. Thus, the processed layer on the surface of the silicon substrate is removed. At this point, fine irregularities are irregularly formed on the surface of the silicon substrate.

Next, the silicon substrate is set in an ultrahigh vacuum chamber, and the pressure in the chamber is set to about 4 to 6 × 10 ^−9.
The pressure is reduced to Pa. Next, the silicon substrate is rapidly heated by a short-time heating method, and is heated for about 1 to 5 seconds to 1150 to 1
Raise the temperature to 250 ° C. Then, it is gradually cooled to a temperature close to room temperature. During the cooling process, silicon on the surface of the silicon substrate rearranges to form a (2 × 1) structure. Since the main surface of the silicon substrate is off from the (001) plane, a structure having an atomic step and a flat terrace is formed. These surface treatment methods are described in JP-A-9-51097. It should be noted that even if silicon atoms are rearranged on the outermost surface of the misorientation substrate by using a high-temperature treatment in a hydrogen atmosphere or a homoepitaxial growth technique instead of such a heat cleaning method, the same surface structure is obtained. Can be formed.

When the misorientation angle θ is 2 degrees and the conditions of the step forming process are controlled so that the step interval (terrace width) L is about 200 nm, the height of the formed step 11 becomes about 7 nm. Against this
When the misorientation angle θ is 5.7 degrees and the step interval (terrace width) L is about 200 nm, the height of the step 11 is about 20 nm. When the step interval (terrace width) L is about 200 nm, the channel length is about 40
If the length is set shorter than 0 nm (0.4 μm), a layout in which one step 11 crosses one channel region can be realized.

FIG. 3 is a graph showing how the electron density in the channel region is distributed according to the depth from the surface to the inside of the silicon substrate 10. A typical value of the depth P at which the electron density becomes maximum is 0.5 to 2.0 nm. The depth P changes depending on the temperature and the magnitude of the bias voltage. As can be seen from FIG. 3, since the depth P is smaller than the height of the step 11, electrons moving along the channel length direction sufficiently “feel” the step 11. According to the present embodiment, since the step 11 exists at a position near the drain region 22 while electrons move from the source region 21 to the drain region 22 shown in FIG. Electrons pass through the step 11 along the arrow and are easily injected into the floating gate 15. Therefore, the electron injection efficiency at the time of writing data is improved. Since most of the hot electrons are formed near the drain region 22, if the position of the step 11 is too close to the source region 21, the improvement of the electron injection efficiency becomes insufficient. To improve the electron injection efficiency, it is preferable that at least one step 11 is located near the drain region 22.
Step 11 does not need to cross the channel linearly, and may have a complicated planar pattern.

The formation process of step 11 is performed by using the floating gate 1
5 is performed before the forming step and the element isolation forming step. Therefore, after the step 11 is formed on the surface of the silicon substrate 10, an active region and an element isolation region are defined in accordance with the position, and then the floating gate 15 is patterned. For example, in a lithography process for forming a resist pattern defining an active region, when matching the position of step 11 with the position of the active region in a predetermined relationship, the position of step 11 is observed by an atomic force microscope or the like. .

Next, a method of manufacturing the apparatus shown in FIG. 2 will be described.

First, a silicon substrate 10 having a surface as shown in FIG. 2 is prepared. Next, the tunnel insulating film 14 is formed on the silicon substrate 10 by using a thin film forming method such as a normal thermal oxidation method or a chemical vapor deposition (CVD) method. In the present embodiment, a 10-nm-thick tunnel insulating film 14 is formed on the surface of the silicon substrate 10 by heat-treating the silicon substrate 10 at a temperature of about 750 ° C. in an electric furnace in a dry oxygen atmosphere. Thereafter, an annealing process is performed in dry nitrogen to remove oxide film defects such as pinholes from the tunnel insulating film 14.

Since the above-mentioned thermal oxidation reaction occurs at the SiO ₂ / Si interface as in the case of the normal thermal oxidation, the SiO ₂ / Si interface is changed to the silicon substrate 10 as the oxidation reaction proceeds.
Move inside the. Generally, as the thickness of the formed oxide film increases, the mechanism of the oxidation reaction changes from the initial process to the diffusion rule process through the reaction rule process, but in the case of the present embodiment, the formed oxide film is extremely thin. Therefore, the mechanism of the oxidation reaction does not go beyond the initial stage. One of the major differences between the nonvolatile semiconductor memory device of the present embodiment and the conventional nonvolatile semiconductor memory device is that the surface of the silicon substrate 10 has an atomically flat surface (terrace 12). .
For this reason, it is considered that a specific oxidizing species intrusion path hardly occurs in the thermal oxidation step, and the reaction between the oxidizing species and the silicon surface atoms proceeds uniformly. As a result, the tunnel insulating film 1
4 is improved, and the reliability and life of the device are improved.

Next, the first functioning as the floating gate 15
CVD polycrystalline silicon film (eg, 200 nm thick)
It is formed on the tunnel insulating film 14 by a method. afterwards,
By thermally oxidizing the surface of the polycrystalline silicon film, a capacitance oxide film 16 having a thickness of about 20 nm is formed on the polycrystalline silicon film. Finally, a second polycrystalline silicon film (for example, 200 nm thick) functioning as the control gate 17 is
Formed on the capacitive insulating film 16 by the D method. Note that the material of each gate is not limited to a polycrystalline silicon film. Also,
The capacitance oxide film 16 has an ON state in which a nitride layer is sandwiched between two oxide layers.
It may be formed from an O film. The gate structure shown in FIG. 2 is obtained by patterning these laminated structures by a known lithography technique and dry etching technique. Thereafter, impurity ions are implanted into the substrate 10 using the gate structure as a mask, whereby the source region 21 is formed.
And a drain region 22 are formed.

According to the apparatus of the present embodiment, the write operation is performed in a state where, for example, a voltage of 5 V is applied to the drain region 22, a voltage of 7 to 9 V is applied to the control gate 17, and a voltage of 0 V is applied to the source region 21 and the substrate 10. In this case, source region 2
The electrons emitted from the channel region 1 flow into the drain region 22 in the channel region.
While moving toward the horizontal direction, energy is obtained from the horizontal lateral electric field in the channel region, becomes hot electrons in the high electric field region in the channel region, and crosses the barrier between the semiconductor substrate 10 and the tunnel insulating film 14 to form a floating gate. 15 is injected. As described above, according to the apparatus of the present embodiment, the step 11 extending in the direction perpendicular to the channel length direction is performed.
Crosses the channel region. Therefore, step 1
1, the lower surfaces of the tunnel insulating film 14 and the floating gate 15 are located so as to cross the traveling direction of the hot electrons.
5 is efficiently injected.

Also, the electrons emitted from the source region 21 travel along the terrace 12 on the semiconductor surface, and reach step 11. Since the terrace 12 is smooth on an atomic scale, scattering is small, and electrons having high energy are easily generated.
This increases the number of electrons injected into the floating gate 15 beyond the energy barrier of the tunnel insulating film 14, and the injection efficiency is further improved.

According to this nonvolatile semiconductor memory device, the erasing operation is performed by controlling the control gate 17 at -6 to -8 V, the drain region 22 at 5 to 6 V, and the source region 21 and the substrate 10 at 0 V.
It is executed in a state where a voltage of V is applied. In this case, electrons in the floating gate 15 are extracted to the drain region 22 by a tunnel current flowing in the tunnel insulating film 14. The erasing operation is performed by controlling the control gate 17 at -6 to -8 V, the source region 21 at 5 to 6 V, the drain region 22 and the substrate 1.
It may be executed in a state where a voltage of 0 V is applied to 0. At this time, the extraction of electrons occurs at the source side edge of the floating gate 15. In this case, since the position of the electron injection during the writing operation is different from the position of the tunneling of the electrons during the erasing operation, there is obtained an effect that the tunnel insulating film 14 is less deteriorated and the reliability is excellent.

In this embodiment, one step 11 is formed in each channel region.
It may be formed in one channel region.

(Second Embodiment) FIGS. 4A to 4C
A second embodiment of the nonvolatile semiconductor memory device according to the present invention will be described with reference to FIG.

FIG. 4A is a perspective view of the silicon substrate 10 used in the nonvolatile semiconductor memory device of the present embodiment.
The silicon substrate 10 is a misorientation substrate made of single crystal silicon having a (001) surface. The surface of the silicon substrate 10 also has a step 11 and a terrace 12 formed by rearrangement of the outermost silicon atoms, similarly to the above-described silicon substrate 10.
As described above, the surface morphology of the step 11 and the terrace 12 can be obtained by heat cleaning in vacuum or homoepitaxial growth of silicon. In this embodiment, the steps 11 are randomly arranged, and a plurality of steps 11 cross the channel region.

FIG. 4B shows a cross section of a main part of the nonvolatile semiconductor memory device of the present embodiment. As shown in FIG. 4B, the semiconductor memory device includes a silicon substrate 10, a tunnel insulating film 14 formed on the surface of the silicon substrate 10, and a floating gate 15 formed on the tunnel insulating film 14. A capacitance insulating film 16 formed on the floating gate 15; and a control gate 17 capacitively coupled to the floating gate 15 via the capacitance insulating film 16.

As described above, the silicon substrate 10 is a mis-orientation substrate, and the surface of the silicon substrate 10 has a plurality of terraces 12 having crystallographically smooth surfaces.
And step 11 located at the boundary between the plurality of terraces 12.

FIG. 4C is a plan layout diagram of the nonvolatile semiconductor memory device of the present embodiment. This semiconductor storage device includes a channel region 18 formed on the surface of the silicon substrate 10 and a source region 21 and a drain region 22 formed on the surface of the silicon substrate 10 with the channel region 18 interposed therebetween. . Step 11 extends parallel to the Y direction.

Hereinafter, a method for manufacturing the semiconductor memory device according to the present embodiment will be described.

First, the silicon substrate 10 shown in FIG. 4A is prepared. By the method described in the first embodiment, a silicon substrate 10 that can be used in the present embodiment is obtained. However, in the present embodiment, the number and intervals of Step 11 do not need to be controlled as in the case of the first embodiment. This is because, in the present embodiment, a plurality of steps 11 may exist in each channel region at random intervals. In the case of the present embodiment, the formation of the active region and the element isolation region is performed without positioning the fine structure on the surface of the base substrate 10.

Next, a tunnel insulating film 14 is formed on the silicon substrate 10 by using a normal thin film forming method such as a thermal oxidation method or a CVD method. For example, a 10-nm-thick tunnel insulating film 14 is formed on the surface of the silicon substrate 10 by heat-treating the silicon substrate 10 at a temperature of about 750 ° C. in an electric furnace in a dry oxygen atmosphere. Thereafter, an annealing process is performed in dry nitrogen to remove oxide film defects such as pinholes from the tunnel insulating film 14.

Next, a polycrystalline silicon film (200 nm thick) functioning as the floating gate 15 is formed on the tunnel insulating film 14 by the CVD method. Then, floating gate 1
5 is thermally oxidized to form a 20 nm-thick capacitive oxide film 16 on the floating gate 15. Finally,
A polycrystalline silicon film having a thickness of 200 nm functioning as the control gate 17 is deposited on the capacitance insulating film 16 by a CVD method to form a multilayer film. Thus, the structure shown in FIG. 4B can be obtained. Thereafter, a gate structure is formed by patterning the multilayer film, and then a source region 21 and a drain region 22 are formed at the positions shown in FIG. 4C by ion implantation.

According to the apparatus of the present embodiment, the write operation is performed in a state where, for example, a voltage of 5 V is applied to the drain region 22, a voltage of 7 to 9 V is applied to the control gate 17, and a voltage of 0 V is applied to the source region 21 and the substrate 10. In this case, source region 2
The electrons emitted from the channel region 1 flow into the drain region 22 in the channel region.
While moving toward the horizontal direction, energy is obtained from the horizontal lateral electric field in the channel region, becomes hot electrons in the high electric field region in the channel region, and crosses the barrier between the semiconductor substrate 10 and the tunnel insulating film 14 to form a floating gate. 15 is injected. As described above, according to the device of the present embodiment, the direction (Y direction) perpendicular to the channel length direction (X direction)
Across the channel 19. Therefore, in step 11, the lower surfaces of the tunnel insulating film 14 and the floating gate 15 are located so as to cross the traveling direction of the hot electrons, and the hot electrons are efficiently injected into the floating gate 15 from that portion.

According to this nonvolatile semiconductor memory device, the erasing operation is performed by controlling the control gate 17 at −6 to −8 V, the drain region 22 at 5 to 6 V, and the source region 21 and the substrate 10 at 0 V.
It is executed in a state where a voltage of V is applied. In this case, electrons in the floating gate 15 are extracted to the drain region 22 by a tunnel current flowing in the tunnel insulating film 14. The erasing operation is performed by controlling the control gate 17 at -6 to -8 V, the source region 21 at 5 to 6 V, the drain region 22 and the substrate 1.
It may be executed in a state where a voltage of 0 V is applied to 0. At this time, the extraction of electrons occurs at the source side edge of the floating gate 15. In this case, since the position of the electron injection during the writing operation is different from the position of the tunneling of the electrons during the erasing operation, there is obtained an effect that the tunnel insulating film 14 is less deteriorated and the reliability is excellent. In the present embodiment, a relatively large number of steps are formed on the surface of the substrate, and a high-precision alignment between the step S and the active region is unnecessary during the lithography process for forming the active region. is there.

An impurity diffusion layer is added to the regions 23 and 24 shown in FIG. 4C, and this embodiment is modified so that they function as the second source region 23 and the second drain region 24. May be. In this case, a first channel (X direction) is formed by applying a voltage between the first source region 21 and the first drain region 22, and a voltage is applied between the source region 23 and the drain region 24. Is applied to form a second channel (Y direction). When a voltage is applied between the source region 21 and the drain region 22, as described above,
The electrons emitted from the substrate travel while feeling the large steps existing on the surface of the substrate 10 before reaching the drain region 22 along the X direction. On the other hand, when a voltage is applied between the source region 23 and the drain region 24, the electrons travel on the smooth terrace surface at the atomic level without feeling a step in the Y direction. Scattering is extremely small and its mobility is improved.
Therefore, when writing data, the source region 2
1 is applied between the drain region 22 and the drain region 22 to read data.
4 may be applied. Then, while improving the electron injection efficiency at the time of writing data, it is also possible to improve the sensitivity at the time of reading data.

(Third Embodiment) FIGS. 5A to 5C
Third Embodiment A nonvolatile semiconductor memory device according to a third embodiment of the present invention will be described with reference to FIG.

As shown in FIG. 5C, the device of this embodiment includes a p-type single-crystal silicon substrate 30, a tunnel insulating film 37 formed on the surface of the silicon substrate 30,
A floating gate 38 formed on the tunnel insulating film 37;
It includes a capacitance insulating film 39 formed on the floating gate 38, and a control gate 40 capacitively coupled to the floating gate 38 via the capacitance insulating film 39.

On the surface of the silicon substrate 30, a source region 41 and a drain region 42 formed of an n ⁺ type diffusion layer are formed, and a region therebetween functions as a channel region. At least one groove 31 is formed in the channel region, and the floating gate 38 is formed so as to completely cover the channel region and straddle the groove 31 in the channel region.

Next, a method of manufacturing this device will be described.

First, as shown in FIG. 5A, a linear groove 31 is formed on a silicon substrate 30 having a (001) surface by a fine processing technique such as lithography and dry etching. The width of the groove is, for example, 50 to 1
The depth is 50 nm, for example, 100 nm. Before the heat treatment described later, the surface 33 of the silicon substrate 30 and the bottom 32 of the groove 31 have "large irregularities on an atomic scale".

Next, the silicon substrate 30 is subjected to direct current heating cleaning in a vacuum (for example, 5 × 10 ⁻⁹ Pa),
As shown in FIG. 5B, a surface on which the groove bottom 34 and the step 36 are formed at the atomic level and smooth is obtained. This heat cleaning is achieved by performing a heat treatment in vacuum at, for example, about 600 ° C. for about 12 hours and then performing a heat treatment at 1300 ° C. for about 1 minute. During this heat cleaning step, a smooth surface at the atomic level is formed by the self-organizing process of surface atoms. That is, a step is formed on the silicon (001) surface by rearrangement of the outermost silicon atoms, and the step is migrated by the current. When the step reaches the groove 31, it is absorbed at the end of the wall, and as a result, the surface of the silicon substrate 30 has a smooth terrace at the atomic level and a step 3 existing between the terraces.
6. Such a phenomenon is caused by a method other than the direct current heating cleaning method, for example, an indirect heating method using a heater or the like. Silicon substrate 3
The number of steps 36 tends to increase as the misorientation angle of 0 increases. In the apparatus of the present embodiment, a normal silicon substrate may be used instead of the misorientation substrate. In that case, no steps are formed on the surface of the substrate, and the surface is covered with a smooth surface at the atomic level.

Next, as shown in FIG. 5C, a tunnel insulating film 37 is formed on the silicon substrate 30 by using a thin film forming method such as a normal thermal oxidation method or a chemical vapor deposition (CVD) method. To form In this embodiment, the silicon substrate 30 is heated at a temperature of about 750 ° C. in an electric furnace in a dry oxygen atmosphere.
Is heat-treated to form a 10-nm-thick tunnel insulating film 37 on the surface of the silicon substrate 30. Thereafter, oxide film defects such as pinholes are removed from the tunnel insulating film 37.
Annealing is performed in dry nitrogen to remove from the substrate. In FIG. 5C, the form of the surface of the silicon substrate 30 is not described in detail for simplification.

Next, a polycrystalline silicon film (200 nm thick) functioning as the floating gate 38 is formed on the tunnel insulating film 37 by the CVD method. Then, floating gate 3
8 is thermally oxidized to form a 20 nm-thick capacitive oxide film 39 on the floating gate 38. afterwards,
A polycrystalline silicon film having a thickness of 200 nm functioning as a control gate 40 is deposited on the capacitance oxide film 39 by a CVD method to form a multilayer film. By patterning this multilayer film, the laminated gate structure shown in FIG. 5C is obtained. Thereafter, a source region 41 and a drain region 42 are formed by an ion implantation method.

According to the device of the present embodiment, the write operation is performed, for example, by applying 5 V to the drain
7 to 9 V, and 0 V to the source region 41 and the substrate 30. In this case, electrons emitted from the source region 41 flow through the drain region 4 in the channel region.
While moving toward 2, it acquires energy from the horizontal lateral electric field in the channel region, becomes hot electrons in the high electric field region in the channel region, and floats across the barrier between the semiconductor substrate 30 and the tunnel insulating film 37. Gate 38
Is injected into. As described above, according to the device of the present embodiment, the groove 31 extending in the direction perpendicular to the channel length direction crosses the channel. For this reason, the lower surface of the tunnel insulating film 37 and the lower surface of the floating gate 38 are located in the groove 31 so as to cross the traveling direction of the hot electrons, and the hot electrons are efficiently injected into the floating gate 38 from that portion. In the present embodiment, since the region of the surface of the substrate 30 where the grooves 31 are not formed is formed by a surface smoothed at the atomic level, electron scattering due to unevenness is small and electron mobility is improved. doing. Therefore, the generation efficiency of hot electrons is high.

According to this nonvolatile semiconductor memory device, the erasing operation is performed by controlling the control gate 40 to -6 to -8 V, the drain region 42 to 5 to 6 V, and the source region 41 and the substrate 30 to 0 V.
It is executed in a state where a voltage of V is applied. In this case, electrons in the floating gate 38 are extracted to the drain region 42 by a tunnel current flowing in the tunnel insulating film 37. The erasing operation is performed by controlling the control gate 40 to -6 to -8 V, the source region 41 to 5 to 6 V, the drain region 42 and the substrate 3
It may be executed in a state where a voltage of 0 V is applied to 0. At this time, the extraction of electrons occurs at the edge of the floating gate 38 on the source side. In this case, since the position of the electron injection during the writing operation is different from the position of the tunneling of the electrons during the erasing operation, the tunnel insulating film 37 is less deteriorated, and the effect of excellent reliability is obtained.

In FIG. 5C, the drain region 42
Although a slight gap exists between the drain region 4 and the groove 31 in FIG.
2 and the groove 31 may overlap. Since the intensity peak of the horizontal lateral electric field is formed at the pn junction between the drain region 42 and the channel region, a lot of hot electrons are generated at and around the intensity peak. For this reason, the groove 31, particularly the side surface of the groove 31 closer to the source region 42, should be provided at or near the position where a large amount of hot electrons are generated. Further, the number of the grooves 31 is not necessarily limited to one, and a plurality of grooves may cross the channel region. However, in order to avoid scattering of electrons by the grooves and increase the energy of the electrons, it is considered preferable to selectively provide the single groove 31 in a region where a large amount of hot electrons are generated.

(Fourth Embodiment) Referring to FIG.
A fourth embodiment of the nonvolatile semiconductor memory device according to the present invention will be described.

As shown in FIG. 6, the apparatus of this embodiment comprises a p-type single crystal silicon substrate 43 and a silicon substrate 4.
3, a tunnel insulating film 44 formed on the surface of the tunnel insulating film 44, a floating gate 45 formed on the tunnel insulating film 44, a capacitive insulating film 46 formed on the floating gate 45, and floating through the capacitive insulating film 46. And a control gate 47 capacitively coupled to the gate 45.

On the surface of the silicon substrate 43, a source region 48 and a drain region 49 made of an n ⁺ type diffusion layer are formed, and a region therebetween functions as a channel region. A groove is formed so as to straddle the boundary between the channel region and the drain region 49, and the floating gate 45
The channel region is formed so as to completely cover the channel region and straddle the side surface of the groove on the channel side.

Next, a method of manufacturing this device will be described.

First, a groove is formed on the surface of the semiconductor substrate 43 by a fine processing technique such as lithography and dry etching. The width of the groove is, for example, 200 to 500 nm,
The depth is, for example, 100 nm. Before the heat treatment described later, the surface of the silicon substrate 43 and the bottom of the groove are
There is "a large irregularity on an atomic scale".

Next, the silicon substrate 43 is subjected to direct current heating cleaning in a vacuum. By this heating, the temperature of the silicon substrate 43 rises to about 1000 ° C., and a smooth surface at the atomic level is formed by the self-organizing process of surface atoms. That is, steps are formed on the silicon surface by rearrangement of the top surface silicon atoms, and the steps are migrated by the electric current. When the step reaches the groove, it is absorbed at the edge of the wall, so that
The surface of the silicon substrate 43 is composed of terraces that are smooth at the atomic level and steps that exist between the terraces. Such a phenomenon is caused by a method other than the direct current heating cleaning method, for example, an indirect heating method using a heater or the like. The number of steps tends to increase as the misorientation angle of the silicon substrate 43 increases. In the apparatus of the present embodiment, a normal silicon substrate may be used instead of the misorientation substrate. In that case, no steps are formed on the surface of the substrate,
The surface is covered with a smooth surface at the atomic level. In FIG. 6, the description of the steps is omitted.

Next, a tunnel insulating film 44 is formed on the silicon substrate 43 by using a normal thin film forming method such as a thermal oxidation method or a CVD method. In this embodiment, a 10-nm-thick tunnel insulating film 44 is formed on the surface of the silicon substrate 43 by heat-treating the silicon substrate 43 at a temperature of about 750 ° C. in an electric furnace in a dry oxygen atmosphere. Thereafter, oxide film defects such as pinholes are removed from the tunnel insulating film 4.
An annealing process is performed in dry nitrogen to remove from Step 4.

Next, a polycrystalline silicon film (thickness: 200 nm) functioning as the floating gate 45 is formed on the tunnel insulating film 44 by the CVD method. Then, floating gate 4
5 is thermally oxidized to form a 20-nm-thick capacitive oxide film 46 on the floating gate 45. afterwards,
A 200-nm-thick polycrystalline silicon film functioning as the control gate 47 is formed on the floating gate 46 by the CVD method, and a multilayer film is formed. By patterning this multilayer film, the gate structure shown in FIG. 6 is obtained. Thereafter, the source region 48 and the drain region 4 are formed by ion implantation.
9 is formed.

According to the device of this embodiment, the write operation is performed, for example, by applying 5 V to the drain
7 to 9 V, and 0 V to the source region 48 and the substrate 43. In this case, electrons emitted from the source region 48 flow through the drain region 4 in the channel region.
While moving toward 9, the device acquires energy from the horizontal lateral electric field in the channel region, becomes hot electrons in the high electric field region in the channel region, and floats across the barrier between the semiconductor substrate 43 and the tunnel insulating film 44. Gate 45
Is injected into. As described above, according to the device of the present embodiment, the groove extending in the direction perpendicular to the channel length direction crosses the boundary between the channel region and the drain region 49. For this reason, the lower surfaces of the tunnel insulating film 44 and the floating gate 45 are located on the side surfaces of the groove so as to cross the traveling direction of the hot electrons, and the hot electrons are efficiently injected into the floating gate 45 from that portion. Further, in the present embodiment, since the region of the surface of the substrate 43 where no groove is formed is smoothed at the atomic level, there is no electron scattering due to unevenness, and the mobility of electrons is improved. Therefore, the generation efficiency of hot electrons is high.

According to this nonvolatile semiconductor memory device, the erasing operation is performed by controlling the control gate 47 to -6 to -8 V, the drain region 49 to 5 to 6 V, and the source region 48 and the substrate 43 to 0 V.
It is executed in a state where a voltage of V is applied. In this case, electrons in the floating gate 45 are extracted to the drain region 49 by a tunnel current flowing in the tunnel insulating film 44. The erasing operation is performed by controlling the control gate 47 at -6 to -8 V, the source region 49 at 5 to 6 V, the drain region 48 and the substrate 4.
3 may be executed with a voltage of 0 V applied. At this time, the extraction of electrons occurs at the source-side edge of the floating gate 45. In this case, since the position of the electron injection during the writing operation is different from the position of the tunneling of the electrons during the erasing operation, the tunnel insulating film 44 is less deteriorated, and the effect of being excellent in reliability is obtained.

Since the intensity peak of the horizontal lateral electric field is formed at the pn junction between the drain region 49 and the channel region, a lot of hot electrons are generated at and around the intensity peak. Therefore, the channel side surface of the groove should be provided at or near a position where a large amount of hot electrons are generated.

In all of the above embodiments, the plane orientation is (0
Although the invention has been described with respect to the example using the silicon substrate of (01), the plane orientation is not limited to (001). For example, a (111) silicon substrate may be used.

[0072]

According to the nonvolatile semiconductor memory device of the present invention, the probability that channel hot electrons are injected into the floating gate in the step portion on the semiconductor surface increases, so that the data write time and the write voltage are reduced. Is realized, and the writing characteristics can be improved. Further, since the region other than the step on the semiconductor surface is smooth at the atomic level, the electron mobility in that region is improved, and the generation efficiency of hot electrons is improved. In addition, the traveling direction of electrons is set to 90 when writing and reading data.
If the rotation is performed by a degree, the data writing time can be shortened, and the data can be easily read.

[Brief description of the drawings]

FIG. 1A is a sectional view of a main part of a conventional nonvolatile semiconductor memory device, and FIG. 1B is a plan layout diagram of the device.

FIG. 2 is a sectional view of the first embodiment of the nonvolatile semiconductor memory device according to the present invention;

FIG. 3 is a graph showing a depth direction distribution of electrons in a channel region of the nonvolatile semiconductor memory device of the present invention.

FIG. 4A is a perspective view of a silicon substrate used in a second embodiment of the nonvolatile semiconductor memory device according to the present invention,
(B) is a sectional view of a main part of the second embodiment, (c).
FIG. 6 is a plan layout diagram of the second embodiment.

FIGS. 5A to 5C are cross-sectional views illustrating a method of manufacturing a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 6 is a sectional view of a fourth embodiment of the nonvolatile semiconductor memory device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 10 Silicon substrate 11 Step formed by rearrangement of top surface silicon atoms 12 Terrace formed by rearrangement of top surface silicon atoms 14 Tunnel insulating film 15 Floating gate 16 Capacitance oxide film 17 Control gate 18 Channel region 19 Channel 20 Oxidation Position of previous step 21 Source region 22 Drain region 23 Source region 24 Drain region 30 Silicon substrate having a (001) surface 31 Groove on a straight line formed by micromachining 32 Large irregularities at the atomic level at bottom of groove 33 Atomic level large irregularities on substrate surface 34 Atomic level smooth groove bottom 36 Substrate surface step after heat cleaning in vacuum 37 Tunnel insulating film 38 Floating gate 39 Capacitance oxide film 40 Control gate 41 Source region 42 Drain region 43 Channel Area 1 silicon substrate 52 channels in hot electron 53 channels in the hot electron in the running direction 54 the tunnel insulating film 55 a floating gate 56 capacitive insulating film 57 control gate 58 source region 59 drain region 60 channel

Claims (13)

[Claims] A semiconductor substrate; a channel region formed on a surface of the semiconductor substrate; a source region and a drain region formed on the surface of the semiconductor substrate with the channel region interposed therebetween; A first insulating film formed on the surface of the substrate, a floating gate formed on the first insulating film, a second insulating film formed on the floating gate, and a second insulating film formed on the second insulating film. A control gate that is capacitively coupled to the floating gate through the semiconductor substrate, wherein the semiconductor substrate is a misorientation substrate, and the surface of the semiconductor substrate is crystallographically smooth. A plurality of terraces each having a surface, and at least one step located at a boundary between the plurality of terraces, wherein the steps are substantially perpendicular to a channel length direction. Volatile semiconductor storage device. 2. The nonvolatile semiconductor memory device according to claim 1, wherein said step is formed at a position closer to said drain region than said source region on said surface of said semiconductor substrate. 3. A semiconductor substrate; a channel region formed on a surface of the semiconductor substrate; a source region and a drain region formed on the surface of the semiconductor substrate with the channel region interposed therebetween; A first insulating film formed on the surface of the substrate, a floating gate formed on the first insulating film, a second insulating film formed on the floating gate, and a second insulating film formed on the second insulating film. A control gate that is capacitively coupled to the floating gate through the semiconductor substrate, wherein the surface of the semiconductor substrate has a groove extending substantially perpendicular to a channel length direction. A nonvolatile semiconductor memory device, wherein a surface of the semiconductor substrate has a crystallographically smooth surface. 4. The semiconductor device according to claim 1, wherein the surface of the semiconductor substrate includes a plurality of terraces having a crystallographically smooth surface and at least one step located at a boundary between the plurality of terraces. 4. The nonvolatile semiconductor memory device according to 3. 5. The nonvolatile semiconductor memory device according to claim 3, wherein at least a part of said trench is covered by said floating gate. 6. A semiconductor substrate; a channel region formed on a surface of the semiconductor substrate; a source region and a drain region formed on the surface of the semiconductor substrate with the channel region interposed therebetween; A first insulating film formed on the surface of the substrate, a floating gate formed on the first insulating film, and a second gate formed on the floating gate;
What is claimed is: 1. A method for manufacturing a nonvolatile semiconductor memory device comprising: an insulating film; and a control gate capacitively coupled to said floating gate via said second insulating film, wherein a misorientation substrate is provided as said semiconductor substrate. Forming a plurality of terraces having a crystallographically smooth surface on the surface of the semiconductor substrate, and at least one step located at a boundary between the plurality of terraces; Forming the source region and the drain region so as to be substantially perpendicular to a direction. 7. The method according to claim 6, further comprising the step of forming the floating gate so that the floating gate covers at least a part of the step. 8. The non-volatile memory according to claim 7, wherein said step includes a step of forming said source and drain regions at a position closer to said drain region than said source region on said surface of said semiconductor substrate. Of manufacturing a nonvolatile semiconductor memory device. 9. A semiconductor substrate; a channel region formed on a surface of the semiconductor substrate; a source region and a drain region formed on the surface of the semiconductor substrate with the channel region interposed therebetween; A first insulating film formed on the surface of the substrate, a floating gate formed on the first insulating film, and a second gate formed on the floating gate;
A method for manufacturing a nonvolatile semiconductor memory device, comprising: an insulating film; and a control gate capacitively coupled to the floating gate via the second insulating film, wherein a groove is formed on a surface as the semiconductor substrate. Providing a substrate; forming a plurality of terraces having a crystallographically smooth surface on the surface of the semiconductor substrate; and forming at least one step located at a boundary between the plurality of terraces; Forming the source region and the drain region such that the groove is substantially perpendicular to the channel length direction. 10. The method according to claim 9, further comprising the step of forming the floating gate so that the floating gate covers at least a part of the trench. 11. The method for manufacturing a nonvolatile semiconductor memory device according to claim 6, wherein said step of forming a step includes a step of rearranging surface atoms of said semiconductor substrate. 12. The method according to claim 11, wherein the rearrangement of the surface atoms of the semiconductor substrate is performed by heating the semiconductor substrate in a vacuum. 13. The device according to claim 1, further comprising another source region and a drain region which form a channel along a direction perpendicular to the channel length direction, separately from the source region and the drain region. Non-volatile semiconductor storage device.