JPH11260056A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory device whose current consumption is smaller than that of a device of a conventional constitution of a method wherein a precharge auxiliary switch is employed. SOLUTION: The precharge circuit UPRi of an upper sense amplifier part USAi precharges the corresponding pair of bit lines UBi and XUBi to a power supply potential VDD. On the other hand, the precharge circuit LPRi of a lower sense amplifier unit LSAi precharges the corresponding pair of bit lines LBi and XLBi to a ground potential VSS. In a precharge operation, 1st and 2nd sense amplifier driving signal lines VSN and VSP are short-circuited by a precharge auxiliary switching means SWSH. With this constitution, charge is transferred between the bit line whose potential is shifted from the precharge potential VDD and the bit line whose potential is shifted from the precharge potential VSS and a current required for the precharge operation can be reduced significantly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor memory device, and more particularly, to a MOS dynamic memory (DRAM).

[0002]

2. Description of the Related Art FIG.
FIG. 2 is a diagram illustrating a configuration example of an OS dynamic memory (DRAM), and is a diagram illustrating a configuration of a sense amplifier unit and peripheral components thereof. As shown in FIG. 9, memory cells MC0 and MC1 each including a capacitor and a transistor are connected to a paired bit line bit and its inverted bit line xbit, respectively. A sense amplifier SA including a circuit PR, an NMOS pair transistor NP, and a PMOS pair transistor PP is provided. The bit line pair b
It and xbit are connected to a data line pair DT0 and DT1, which are signal lines for extracting data, via a column switch CLSW. In FIG. 9, for simplicity, only one memory cell is connected to each bit line.
In an actual device, a plurality of memory cells MC are naturally connected to each bit line. For example, 64M bit D
In the case of a RAM, usually, about 256 memory cells are connected to each bit line pair.

FIG. 10 is a timing chart showing the operation of the conventional semiconductor memory device shown in FIG. Bit line bi
t and xbit are equal to the potential VDD / 2 before the signal is read.
(VDD is a power supply potential). Next, the potential of the word line WL0 rises,
The signal charge stored in the memory cell MC0 connected to 0 is read out to the bit line bit, whereby the potential of the bit line bit slightly changes (ΔV).

Next, the potential of the first sense amplifier drive signal VSN is lowered, and then the second sense amplifier drive signal VSN is
By raising the potential of SP, the sense amplifier unit SA operates the bit line pair bi by the operation of the NMOS pair transistor NP and the PMOS pair transistor PP.
A small potential difference ΔV between t and xbit is amplified. Next, a rewrite operation is performed on the memory cell MC. Thereafter, the precharge circuit PR operates and the bit lines bit, xbit
Is charged until its potential becomes VDD / 2.

[0005]

In recent years, it has been desired to reduce the power consumption of a semiconductor memory device. However, a large amount of current consumption during the precharge operation is one of the reasons for the reduction in power consumption.
Are two major obstacles. There is also an approach of lowering the power supply voltage in order to reduce the operating current. In this case, however, the sense amplifier amplification time (the time required for the sense amplifier unit to amplify a signal) significantly increases as the power supply voltage decreases. Therefore, there is naturally a limit in reducing the power supply voltage.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to provide a semiconductor memory device that consumes less current during a precharge operation than in the past.

[0007]

Means for Solving the Problems In order to solve the above-mentioned problems, a solution taken by the invention of claim 1 is that a plurality of memory cells, a plurality of bit line pairs, and a plurality of bit line pairs are provided. And a plurality of sense amplifiers respectively provided for amplifying and outputting data read from the memory cell to the bit line pair. At least a part of the plurality of bit lines has a precharge potential. Is the first
And a second different potential.

According to the first aspect of the present invention, the bit line charge / discharge current is offset between the bit line precharged to the first potential and the bit line precharged to the second potential. As a result, the precharge current can be reduced as compared with the conventional case.

According to a second aspect of the present invention, in the semiconductor memory device according to the first aspect, a bit line precharged to the first potential and a second potential are precharged during a precharge operation. It is assumed that there is provided a precharge assisting means for transferring charges between the bit lines and assisting the precharge operation.

According to the second aspect of the present invention, during the precharge operation, the precharge auxiliary means causes the bit line pair to be precharged to the first potential and the bit line pair to be precharged to the second potential. Then, the electric charge is transferred, and the precharge operation is assisted, so that the current required at the time of the precharge operation can be reduced as compared with the related art. Thereby, the power consumption of the semiconductor memory device is greatly reduced.

According to a third aspect of the present invention, the semiconductor memory device of the second aspect includes first and second sense amplifier drive signal lines for transferring a signal for driving each of the sense amplifier units. , The precharge auxiliary means,
Precharge auxiliary switch means for controlling whether or not the first and second sense amplifier drive signal lines are short-circuited, and the first and second sense amplifier drive signal lines are controlled by the precharge auxiliary switch means during a precharge operation. A sense amplifier drive signal line is short-circuited, and data is transferred from a memory cell among the bit lines precharged to the first potential via the short-circuited first and second sense amplifier drive signal lines. A first bit line whose read-out potential has changed and a second bit line whose potential has changed by reading out data from a memory cell among the bit lines precharged to the second potential; It is assumed that charges are transferred between them.

Further, in the invention according to claim 4, the plurality of sense amplifier units in the semiconductor memory device according to claim 3 are:
Each of the transistors includes two conductive transistors connected in series between the corresponding bit line pair, the potential of the bit line connected to one transistor is applied to the gate of the other transistor, and The connection portion is composed of a first pair transistor connected to the first sense amplifier drive signal line and two other conductivity type transistors connected in series between the corresponding bit line pair, and is connected to one of the transistors. The applied potential of the bit line is applied to the gate of the other transistor, and the connection between the transistors includes a second pair transistor connected to the second sense amplifier drive signal line,
When the first and second sense amplifier drive signal lines are short-circuited by the precharge auxiliary switch means,
Between the first bit line and the second bit line, a short-circuited first and second sense amplifier drive signal line and a first sense amplifier portion corresponding to the first bit line are provided. Charges are transferred via one of the first and second paired transistors and the other of the first and second paired transistors included in the sense amplifier corresponding to the second bit line.

According to a fifth aspect of the present invention, in the semiconductor memory device of the first aspect, the number of bit lines precharged to the first potential and the number of bit lines precharged to the second potential Are almost the same.

[0014] In the invention of claim 6, according to claim 1,
The plurality of sense amplifier sections in the semiconductor memory device of the first aspect is composed of a plurality of
And a second sense amplifier group composed of a plurality of sense amplifier sections adjacent to each other on a layout, and a bit line corresponding to the first sense amplifier group has a precharge potential of the first potential. While the precharge potential of the bit line corresponding to the second sense amplifier group is set to the second potential.

According to a seventh aspect of the present invention, the semiconductor memory device according to the first aspect includes a plurality of data line pairs for transferring memory cell data amplified and output from the plurality of sense amplifiers, Each data line pair is precharged to a predetermined potential before memory cell data transfer, and the precharge potential is substantially the same as the potential at which the corresponding sense amplifier unit precharges the bit line pair. Shall be.

Further, in the invention according to claim 8, the data line pair in the semiconductor memory device according to claim 7 is a global bit line pair arranged substantially in parallel with the bit line pair.

According to a ninth aspect of the present invention, a plurality of memory cells, a plurality of bit line pairs, and a plurality of bit line pairs are provided for each bit line pair. As a semiconductor memory device having a plurality of sense amplifiers for amplifying and outputting output data, a bit line whose potential has changed from a precharge potential is selectively connected to a precharge node during a precharge operation. It has a selection precharge means for performing a charging operation.

According to another aspect of the present invention, a plurality of memory cells, a plurality of bit line pairs, and a plurality of bit line pairs are provided for each of the bit line pairs. A semiconductor memory device having a plurality of sense amplifiers for amplifying and outputting the output data, a global bit formed substantially parallel to the plurality of bit line pairs and transferring data output from the plurality of sense amplifiers; A plurality of global bit line pairs, each of which is connected to at least two or more sense amplifier units via switch means.
The open / close operation is performed so that the plurality of sense amplifier units are not electrically connected to the global bit line pair at the same time.

According to another aspect of the present invention, a plurality of memory cells, a plurality of bit line pairs, and a plurality of bit line pairs are provided for each bit line pair. A semiconductor memory device having a plurality of sense amplifiers for amplifying and outputting the output data, a global bit disposed substantially in parallel with the plurality of bit line pairs and transferring data output from the plurality of sense amplifiers; First and second amplifying and outputting the data transferred through the line pair group and the global bit line pair group, respectively.
And the first and second data amplifying means are different from each other in the number of bits of the output data.

According to a twelfth aspect of the present invention, in the semiconductor memory device of the eleventh aspect, the global bit line pair group is arranged over an arrangement area of a memory core including the memory cells and the sense amplifier unit. The first and second data amplifying means are provided on both ends of the global bit line pair group with the memory core arrangement region interposed therebetween.

According to a thirteenth aspect of the present invention, the semiconductor memory device according to the twelfth aspect includes a massively parallel processing device for performing multi-bit data processing. It is assumed that one output data of the data amplifying means is input.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention. In the semiconductor memory device according to the present embodiment shown in FIG. 1, a memory cell array having a plurality of memory cells MC is separately arranged on the layout into an upper side and a lower side in a word line WL direction. In FIG.
UBi and XUBi (i = 1 to n) are upper bit line pairs,
LBi and XLBi (i = 1 to n) are lower bit line pairs,
USAi (i = 1 to n) is an upper sense amplifier unit constituting the first sense amplifier group, and LSAi (i = 1 to n) is a lower sense amplifier unit constituting the second sense amplifier group. .

The upper sense amplifier unit USAi (i = 1 to 1)
n) includes a precharge circuit UPRi composed of three PMOSs, a first pair transistor UNPi, and a second pair transistor UPPi. Similarly, the lower sense amplifier units LSAi (i = 1 to n) each have a precharge circuit LP composed of three NMOSs.
Ri, a first pair transistor LNPi and a second pair transistor LPPi.

The precharge circuit UPLi of the upper sense amplifier circuit USAi and the precharge circuit LPRI of the lower sense amplifier circuit LSAi are both controlled by a precharge clock PPRE.
When the precharge clock PPRE becomes “H”, the precharge circuit UPRi activates the corresponding bit line pair UBi, X
UBi is precharged to the power supply potential VDD as the first potential, while the precharge circuit LPri precharges the corresponding bit line pair LBi and XLBi to the ground potential VSS as the second potential.

The first pair transistor UNPi included in the upper sense amplifier unit USAi is composed of two NMOSs connected in series between the corresponding bit line pair UBi and XUBi. A potential is applied to the gate of the other NMOS. First pair transistor L included in lower sense amplifier section LSAi
Similarly, NPi also has a corresponding bit line pair LBi, XLBi
It consists of two NMOSs connected in series between
The potential of the bit line connected to the MOS is applied to the gate of the other NMOS.

The second pair transistor UPPi included in the upper sense amplifier unit USAi is composed of two PMOs connected in series between corresponding bit line pairs UBi and XUBi.
The potential of a bit line made of S and connected to one PMOS is applied to the gate of the other PMOS. Similarly, the second pair transistor LPPi of the lower sense amplifier LSAi has a corresponding bit line pair LBi, XL
Bi consists of two PMOSs connected in series, and the potential of a bit line connected to one PMOS is
Applied to the S gate.

An NSA driver 11 and a PSA driver 12 for driving each of the sense amplifier units USAi and LSAi
Supplies a drive signal to each of the sense amplifier units USAi and LSAi via the first and second sense amplifier drive signal lines VSN and VSP in response to the drive control signal SEN. The first sense amplifier drive signal line VSN is connected to a connection between NMOSs in the first pair transistors UNPi, LNPi of each of the sense amplifier units USAi, LSAi. On the other hand, the second sense amplifier drive signal line VSP is connected to each sense amplifier unit USAi, LSA
i of the second pair transistors UPPi and LPPi are connected to the connection portions of the PMOSs.

As compared with the conventional semiconductor memory device, the number of elements constituting the memory cell array has not changed. The difference from the conventional semiconductor memory device is that the upper sense amplifier unit U
The precharge circuit UPi of SAi is formed of PMOS, and the precharge potential when precharging the corresponding bit line pair UBi and XUBi is VDD, while the precharge circuit LPLi of the lower sense amplifier LSAi is The precharge potential is VSS when precharging the corresponding bit line pair LBi, XLBi.

Further, a precharge auxiliary switch means SWSH for controlling whether or not the first and second sense amplifier drive signal lines VSN and VSP are short-circuited is greatly different from the conventional semiconductor memory device. ing. In the semiconductor memory device according to the present embodiment, the precharge auxiliary switch means SWSH, the first and second sense amplifier drive signal lines VSN and VSP, and the first and second sense amplifier drive signal lines VSN and VSP.
Pair transistors UNPi, UPPi, LNPi, L
Precharge auxiliary means is constituted by PPi. The first and second sense amplifier drive signal lines V
A precharge node is formed by SN and VSP, and a first pair transistor UNPi and a lower sense amplifier L included in an upper sense amplifier USAi.
The second pre-transistor LPPi of SAi constitutes a selective precharge unit.

FIG. 2 is a timing chart showing the operation of the semiconductor memory device according to the present embodiment shown in FIG. FIG.
The operation of the semiconductor memory device according to the embodiment will be described with reference to FIG. In FIG. 2, the upper bit line pair UBi,
Of the XUBi, "1" is applied as a signal to the bit line UBi.
While “0” is output as a signal to the bit line XUBi, while “1” is output as a signal to the bit line LBj of the lower bit line pair LBj and XLBj, and the bit line XLB
It is assumed that “0” is output as a signal to j.

First, before data is read from the memory cell, the upper bit line pair UB is
i, XUBi is precharged to VDD, and the lower bit line pair LBj, XLBj is precharged to VSS. NSA driver 11 and PSA driver 12
Does not operate, and the potentials of the first and second sense amplifier drive signal lines VSN and VSP are maintained at VDD / 2.

Next, data is read from the memory cell. The potential of the word line connected to the memory cell to be read is increased, and the signal charge stored in the memory cell is output to the corresponding bit line pair. At this time, the potential of the dummy word line is also increased, and the reference signal previously stored in the dummy memory cell is read out to the corresponding bit line pair. As a result, a small potential difference ΔV1 is generated between the upper bit line pair UBi and XUBi,
The small potential difference ΔV between the lower bit line pair LBj and XLBj
2 results.

Next, the minute potential difference generated in the bit line pair is amplified by the sense amplifier operation. First, the NSA driver 11 and the PSA driver 12 control the drive control signal SE.
N, and the potential of the first sense amplifier drive signal line VSN is changed to VSS by the operation of the NSA driver 11.
And the potential of the second sense amplifier drive signal line VSP becomes VD by the operation of the PSA driver 12.
It rises to D. The potential change of the first and second sense amplifier drive signals VSN and VSP causes the first pair transistor UNP of each sense amplifier unit USAi and LSAj to change.
i, LNPj and the second pair transistor UPPPi,
LPPj operates to perform a so-called sense amplifier operation, and a small potential difference between the bit line pair is amplified. As a result of such an operation, the potential of the upper bit line XUBi becomes VSS
And the potential of the lower bit line LBj rises to VDD.

After the data of the bit line pair selected by the column switch is output from the memory cell array,
Each bit line pair is precharged again. At this time, before the precharge operation by the precharge circuits UPRi and LPRj, the precharge auxiliary switch means SWSH is turned on to turn on the first and second sense amplifier drive signal lines V.
The precharge auxiliary operation is performed by short-circuiting SN and VSP.

The precharge auxiliary switch means SWSH is turned on to switch the first and second sense amplifier drive signal lines V
When SN and VSP are short-circuited, the potential is almost set to VDD / 2. Since the potentials of the first and second sense amplifier drive signal lines VSN and VSP are set by redistribution of electric charges, no power supply current is consumed at this time.

As a result, the first or second pair transistor and the first and second sense amplifier drivers of the sense amplifier section corresponding to the bit line between bit lines having a potential change from the precharge potential. Signal line VSN,
Charge transfer is performed via the VSP. In particular,
Charge transfer is performed between the bit line XUBi whose potential has dropped from the precharge potential VDD to VSS and the bit line LBj whose potential has risen from the precharge potential VSS to VDD.

As shown in FIGS. 3A and 3B, the potential of the bit line XUBi is changed from the precharge potential VDD to VSS.
, The first sense amplifier drive signal line V
From the SN, the NMOS of the first pair transistor UNPi
While charges are transferred via TN2, bit lines LBj
Of the second pair transistor LPPj since the potential of the second pair transistor LPPj rises from the precharge potential VSS to VDD.
A second sense amplifier drive signal line VSP via TP1
Is transferred to the device. As a result, the potential of the bit line XUBi becomes VDD when no current is supplied from the outside.
/ 2 while the potential of the bit line LBj is VDD
/ 2. In other words, the first or second sense amplifier unit of the corresponding sense amplifier unit
The precharge auxiliary operation is selectively performed through the paired transistors.

Finally, each precharge circuit UPRi, L
PRj performs the same precharge operation as in the prior art. When the precharge clock PPRE becomes “H”, the upper precharge circuit UPRi sets each bit line pair U
The precharge operation is performed until the potential of Bi, XUBi reaches the precharge potential VDD, and the lower precharge circuit LPRj performs the precharge operation until the potential of each bit line pair LBj, XLBj reaches the precharge potential VSS. .

As described above, according to the present embodiment, by performing the precharge assisting operation before the precharge circuit is operated, the current consumption can be significantly reduced as compared with the conventional case.

Further, according to the semiconductor memory device of the present embodiment, the power supply voltage can be set lower than in the prior art. FIG. 4 is a graph showing the relationship between the power supply voltage and the sensing time in the semiconductor memory device according to the present embodiment. FIG.
In the graph, the vertical axis represents the power supply voltage (V), and the horizontal axis represents the sensing time (ns). For comparison, the relationship between the power supply voltage and the sensing time in a conventional semiconductor memory device is also shown. As can be seen from FIG. 4, in the semiconductor memory device according to the present embodiment, the sense amplifier operates normally up to a lower power supply voltage as compared with the conventional one. This is because, when the power supply voltage is the same, the voltage applied between the source and the drain of the pair transistor included in the sense amplifier section is about twice that of the conventional one. Therefore, in the present embodiment, the power supply voltage can be set lower than before.

Combining the effect of normal operation even at this low power supply voltage and the above-mentioned effect of reducing current consumption, the current consumption of the entire semiconductor memory device can be reduced to about half that of the conventional semiconductor memory device.

In the present embodiment, the precharge auxiliary operation is performed using the first and second pair transistors and the first and second sense amplifier drive signal lines. May be provided separately.

(Second Embodiment) FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention. In the first embodiment, the sense amplifier groups having different precharge potentials are vertically separated from each other in the word line direction. However, in the semiconductor memory device according to the present embodiment shown in FIG. Are arranged separately in a direction perpendicular to the word line WL direction. Each component and its operation are the same as in the first embodiment.

According to the present embodiment, the precharge circuits having different conductivity types of the transistors can be arranged separately with the memory cell portion interposed therebetween, so that the layout is easier and the area is smaller than in the first embodiment. However, a smaller memory core can be realized.

(Third Embodiment) FIG. 6 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment. FIG.
FIG. 2 also shows components related to data read / write from the sense amplifier unit. As shown in FIG. 6, the first global bit line pair GRBU, XGRBU and the second global bit line pair are parallel to the bit line pairs UBi, XUBi (i = 1, 2) and LBi, XLBi (i = 1, 2). A bit line pair GRBL, XGRBL is formed, and a first global bit line pair GRBU, XGR
BU is connected to sense amplifier units USA1 and USA2 whose precharge potential is VDD via column switches UCL1 and UCL2 as switch means, respectively, and the second global bit line pair GRBL and XGRBL has a precharge potential of VSS. Sense amplifier units LSA1,
LSA2 and column switch LCL as switch means
1 and LCL2. In addition,
The global bit line refers to a data line formed in parallel with the bit line.

In the semiconductor memory device according to the present embodiment, the data read operation is performed as follows. That is, the data of the memory cell MC read out to the sense amplifier units USA1 and USA2 is stored in the column switch UCL.
1, the first global bit line pair GR via UCL2
The data of the memory cell MC read out to the sense amplifier units LSA1 and LSA2 while being read out to the BU and XGRBU are read out to the second pair of global bit lines GRBL and XGRBL via the column switches LCL1 and LCL2. First global bit line pair GRBU, X
The data of the memory cell MC to which the GRBU has been transferred is amplified by the first intermediate amplifier 33, and the data of the memory cell MC to which the second pair of global bit lines GRBU and XGRBU has been transferred is amplified by the second intermediate amplifier 34. The signals are amplified and output to the outside of the device.

The feature of the present embodiment is that the first global bit line pair GR
BU and XGRBU are precharged to the power supply potential VDD by the VDD precharge circuit 31, while the second global bit line pair GRBL and XGRBL are precharged to the ground potential VSS by the VSS precharge circuit 32. That is, each global bit line pair is precharged to a potential corresponding to the precharge potential of the connected sense amplifier unit. As described above, by matching the precharge potentials of the global bit line pair and the sense amplifier unit connected to each other, it is possible to minimize current consumption due to charging and discharging of the global bit line pair.

Although FIG. 6 shows a configuration in which two sense amplifiers are connected to one global bit line pair for simplification of description, it is needless to say that two sense amplifiers are connected to one global bit line pair. The number of the sense amplifiers may be any number.

In FIG. 6, first and second global bit line pairs GRBU, XGRBU and GRB
Although L and XGRBL are shown so as to avoid each sense amplifier section, this is to avoid complication of the drawing. In practice, the global bit line pair is arranged at any position including on the sense amplifier section. Is done.

(Fourth Embodiment) FIG. 7 is a diagram showing a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.
As shown in FIG. 7, the semiconductor memory device according to the present embodiment is provided with a Y decoder 41, and each column switch 44b of the first sense amplifier group 44a is
1, while each column switch 45b of the second sense amplifier group 45a is controlled by the Y decoder 4.
1 is controlled by the output Yj. by this,
Data output from the sense amplifier groups 44a and 45a can be read out via the global bit line pair group 46 without interfering with each other.

In the semiconductor memory device according to this embodiment, the first intermediate amplifier 42 as the first data amplifier and the second intermediate amplifier 42 as the second data amplifier are provided on both sides of the global bit line pair group 46. An intermediate amplifier 43 is provided. The first intermediate amplifier 42 has a 2-bit output, and the second intermediate amplifier 43 has a 4-bit output. With such a configuration, the semiconductor memory device according to the present embodiment can be operated as a two-port memory.

In FIG. 7, for simplification of the drawing,
All signal line pairs are indicated by a single line. For the sake of simplicity, the global bit line pair group 46 is shown avoiding the first and second sense amplifier groups 44a and 45a, but in an actual device, the global bit line pair group 46 is located at an arbitrary position including the sense amplifier section. , Are arranged in parallel with the bit lines.

FIG. 8 is a diagram showing a schematic configuration of a semiconductor chip using a memory core according to the present invention. As shown in FIG. 8, a memory core 5 comprising a memory cell and a sense amplifier unit
1 is arranged substantially at the center of the semiconductor chip 50, and a global bit line pair group 52 is wired in the vertical direction in the figure. A first intermediate amplifier 53 as first data amplifying means is provided at one end (lower side in the figure) of the global bit line pair group 52, and a data input between the memory core 51 and the outside of the semiconductor chip 50 is provided. The output is performed via the first intermediate amplifier 53 and the input / output unit 55. The output bit width of the input / output unit 55 is usually about 16 bits. At the other end of the global bit line pair group 52, a second intermediate amplifier 54 is provided as a second data amplifying means.
Data having a bit width of about 4 bits is input to the massively parallel processing device 56 and processed.

In an actual operation, data written to the memory core 51 from the outside of the semiconductor chip 50 via the first intermediate amplifier 53 is read out by the second intermediate amplifier 54 at a timing different from the writing, and is super-parallel. Processing device 5
6 is processed. The processing result data is written into the memory core 51 again, and the processing result data is read out of the semiconductor chip 50 at a different timing from the writing.

[0055]

As described above, according to the semiconductor memory device of the present invention, between the bit line precharged to the first potential and the bit line precharged to the second potential,
It becomes possible to cancel the bit line charge / discharge current. Further, during the precharge operation, the bit line pair precharged to the first potential by the precharge auxiliary means and the second
The electric charge is transferred between the bit line pair that is precharged to the potential and the precharge operation is assisted, so that the current required for the precharge operation is smaller than before and the power consumption is greatly reduced. Is done.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a configuration of a semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing an operation of the semiconductor memory device according to the first embodiment of the present invention shown in FIG.

FIGS. 3A and 3B are diagrams for explaining that current consumption can be reduced in the first embodiment of the present invention. FIGS.

FIG. 4 is a graph showing a relationship between a power supply voltage and a sensing time in the semiconductor memory device according to the first embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a semiconductor memory device according to a third embodiment of the present invention.

FIG. 7 is a diagram illustrating a configuration of a semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 8 is a diagram showing a schematic configuration of a semiconductor chip using a memory core according to the present invention.

FIG. 9 is a diagram illustrating a configuration example of a conventional semiconductor memory device.

FIG. 10 is a timing chart showing the operation of the conventional semiconductor memory device shown in FIG.

[Explanation of symbols]

MC memory cell UBi, XUBi, LBi, XLBi Bit line USAi, LSAi Sense amplifier section VDD Power supply potential (first potential) VSS Ground potential (second potential) SWSH Precharge auxiliary switch means VSN First sense amplifier drive signal Line VSP Second sense amplifier drive signal line UNPi, LNPi First pair transistor UPPi, LPPi Second pair transistor GRBU, XGRBU First global bit line pair GRBL, XGRBL Second global bit line pair UCL1, UCL2 LCL1, LCL2 Column switch (switch means) 42 First intermediate amplifier (first data amplifying means) 43 Second intermediate amplifier (second data amplifying means) 44b, 45b Column switch (switch means) 46 Global bit line versus 51 first intermediate amplifier memory core 52 global bit line pair group 53 (first data amplifying means) 54 second intermediate amplifier (second data amplifying means) 56 massively parallel processor

Claims (13)

[Claims] 1. A plurality of sense amplifiers provided for a plurality of memory cells, a plurality of bit line pairs, and each bit line pair, and amplifying and outputting data read from the memory cells to the bit line pair. A precharge potential of at least a part of the plurality of bit lines is set to first and second different potentials. apparatus. 2. The semiconductor memory device according to claim 1, wherein during a precharge operation, between a bit line precharged to said first potential and a bit line precharged to said second potential, A semiconductor memory device comprising a precharge assisting means for transferring a charge and assisting the precharge operation. 3. The semiconductor memory device according to claim 2, further comprising: first and second sense amplifier drive signal lines for transferring a signal for driving each of said sense amplifier units, wherein said precharge auxiliary means comprises: Precharge auxiliary switch means for controlling whether to short-circuit the first and second sense amplifier drive signal lines, and the first and second sense amplifiers are operated by the precharge auxiliary switch means during a precharge operation. A drive signal line is short-circuited, and data is read from a memory cell among the bit lines precharged to the first potential via the short-circuited first and second sense amplifier drive signal lines. Data is read from a memory cell among a first bit line that has been output and the potential has changed, and bit lines that are precharged to the second potential. A charge is transferred to and from a second bit line whose potential has changed. 4. The semiconductor memory device according to claim 3, wherein each of the plurality of sense amplifier units includes two one conductivity type transistors connected in series between corresponding bit line pairs, and one of the plurality of sense amplifier units is one of the transistors. The potential of the bit line connected to the first transistor is applied to the gate of the other transistor, and the connection between the transistors is connected to the first paired transistor connected to the first sense amplifier drive signal line; It consists of two other conductive transistors connected in series between the pair, the potential of the bit line connected to one transistor is applied to the gate of the other transistor, and the connection between the transistors is the second transistor. And a second pair transistor connected to the sense amplifier drive signal line of the precharge auxiliary switch means. Thus when the first and second sense amplifier drive signal line is short-circuited,
Between the first bit line and the second bit line, a short-circuited first and second sense amplifier drive signal line and a first sense amplifier portion corresponding to the first bit line are provided. Semiconductor, wherein charges are transferred through one of the first and second paired transistors and the other of the first and second paired transistors included in the sense amplifier corresponding to the second bit line. Storage device. 5. The semiconductor memory device according to claim 1, wherein the number of bit lines precharged to said first potential is substantially equal to the number of bit lines precharged to said second potential. A semiconductor memory device, comprising: 6. The semiconductor memory device according to claim 1, wherein the plurality of sense amplifier units include a first sense amplifier group including a plurality of sense amplifier units adjacent on a layout.
A second sense amplifier group including a plurality of sense amplifier units adjacent to each other on a layout, wherein a bit line corresponding to the first sense amplifier group has a precharge potential set to the first potential. On the other hand, the bit line corresponding to the second sense amplifier group
A semiconductor memory device, wherein the precharge potential is set to the second potential. 7. The semiconductor memory device according to claim 1, further comprising a plurality of data line pairs for transferring memory cell data amplified and output from said plurality of sense amplifier units, wherein each of said data line pairs is a memory cell data. A semiconductor memory device which is precharged to a predetermined potential before transfer, and the precharge potential is substantially the same as a potential at which a corresponding sense amplifier unit precharges a bit line pair. 8. The semiconductor memory device according to claim 7, wherein said data line pair is a global bit line pair arranged substantially in parallel with said bit line pair. 9. A plurality of memory cells, a plurality of bit line pairs, and a plurality of sense amplifiers provided for each bit line pair, for amplifying and outputting data read from the memory cells to the bit line pair. And a selection precharge means for performing a precharge operation by selectively connecting a bit line whose potential has changed from the precharge potential to a precharge node during a precharge operation. A semiconductor memory device characterized in that: 10. A plurality of memory cells, a plurality of bit line pairs, and a plurality of sense amplifiers provided for each bit line pair and amplifying and outputting data read from the memory cell to the bit line pair. A global bit line pair group formed substantially in parallel with the plurality of bit line pairs and transferring data output from the plurality of sense amplifier units. Each pair is connected to at least two or more sense amplifier units via switch means, and this switch means is opened and closed so that the plurality of sense amplifier units are not electrically connected to the global bit line pair at the same time. A semiconductor memory device which operates. 11. A plurality of sense amplifiers provided for a plurality of memory cells, a plurality of bit line pairs, and each bit line pair, and amplifying and outputting data read from the memory cells to the bit line pair. A global bit line pair group arranged substantially in parallel with the plurality of bit line pairs and transferring data output from the plurality of sense amplifier units; and the global bit line pair. First and second data amplifying means for amplifying and outputting the data transferred from the group, respectively, wherein the first and second data amplifying means have different numbers of bits of output data from each other. A semiconductor memory device characterized by the following. 12. The semiconductor memory device according to claim 11, wherein said global bit line pair group is arranged over an arrangement region of a memory core comprising said memory cell and a sense amplifier unit, and 2. A semiconductor memory device according to claim 2, wherein the data amplifying means is provided at both ends of the global bit line pair group with the memory core arrangement area interposed therebetween. 13. The semiconductor memory device according to claim 12, further comprising a massively parallel processing device for performing multi-bit data processing, wherein said massively parallel processing device is one of said first and second data amplifying means. A semiconductor memory device to which the output data of (1) is input.